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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
0007 
0008 #include <linux/types.h>
0009 #include <linux/completion.h>
0010 #include <linux/delay.h>
0011 #include <linux/phy/phy.h>
0012 #include <linux/phy/phy-dp.h>
0013 #include <linux/pm_opp.h>
0014 
0015 #include <drm/display/drm_dp_helper.h>
0016 #include <drm/drm_fixed.h>
0017 #include <drm/drm_print.h>
0018 
0019 #include "dp_reg.h"
0020 #include "dp_ctrl.h"
0021 #include "dp_link.h"
0022 
0023 #define DP_KHZ_TO_HZ 1000
0024 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
0025 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
0026 
0027 #define DP_CTRL_INTR_READY_FOR_VIDEO     BIT(0)
0028 #define DP_CTRL_INTR_IDLE_PATTERN_SENT  BIT(3)
0029 
0030 #define MR_LINK_TRAINING1  0x8
0031 #define MR_LINK_SYMBOL_ERM 0x80
0032 #define MR_LINK_PRBS7 0x100
0033 #define MR_LINK_CUSTOM80 0x200
0034 #define MR_LINK_TRAINING4  0x40
0035 
0036 enum {
0037     DP_TRAINING_NONE,
0038     DP_TRAINING_1,
0039     DP_TRAINING_2,
0040 };
0041 
0042 struct dp_tu_calc_input {
0043     u64 lclk;        /* 162, 270, 540 and 810 */
0044     u64 pclk_khz;    /* in KHz */
0045     u64 hactive;     /* active h-width */
0046     u64 hporch;      /* bp + fp + pulse */
0047     int nlanes;      /* no.of.lanes */
0048     int bpp;         /* bits */
0049     int pixel_enc;   /* 444, 420, 422 */
0050     int dsc_en;     /* dsc on/off */
0051     int async_en;   /* async mode */
0052     int fec_en;     /* fec */
0053     int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
0054     int num_of_dsc_slices; /* number of slices per line */
0055 };
0056 
0057 struct dp_vc_tu_mapping_table {
0058     u32 vic;
0059     u8 lanes;
0060     u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
0061     u8 bpp;
0062     u8 valid_boundary_link;
0063     u16 delay_start_link;
0064     bool boundary_moderation_en;
0065     u8 valid_lower_boundary_link;
0066     u8 upper_boundary_count;
0067     u8 lower_boundary_count;
0068     u8 tu_size_minus1;
0069 };
0070 
0071 struct dp_ctrl_private {
0072     struct dp_ctrl dp_ctrl;
0073     struct drm_device *drm_dev;
0074     struct device *dev;
0075     struct drm_dp_aux *aux;
0076     struct dp_panel *panel;
0077     struct dp_link *link;
0078     struct dp_power *power;
0079     struct dp_parser *parser;
0080     struct dp_catalog *catalog;
0081 
0082     struct completion idle_comp;
0083     struct completion video_comp;
0084 };
0085 
0086 static int dp_aux_link_configure(struct drm_dp_aux *aux,
0087                     struct dp_link_info *link)
0088 {
0089     u8 values[2];
0090     int err;
0091 
0092     values[0] = drm_dp_link_rate_to_bw_code(link->rate);
0093     values[1] = link->num_lanes;
0094 
0095     if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
0096         values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
0097 
0098     err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
0099     if (err < 0)
0100         return err;
0101 
0102     return 0;
0103 }
0104 
0105 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
0106 {
0107     struct dp_ctrl_private *ctrl;
0108 
0109     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
0110 
0111     reinit_completion(&ctrl->idle_comp);
0112     dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
0113 
0114     if (!wait_for_completion_timeout(&ctrl->idle_comp,
0115             IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
0116         pr_warn("PUSH_IDLE pattern timedout\n");
0117 
0118     drm_dbg_dp(ctrl->drm_dev, "mainlink off\n");
0119 }
0120 
0121 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
0122 {
0123     u32 config = 0, tbd;
0124     const u8 *dpcd = ctrl->panel->dpcd;
0125 
0126     /* Default-> LSCLK DIV: 1/4 LCLK  */
0127     config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
0128 
0129     /* Scrambler reset enable */
0130     if (drm_dp_alternate_scrambler_reset_cap(dpcd))
0131         config |= DP_CONFIGURATION_CTRL_ASSR;
0132 
0133     tbd = dp_link_get_test_bits_depth(ctrl->link,
0134             ctrl->panel->dp_mode.bpp);
0135 
0136     if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
0137         pr_debug("BIT_DEPTH not set. Configure default\n");
0138         tbd = DP_TEST_BIT_DEPTH_8;
0139     }
0140 
0141     config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
0142 
0143     /* Num of Lanes */
0144     config |= ((ctrl->link->link_params.num_lanes - 1)
0145             << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
0146 
0147     if (drm_dp_enhanced_frame_cap(dpcd))
0148         config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
0149 
0150     config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */
0151 
0152     /* sync clock & static Mvid */
0153     config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
0154     config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
0155 
0156     dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
0157 }
0158 
0159 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
0160 {
0161     u32 cc, tb;
0162 
0163     dp_catalog_ctrl_lane_mapping(ctrl->catalog);
0164     dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
0165 
0166     dp_ctrl_config_ctrl(ctrl);
0167 
0168     tb = dp_link_get_test_bits_depth(ctrl->link,
0169         ctrl->panel->dp_mode.bpp);
0170     cc = dp_link_get_colorimetry_config(ctrl->link);
0171     dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
0172     dp_panel_timing_cfg(ctrl->panel);
0173 }
0174 
0175 /*
0176  * The structure and few functions present below are IP/Hardware
0177  * specific implementation. Most of the implementation will not
0178  * have coding comments
0179  */
0180 struct tu_algo_data {
0181     s64 lclk_fp;
0182     s64 pclk_fp;
0183     s64 lwidth;
0184     s64 lwidth_fp;
0185     s64 hbp_relative_to_pclk;
0186     s64 hbp_relative_to_pclk_fp;
0187     int nlanes;
0188     int bpp;
0189     int pixelEnc;
0190     int dsc_en;
0191     int async_en;
0192     int bpc;
0193 
0194     uint delay_start_link_extra_pixclk;
0195     int extra_buffer_margin;
0196     s64 ratio_fp;
0197     s64 original_ratio_fp;
0198 
0199     s64 err_fp;
0200     s64 n_err_fp;
0201     s64 n_n_err_fp;
0202     int tu_size;
0203     int tu_size_desired;
0204     int tu_size_minus1;
0205 
0206     int valid_boundary_link;
0207     s64 resulting_valid_fp;
0208     s64 total_valid_fp;
0209     s64 effective_valid_fp;
0210     s64 effective_valid_recorded_fp;
0211     int n_tus;
0212     int n_tus_per_lane;
0213     int paired_tus;
0214     int remainder_tus;
0215     int remainder_tus_upper;
0216     int remainder_tus_lower;
0217     int extra_bytes;
0218     int filler_size;
0219     int delay_start_link;
0220 
0221     int extra_pclk_cycles;
0222     int extra_pclk_cycles_in_link_clk;
0223     s64 ratio_by_tu_fp;
0224     s64 average_valid2_fp;
0225     int new_valid_boundary_link;
0226     int remainder_symbols_exist;
0227     int n_symbols;
0228     s64 n_remainder_symbols_per_lane_fp;
0229     s64 last_partial_tu_fp;
0230     s64 TU_ratio_err_fp;
0231 
0232     int n_tus_incl_last_incomplete_tu;
0233     int extra_pclk_cycles_tmp;
0234     int extra_pclk_cycles_in_link_clk_tmp;
0235     int extra_required_bytes_new_tmp;
0236     int filler_size_tmp;
0237     int lower_filler_size_tmp;
0238     int delay_start_link_tmp;
0239 
0240     bool boundary_moderation_en;
0241     int boundary_mod_lower_err;
0242     int upper_boundary_count;
0243     int lower_boundary_count;
0244     int i_upper_boundary_count;
0245     int i_lower_boundary_count;
0246     int valid_lower_boundary_link;
0247     int even_distribution_BF;
0248     int even_distribution_legacy;
0249     int even_distribution;
0250     int min_hblank_violated;
0251     s64 delay_start_time_fp;
0252     s64 hbp_time_fp;
0253     s64 hactive_time_fp;
0254     s64 diff_abs_fp;
0255 
0256     s64 ratio;
0257 };
0258 
0259 static int _tu_param_compare(s64 a, s64 b)
0260 {
0261     u32 a_sign;
0262     u32 b_sign;
0263     s64 a_temp, b_temp, minus_1;
0264 
0265     if (a == b)
0266         return 0;
0267 
0268     minus_1 = drm_fixp_from_fraction(-1, 1);
0269 
0270     a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
0271 
0272     b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
0273 
0274     if (a_sign > b_sign)
0275         return 2;
0276     else if (b_sign > a_sign)
0277         return 1;
0278 
0279     if (!a_sign && !b_sign) { /* positive */
0280         if (a > b)
0281             return 1;
0282         else
0283             return 2;
0284     } else { /* negative */
0285         a_temp = drm_fixp_mul(a, minus_1);
0286         b_temp = drm_fixp_mul(b, minus_1);
0287 
0288         if (a_temp > b_temp)
0289             return 2;
0290         else
0291             return 1;
0292     }
0293 }
0294 
0295 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
0296                     struct tu_algo_data *tu)
0297 {
0298     int nlanes = in->nlanes;
0299     int dsc_num_slices = in->num_of_dsc_slices;
0300     int dsc_num_bytes  = 0;
0301     int numerator;
0302     s64 pclk_dsc_fp;
0303     s64 dwidth_dsc_fp;
0304     s64 hbp_dsc_fp;
0305 
0306     int tot_num_eoc_symbols = 0;
0307     int tot_num_hor_bytes   = 0;
0308     int tot_num_dummy_bytes = 0;
0309     int dwidth_dsc_bytes    = 0;
0310     int  eoc_bytes           = 0;
0311 
0312     s64 temp1_fp, temp2_fp, temp3_fp;
0313 
0314     tu->lclk_fp              = drm_fixp_from_fraction(in->lclk, 1);
0315     tu->pclk_fp              = drm_fixp_from_fraction(in->pclk_khz, 1000);
0316     tu->lwidth               = in->hactive;
0317     tu->hbp_relative_to_pclk = in->hporch;
0318     tu->nlanes               = in->nlanes;
0319     tu->bpp                  = in->bpp;
0320     tu->pixelEnc             = in->pixel_enc;
0321     tu->dsc_en               = in->dsc_en;
0322     tu->async_en             = in->async_en;
0323     tu->lwidth_fp            = drm_fixp_from_fraction(in->hactive, 1);
0324     tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
0325 
0326     if (tu->pixelEnc == 420) {
0327         temp1_fp = drm_fixp_from_fraction(2, 1);
0328         tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
0329         tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
0330         tu->hbp_relative_to_pclk_fp =
0331                 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
0332     }
0333 
0334     if (tu->pixelEnc == 422) {
0335         switch (tu->bpp) {
0336         case 24:
0337             tu->bpp = 16;
0338             tu->bpc = 8;
0339             break;
0340         case 30:
0341             tu->bpp = 20;
0342             tu->bpc = 10;
0343             break;
0344         default:
0345             tu->bpp = 16;
0346             tu->bpc = 8;
0347             break;
0348         }
0349     } else {
0350         tu->bpc = tu->bpp/3;
0351     }
0352 
0353     if (!in->dsc_en)
0354         goto fec_check;
0355 
0356     temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
0357     temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
0358     temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
0359     temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
0360 
0361     temp1_fp = drm_fixp_from_fraction(8, 1);
0362     temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
0363 
0364     numerator = drm_fixp2int(temp3_fp);
0365 
0366     dsc_num_bytes  = numerator / dsc_num_slices;
0367     eoc_bytes           = dsc_num_bytes % nlanes;
0368     tot_num_eoc_symbols = nlanes * dsc_num_slices;
0369     tot_num_hor_bytes   = dsc_num_bytes * dsc_num_slices;
0370     tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
0371 
0372     if (dsc_num_bytes == 0)
0373         pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
0374 
0375     dwidth_dsc_bytes = (tot_num_hor_bytes +
0376                 tot_num_eoc_symbols +
0377                 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
0378 
0379     dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
0380 
0381     temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
0382     temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
0383     pclk_dsc_fp = temp1_fp;
0384 
0385     temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
0386     temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
0387     hbp_dsc_fp = temp2_fp;
0388 
0389     /* output */
0390     tu->pclk_fp = pclk_dsc_fp;
0391     tu->lwidth_fp = dwidth_dsc_fp;
0392     tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
0393 
0394 fec_check:
0395     if (in->fec_en) {
0396         temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
0397         tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
0398     }
0399 }
0400 
0401 static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
0402 {
0403     s64 temp1_fp, temp2_fp, temp, temp1, temp2;
0404     int compare_result_1, compare_result_2, compare_result_3;
0405 
0406     temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
0407     temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
0408 
0409     tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
0410 
0411     temp = (tu->i_upper_boundary_count *
0412                 tu->new_valid_boundary_link +
0413                 tu->i_lower_boundary_count *
0414                 (tu->new_valid_boundary_link-1));
0415     tu->average_valid2_fp = drm_fixp_from_fraction(temp,
0416                     (tu->i_upper_boundary_count +
0417                     tu->i_lower_boundary_count));
0418 
0419     temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
0420     temp2_fp = tu->lwidth_fp;
0421     temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
0422     temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
0423     tu->n_tus = drm_fixp2int(temp2_fp);
0424     if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
0425         tu->n_tus += 1;
0426 
0427     temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
0428     temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
0429     temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
0430     temp2_fp = temp1_fp - temp2_fp;
0431     temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
0432     temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
0433     tu->n_remainder_symbols_per_lane_fp = temp2_fp;
0434 
0435     temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
0436     tu->last_partial_tu_fp =
0437             drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
0438                     temp1_fp);
0439 
0440     if (tu->n_remainder_symbols_per_lane_fp != 0)
0441         tu->remainder_symbols_exist = 1;
0442     else
0443         tu->remainder_symbols_exist = 0;
0444 
0445     temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
0446     tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
0447 
0448     tu->paired_tus = (int)((tu->n_tus_per_lane) /
0449                     (tu->i_upper_boundary_count +
0450                      tu->i_lower_boundary_count));
0451 
0452     tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
0453                         (tu->i_upper_boundary_count +
0454                         tu->i_lower_boundary_count);
0455 
0456     if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
0457         tu->remainder_tus_upper = tu->i_upper_boundary_count;
0458         tu->remainder_tus_lower = tu->remainder_tus -
0459                         tu->i_upper_boundary_count;
0460     } else {
0461         tu->remainder_tus_upper = tu->remainder_tus;
0462         tu->remainder_tus_lower = 0;
0463     }
0464 
0465     temp = tu->paired_tus * (tu->i_upper_boundary_count *
0466                 tu->new_valid_boundary_link +
0467                 tu->i_lower_boundary_count *
0468                 (tu->new_valid_boundary_link - 1)) +
0469                 (tu->remainder_tus_upper *
0470                  tu->new_valid_boundary_link) +
0471                 (tu->remainder_tus_lower *
0472                 (tu->new_valid_boundary_link - 1));
0473     tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
0474 
0475     if (tu->remainder_symbols_exist) {
0476         temp1_fp = tu->total_valid_fp +
0477                 tu->n_remainder_symbols_per_lane_fp;
0478         temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
0479         temp2_fp = temp2_fp + tu->last_partial_tu_fp;
0480         temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
0481     } else {
0482         temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
0483         temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
0484     }
0485     tu->effective_valid_fp = temp1_fp;
0486 
0487     temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
0488     temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
0489     tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
0490 
0491     temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
0492     temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
0493     tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
0494 
0495     tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
0496 
0497     temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
0498     temp2_fp = tu->lwidth_fp;
0499     temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
0500     temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
0501 
0502     if (temp2_fp)
0503         tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
0504     else
0505         tu->n_tus_incl_last_incomplete_tu = 0;
0506 
0507     temp1 = 0;
0508     temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
0509     temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
0510     temp1_fp = tu->average_valid2_fp - temp2_fp;
0511     temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
0512     temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
0513 
0514     if (temp1_fp)
0515         temp1 = drm_fixp2int_ceil(temp1_fp);
0516 
0517     temp = tu->i_upper_boundary_count * tu->nlanes;
0518     temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
0519     temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
0520     temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
0521     temp2_fp = temp1_fp - temp2_fp;
0522     temp1_fp = drm_fixp_from_fraction(temp, 1);
0523     temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
0524 
0525     if (temp2_fp)
0526         temp2 = drm_fixp2int_ceil(temp2_fp);
0527     else
0528         temp2 = 0;
0529     tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
0530 
0531     temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
0532     temp2_fp = drm_fixp_from_fraction(
0533     tu->extra_required_bytes_new_tmp, 1);
0534     temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
0535 
0536     if (temp1_fp)
0537         tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
0538     else
0539         tu->extra_pclk_cycles_tmp = 0;
0540 
0541     temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
0542     temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
0543     temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
0544 
0545     if (temp1_fp)
0546         tu->extra_pclk_cycles_in_link_clk_tmp =
0547                         drm_fixp2int_ceil(temp1_fp);
0548     else
0549         tu->extra_pclk_cycles_in_link_clk_tmp = 0;
0550 
0551     tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
0552 
0553     tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
0554 
0555     tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
0556                     tu->lower_filler_size_tmp +
0557                     tu->extra_buffer_margin;
0558 
0559     temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
0560     tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
0561 
0562     compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
0563     if (compare_result_1 == 2)
0564         compare_result_1 = 1;
0565     else
0566         compare_result_1 = 0;
0567 
0568     compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
0569     if (compare_result_2 == 2)
0570         compare_result_2 = 1;
0571     else
0572         compare_result_2 = 0;
0573 
0574     compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
0575                     tu->delay_start_time_fp);
0576     if (compare_result_3 == 2)
0577         compare_result_3 = 0;
0578     else
0579         compare_result_3 = 1;
0580 
0581     if (((tu->even_distribution == 1) ||
0582             ((tu->even_distribution_BF == 0) &&
0583             (tu->even_distribution_legacy == 0))) &&
0584             tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
0585             compare_result_2 &&
0586             (compare_result_1 || (tu->min_hblank_violated == 1)) &&
0587             (tu->new_valid_boundary_link - 1) > 0 &&
0588             compare_result_3 &&
0589             (tu->delay_start_link_tmp <= 1023)) {
0590         tu->upper_boundary_count = tu->i_upper_boundary_count;
0591         tu->lower_boundary_count = tu->i_lower_boundary_count;
0592         tu->err_fp = tu->n_n_err_fp;
0593         tu->boundary_moderation_en = true;
0594         tu->tu_size_desired = tu->tu_size;
0595         tu->valid_boundary_link = tu->new_valid_boundary_link;
0596         tu->effective_valid_recorded_fp = tu->effective_valid_fp;
0597         tu->even_distribution_BF = 1;
0598         tu->delay_start_link = tu->delay_start_link_tmp;
0599     } else if (tu->boundary_mod_lower_err == 0) {
0600         compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
0601                             tu->diff_abs_fp);
0602         if (compare_result_1 == 2)
0603             tu->boundary_mod_lower_err = 1;
0604     }
0605 }
0606 
0607 static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl,
0608                 struct dp_tu_calc_input *in,
0609                 struct dp_vc_tu_mapping_table *tu_table)
0610 {
0611     struct tu_algo_data *tu;
0612     int compare_result_1, compare_result_2;
0613     u64 temp = 0;
0614     s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
0615 
0616     s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
0617     s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
0618     s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
0619     s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
0620 
0621     u8 DP_BRUTE_FORCE = 1;
0622     s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
0623     uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
0624     uint HBLANK_MARGIN = 4;
0625 
0626     tu = kzalloc(sizeof(*tu), GFP_KERNEL);
0627     if (!tu)
0628         return;
0629 
0630     dp_panel_update_tu_timings(in, tu);
0631 
0632     tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
0633 
0634     temp1_fp = drm_fixp_from_fraction(4, 1);
0635     temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
0636     temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
0637     tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
0638 
0639     temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
0640     temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
0641     temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
0642     temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
0643     tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
0644 
0645     tu->original_ratio_fp = tu->ratio_fp;
0646     tu->boundary_moderation_en = false;
0647     tu->upper_boundary_count = 0;
0648     tu->lower_boundary_count = 0;
0649     tu->i_upper_boundary_count = 0;
0650     tu->i_lower_boundary_count = 0;
0651     tu->valid_lower_boundary_link = 0;
0652     tu->even_distribution_BF = 0;
0653     tu->even_distribution_legacy = 0;
0654     tu->even_distribution = 0;
0655     tu->delay_start_time_fp = 0;
0656 
0657     tu->err_fp = drm_fixp_from_fraction(1000, 1);
0658     tu->n_err_fp = 0;
0659     tu->n_n_err_fp = 0;
0660 
0661     tu->ratio = drm_fixp2int(tu->ratio_fp);
0662     temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
0663     div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
0664     if (temp2_fp != 0 &&
0665             !tu->ratio && tu->dsc_en == 0) {
0666         tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
0667         tu->ratio = drm_fixp2int(tu->ratio_fp);
0668         if (tu->ratio)
0669             tu->ratio_fp = drm_fixp_from_fraction(1, 1);
0670     }
0671 
0672     if (tu->ratio > 1)
0673         tu->ratio = 1;
0674 
0675     if (tu->ratio == 1)
0676         goto tu_size_calc;
0677 
0678     compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
0679     if (!compare_result_1 || compare_result_1 == 1)
0680         compare_result_1 = 1;
0681     else
0682         compare_result_1 = 0;
0683 
0684     compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
0685     if (!compare_result_2 || compare_result_2 == 2)
0686         compare_result_2 = 1;
0687     else
0688         compare_result_2 = 0;
0689 
0690     if (tu->dsc_en && compare_result_1 && compare_result_2) {
0691         HBLANK_MARGIN += 4;
0692         drm_dbg_dp(ctrl->drm_dev,
0693             "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN);
0694     }
0695 
0696 tu_size_calc:
0697     for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
0698         temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
0699         temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
0700         temp = drm_fixp2int_ceil(temp2_fp);
0701         temp1_fp = drm_fixp_from_fraction(temp, 1);
0702         tu->n_err_fp = temp1_fp - temp2_fp;
0703 
0704         if (tu->n_err_fp < tu->err_fp) {
0705             tu->err_fp = tu->n_err_fp;
0706             tu->tu_size_desired = tu->tu_size;
0707         }
0708     }
0709 
0710     tu->tu_size_minus1 = tu->tu_size_desired - 1;
0711 
0712     temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
0713     temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
0714     tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
0715 
0716     temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
0717     temp2_fp = tu->lwidth_fp;
0718     temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
0719 
0720     temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
0721     temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
0722     tu->n_tus = drm_fixp2int(temp2_fp);
0723     if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
0724         tu->n_tus += 1;
0725 
0726     tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
0727 
0728     drm_dbg_dp(ctrl->drm_dev,
0729             "n_sym = %d, num_of_tus = %d\n",
0730             tu->valid_boundary_link, tu->n_tus);
0731 
0732     temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
0733     temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
0734     temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
0735     temp2_fp = temp1_fp - temp2_fp;
0736     temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
0737     temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
0738 
0739     temp = drm_fixp2int(temp2_fp);
0740     if (temp && temp2_fp)
0741         tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
0742     else
0743         tu->extra_bytes = 0;
0744 
0745     temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
0746     temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
0747     temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
0748 
0749     if (temp && temp1_fp)
0750         tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
0751     else
0752         tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
0753 
0754     temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
0755     temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
0756     temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
0757 
0758     if (temp1_fp)
0759         tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
0760     else
0761         tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
0762 
0763     tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
0764 
0765     temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
0766     tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
0767 
0768     tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
0769                 tu->filler_size + tu->extra_buffer_margin;
0770 
0771     tu->resulting_valid_fp =
0772             drm_fixp_from_fraction(tu->valid_boundary_link, 1);
0773 
0774     temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
0775     temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
0776     tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
0777 
0778     temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
0779     temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
0780     tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
0781 
0782     temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
0783     tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
0784 
0785     compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
0786                     tu->delay_start_time_fp);
0787     if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
0788         tu->min_hblank_violated = 1;
0789 
0790     tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
0791 
0792     compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
0793                         tu->delay_start_time_fp);
0794     if (compare_result_2 == 2)
0795         tu->min_hblank_violated = 1;
0796 
0797     tu->delay_start_time_fp = 0;
0798 
0799     /* brute force */
0800 
0801     tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
0802     tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
0803 
0804     temp = drm_fixp2int(tu->diff_abs_fp);
0805     if (!temp && tu->diff_abs_fp <= 0xffff)
0806         tu->diff_abs_fp = 0;
0807 
0808     /* if(diff_abs < 0) diff_abs *= -1 */
0809     if (tu->diff_abs_fp < 0)
0810         tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
0811 
0812     tu->boundary_mod_lower_err = 0;
0813     if ((tu->diff_abs_fp != 0 &&
0814             ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
0815              (tu->even_distribution_legacy == 0) ||
0816              (DP_BRUTE_FORCE == 1))) ||
0817             (tu->min_hblank_violated == 1)) {
0818         do {
0819             tu->err_fp = drm_fixp_from_fraction(1000, 1);
0820 
0821             temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
0822             temp2_fp = drm_fixp_from_fraction(
0823                     tu->delay_start_link_extra_pixclk, 1);
0824             temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
0825 
0826             if (temp1_fp)
0827                 tu->extra_buffer_margin =
0828                     drm_fixp2int_ceil(temp1_fp);
0829             else
0830                 tu->extra_buffer_margin = 0;
0831 
0832             temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
0833             temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
0834 
0835             if (temp1_fp)
0836                 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
0837             else
0838                 tu->n_symbols = 0;
0839 
0840             for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
0841                 for (tu->i_upper_boundary_count = 1;
0842                     tu->i_upper_boundary_count <= 15;
0843                     tu->i_upper_boundary_count++) {
0844                     for (tu->i_lower_boundary_count = 1;
0845                         tu->i_lower_boundary_count <= 15;
0846                         tu->i_lower_boundary_count++) {
0847                         _tu_valid_boundary_calc(tu);
0848                     }
0849                 }
0850             }
0851             tu->delay_start_link_extra_pixclk--;
0852         } while (tu->boundary_moderation_en != true &&
0853             tu->boundary_mod_lower_err == 1 &&
0854             tu->delay_start_link_extra_pixclk != 0);
0855 
0856         if (tu->boundary_moderation_en == true) {
0857             temp1_fp = drm_fixp_from_fraction(
0858                     (tu->upper_boundary_count *
0859                     tu->valid_boundary_link +
0860                     tu->lower_boundary_count *
0861                     (tu->valid_boundary_link - 1)), 1);
0862             temp2_fp = drm_fixp_from_fraction(
0863                     (tu->upper_boundary_count +
0864                     tu->lower_boundary_count), 1);
0865             tu->resulting_valid_fp =
0866                     drm_fixp_div(temp1_fp, temp2_fp);
0867 
0868             temp1_fp = drm_fixp_from_fraction(
0869                     tu->tu_size_desired, 1);
0870             tu->ratio_by_tu_fp =
0871                 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
0872 
0873             tu->valid_lower_boundary_link =
0874                 tu->valid_boundary_link - 1;
0875 
0876             temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
0877             temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
0878             temp2_fp = drm_fixp_div(temp1_fp,
0879                         tu->resulting_valid_fp);
0880             tu->n_tus = drm_fixp2int(temp2_fp);
0881 
0882             tu->tu_size_minus1 = tu->tu_size_desired - 1;
0883             tu->even_distribution_BF = 1;
0884 
0885             temp1_fp =
0886                 drm_fixp_from_fraction(tu->tu_size_desired, 1);
0887             temp2_fp =
0888                 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
0889             tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
0890         }
0891     }
0892 
0893     temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
0894 
0895     if (temp2_fp)
0896         temp = drm_fixp2int_ceil(temp2_fp);
0897     else
0898         temp = 0;
0899 
0900     temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
0901     temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
0902     temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
0903     temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
0904     temp1_fp = drm_fixp_from_fraction(temp, 1);
0905     temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
0906     temp = drm_fixp2int(temp2_fp);
0907 
0908     if (tu->async_en)
0909         tu->delay_start_link += (int)temp;
0910 
0911     temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
0912     tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
0913 
0914     /* OUTPUTS */
0915     tu_table->valid_boundary_link       = tu->valid_boundary_link;
0916     tu_table->delay_start_link          = tu->delay_start_link;
0917     tu_table->boundary_moderation_en    = tu->boundary_moderation_en;
0918     tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
0919     tu_table->upper_boundary_count      = tu->upper_boundary_count;
0920     tu_table->lower_boundary_count      = tu->lower_boundary_count;
0921     tu_table->tu_size_minus1            = tu->tu_size_minus1;
0922 
0923     drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n",
0924                 tu_table->valid_boundary_link);
0925     drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n",
0926                 tu_table->delay_start_link);
0927     drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n",
0928             tu_table->boundary_moderation_en);
0929     drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n",
0930             tu_table->valid_lower_boundary_link);
0931     drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n",
0932             tu_table->upper_boundary_count);
0933     drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n",
0934             tu_table->lower_boundary_count);
0935     drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n",
0936             tu_table->tu_size_minus1);
0937 
0938     kfree(tu);
0939 }
0940 
0941 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
0942         struct dp_vc_tu_mapping_table *tu_table)
0943 {
0944     struct dp_tu_calc_input in;
0945     struct drm_display_mode *drm_mode;
0946 
0947     drm_mode = &ctrl->panel->dp_mode.drm_mode;
0948 
0949     in.lclk = ctrl->link->link_params.rate / 1000;
0950     in.pclk_khz = drm_mode->clock;
0951     in.hactive = drm_mode->hdisplay;
0952     in.hporch = drm_mode->htotal - drm_mode->hdisplay;
0953     in.nlanes = ctrl->link->link_params.num_lanes;
0954     in.bpp = ctrl->panel->dp_mode.bpp;
0955     in.pixel_enc = 444;
0956     in.dsc_en = 0;
0957     in.async_en = 0;
0958     in.fec_en = 0;
0959     in.num_of_dsc_slices = 0;
0960     in.compress_ratio = 100;
0961 
0962     _dp_ctrl_calc_tu(ctrl, &in, tu_table);
0963 }
0964 
0965 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
0966 {
0967     u32 dp_tu = 0x0;
0968     u32 valid_boundary = 0x0;
0969     u32 valid_boundary2 = 0x0;
0970     struct dp_vc_tu_mapping_table tu_calc_table;
0971 
0972     dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
0973 
0974     dp_tu |= tu_calc_table.tu_size_minus1;
0975     valid_boundary |= tu_calc_table.valid_boundary_link;
0976     valid_boundary |= (tu_calc_table.delay_start_link << 16);
0977 
0978     valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
0979     valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
0980     valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
0981 
0982     if (tu_calc_table.boundary_moderation_en)
0983         valid_boundary2 |= BIT(0);
0984 
0985     pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
0986             dp_tu, valid_boundary, valid_boundary2);
0987 
0988     dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
0989                 dp_tu, valid_boundary, valid_boundary2);
0990 }
0991 
0992 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
0993 {
0994     int ret = 0;
0995 
0996     if (!wait_for_completion_timeout(&ctrl->video_comp,
0997                 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
0998         DRM_ERROR("wait4video timedout\n");
0999         ret = -ETIMEDOUT;
1000     }
1001     return ret;
1002 }
1003 
1004 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
1005 {
1006     struct dp_link *link = ctrl->link;
1007     int ret = 0, lane, lane_cnt;
1008     u8 buf[4];
1009     u32 max_level_reached = 0;
1010     u32 voltage_swing_level = link->phy_params.v_level;
1011     u32 pre_emphasis_level = link->phy_params.p_level;
1012 
1013     drm_dbg_dp(ctrl->drm_dev,
1014         "voltage level: %d emphasis level: %d\n",
1015             voltage_swing_level, pre_emphasis_level);
1016     ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1017         voltage_swing_level, pre_emphasis_level);
1018 
1019     if (ret)
1020         return ret;
1021 
1022     if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1023         drm_dbg_dp(ctrl->drm_dev,
1024                 "max. voltage swing level reached %d\n",
1025                 voltage_swing_level);
1026         max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1027     }
1028 
1029     if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1030         drm_dbg_dp(ctrl->drm_dev,
1031                 "max. pre-emphasis level reached %d\n",
1032                 pre_emphasis_level);
1033         max_level_reached  |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1034     }
1035 
1036     pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1037 
1038     lane_cnt = ctrl->link->link_params.num_lanes;
1039     for (lane = 0; lane < lane_cnt; lane++)
1040         buf[lane] = voltage_swing_level | pre_emphasis_level
1041                 | max_level_reached;
1042 
1043     drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n",
1044             voltage_swing_level | pre_emphasis_level);
1045     ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1046                     buf, lane_cnt);
1047     if (ret == lane_cnt)
1048         ret = 0;
1049 
1050     return ret;
1051 }
1052 
1053 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
1054         u8 pattern)
1055 {
1056     u8 buf;
1057     int ret = 0;
1058 
1059     drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern);
1060 
1061     buf = pattern;
1062 
1063     if (pattern && pattern != DP_TRAINING_PATTERN_4)
1064         buf |= DP_LINK_SCRAMBLING_DISABLE;
1065 
1066     ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1067     return ret == 1;
1068 }
1069 
1070 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
1071                     u8 *link_status)
1072 {
1073     int ret = 0, len;
1074 
1075     len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1076     if (len != DP_LINK_STATUS_SIZE) {
1077         DRM_ERROR("DP link status read failed, err: %d\n", len);
1078         ret = -EINVAL;
1079     }
1080 
1081     return ret;
1082 }
1083 
1084 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1085             int *training_step)
1086 {
1087     int tries, old_v_level, ret = 0;
1088     u8 link_status[DP_LINK_STATUS_SIZE];
1089     int const maximum_retries = 4;
1090 
1091     dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1092 
1093     *training_step = DP_TRAINING_1;
1094 
1095     ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1);
1096     if (ret)
1097         return ret;
1098     dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1099         DP_LINK_SCRAMBLING_DISABLE);
1100 
1101     ret = dp_ctrl_update_vx_px(ctrl);
1102     if (ret)
1103         return ret;
1104 
1105     tries = 0;
1106     old_v_level = ctrl->link->phy_params.v_level;
1107     for (tries = 0; tries < maximum_retries; tries++) {
1108         drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1109 
1110         ret = dp_ctrl_read_link_status(ctrl, link_status);
1111         if (ret)
1112             return ret;
1113 
1114         if (drm_dp_clock_recovery_ok(link_status,
1115             ctrl->link->link_params.num_lanes)) {
1116             return 0;
1117         }
1118 
1119         if (ctrl->link->phy_params.v_level >=
1120             DP_TRAIN_VOLTAGE_SWING_MAX) {
1121             DRM_ERROR_RATELIMITED("max v_level reached\n");
1122             return -EAGAIN;
1123         }
1124 
1125         if (old_v_level != ctrl->link->phy_params.v_level) {
1126             tries = 0;
1127             old_v_level = ctrl->link->phy_params.v_level;
1128         }
1129 
1130         dp_link_adjust_levels(ctrl->link, link_status);
1131         ret = dp_ctrl_update_vx_px(ctrl);
1132         if (ret)
1133             return ret;
1134     }
1135 
1136     DRM_ERROR("max tries reached\n");
1137     return -ETIMEDOUT;
1138 }
1139 
1140 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1141 {
1142     int ret = 0;
1143 
1144     switch (ctrl->link->link_params.rate) {
1145     case 810000:
1146         ctrl->link->link_params.rate = 540000;
1147         break;
1148     case 540000:
1149         ctrl->link->link_params.rate = 270000;
1150         break;
1151     case 270000:
1152         ctrl->link->link_params.rate = 162000;
1153         break;
1154     case 162000:
1155     default:
1156         ret = -EINVAL;
1157         break;
1158     }
1159 
1160     if (!ret) {
1161         drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
1162                 ctrl->link->link_params.rate);
1163     }
1164 
1165     return ret;
1166 }
1167 
1168 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
1169 {
1170 
1171     if (ctrl->link->link_params.num_lanes == 1)
1172         return -1;
1173 
1174     ctrl->link->link_params.num_lanes /= 2;
1175     ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1176 
1177     ctrl->link->phy_params.p_level = 0;
1178     ctrl->link->phy_params.v_level = 0;
1179 
1180     return 0;
1181 }
1182 
1183 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
1184 {
1185     dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1186     drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1187 }
1188 
1189 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1190             int *training_step)
1191 {
1192     int tries = 0, ret = 0;
1193     u8 pattern;
1194     u32 state_ctrl_bit;
1195     int const maximum_retries = 5;
1196     u8 link_status[DP_LINK_STATUS_SIZE];
1197 
1198     dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1199 
1200     *training_step = DP_TRAINING_2;
1201 
1202     if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
1203         pattern = DP_TRAINING_PATTERN_4;
1204         state_ctrl_bit = 4;
1205     } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1206         pattern = DP_TRAINING_PATTERN_3;
1207         state_ctrl_bit = 3;
1208     } else {
1209         pattern = DP_TRAINING_PATTERN_2;
1210         state_ctrl_bit = 2;
1211     }
1212 
1213     ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit);
1214     if (ret)
1215         return ret;
1216 
1217     dp_ctrl_train_pattern_set(ctrl, pattern);
1218 
1219     for (tries = 0; tries <= maximum_retries; tries++) {
1220         drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1221 
1222         ret = dp_ctrl_read_link_status(ctrl, link_status);
1223         if (ret)
1224             return ret;
1225 
1226         if (drm_dp_channel_eq_ok(link_status,
1227             ctrl->link->link_params.num_lanes)) {
1228             return 0;
1229         }
1230 
1231         dp_link_adjust_levels(ctrl->link, link_status);
1232         ret = dp_ctrl_update_vx_px(ctrl);
1233         if (ret)
1234             return ret;
1235 
1236     }
1237 
1238     return -ETIMEDOUT;
1239 }
1240 
1241 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl);
1242 
1243 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1244             int *training_step)
1245 {
1246     int ret = 0;
1247     const u8 *dpcd = ctrl->panel->dpcd;
1248     u8 encoding = DP_SET_ANSI_8B10B;
1249     u8 ssc;
1250     u8 assr;
1251     struct dp_link_info link_info = {0};
1252 
1253     dp_ctrl_config_ctrl(ctrl);
1254 
1255     link_info.num_lanes = ctrl->link->link_params.num_lanes;
1256     link_info.rate = ctrl->link->link_params.rate;
1257     link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1258 
1259     dp_aux_link_configure(ctrl->aux, &link_info);
1260 
1261     if (drm_dp_max_downspread(dpcd)) {
1262         ssc = DP_SPREAD_AMP_0_5;
1263         drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);
1264     }
1265 
1266     drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
1267                 &encoding, 1);
1268 
1269     if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
1270         assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
1271         drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
1272                 &assr, 1);
1273     }
1274 
1275     ret = dp_ctrl_link_train_1(ctrl, training_step);
1276     if (ret) {
1277         DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1278         goto end;
1279     }
1280 
1281     /* print success info as this is a result of user initiated action */
1282     drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n");
1283 
1284     ret = dp_ctrl_link_train_2(ctrl, training_step);
1285     if (ret) {
1286         DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1287         goto end;
1288     }
1289 
1290     /* print success info as this is a result of user initiated action */
1291     drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n");
1292 
1293 end:
1294     dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1295 
1296     return ret;
1297 }
1298 
1299 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1300             int *training_step)
1301 {
1302     int ret = 0;
1303 
1304     dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1305 
1306     if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1307         return ret;
1308 
1309     /*
1310      * As part of previous calls, DP controller state might have
1311      * transitioned to PUSH_IDLE. In order to start transmitting
1312      * a link training pattern, we have to first do soft reset.
1313      */
1314 
1315     ret = dp_ctrl_link_train(ctrl, training_step);
1316 
1317     return ret;
1318 }
1319 
1320 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1321             enum dp_pm_type module, char *name, unsigned long rate)
1322 {
1323     u32 num = ctrl->parser->mp[module].num_clk;
1324     struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks;
1325 
1326     while (num && strcmp(cfg->id, name)) {
1327         num--;
1328         cfg++;
1329     }
1330 
1331     drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n",
1332                         rate, name);
1333 
1334     if (num)
1335         clk_set_rate(cfg->clk, rate);
1336     else
1337         DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1338                 name, rate);
1339 }
1340 
1341 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1342 {
1343     int ret = 0;
1344     struct dp_io *dp_io = &ctrl->parser->io;
1345     struct phy *phy = dp_io->phy;
1346     struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1347     const u8 *dpcd = ctrl->panel->dpcd;
1348 
1349     opts_dp->lanes = ctrl->link->link_params.num_lanes;
1350     opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1351     opts_dp->ssc = drm_dp_max_downspread(dpcd);
1352 
1353     phy_configure(phy, &dp_io->phy_opts);
1354     phy_power_on(phy);
1355 
1356     dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);
1357     ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
1358     if (ret)
1359         DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1360 
1361     drm_dbg_dp(ctrl->drm_dev, "link rate=%d pixel_clk=%d\n",
1362         ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1363 
1364     return ret;
1365 }
1366 
1367 static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
1368 {
1369     int ret = 0;
1370 
1371     dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
1372                     ctrl->dp_ctrl.pixel_rate * 1000);
1373 
1374     ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1375     if (ret)
1376         DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret);
1377 
1378     drm_dbg_dp(ctrl->drm_dev, "link rate=%d pixel_clk=%d\n",
1379             ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1380 
1381     return ret;
1382 }
1383 
1384 void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
1385 {
1386     struct dp_ctrl_private *ctrl;
1387 
1388     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1389 
1390     dp_catalog_ctrl_reset(ctrl->catalog);
1391 
1392     /*
1393      * all dp controller programmable registers will not
1394      * be reset to default value after DP_SW_RESET
1395      * therefore interrupt mask bits have to be updated
1396      * to enable/disable interrupts
1397      */
1398     dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
1399 }
1400 
1401 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
1402 {
1403     struct dp_ctrl_private *ctrl;
1404     struct dp_io *dp_io;
1405     struct phy *phy;
1406 
1407     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1408     dp_io = &ctrl->parser->io;
1409     phy = dp_io->phy;
1410 
1411     dp_catalog_ctrl_phy_reset(ctrl->catalog);
1412     phy_init(phy);
1413 
1414     drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1415             phy, phy->init_count, phy->power_count);
1416 }
1417 
1418 void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
1419 {
1420     struct dp_ctrl_private *ctrl;
1421     struct dp_io *dp_io;
1422     struct phy *phy;
1423 
1424     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1425     dp_io = &ctrl->parser->io;
1426     phy = dp_io->phy;
1427 
1428     dp_catalog_ctrl_phy_reset(ctrl->catalog);
1429     phy_exit(phy);
1430     drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1431             phy, phy->init_count, phy->power_count);
1432 }
1433 
1434 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
1435 {
1436     const u8 *dpcd = ctrl->panel->dpcd;
1437 
1438     /*
1439      * For better interop experience, used a fixed NVID=0x8000
1440      * whenever connected to a VGA dongle downstream.
1441      */
1442     if (drm_dp_is_branch(dpcd))
1443         return (drm_dp_has_quirk(&ctrl->panel->desc,
1444                      DP_DPCD_QUIRK_CONSTANT_N));
1445 
1446     return false;
1447 }
1448 
1449 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1450 {
1451     int ret = 0;
1452     struct dp_io *dp_io = &ctrl->parser->io;
1453     struct phy *phy = dp_io->phy;
1454     struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1455 
1456     dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1457     opts_dp->lanes = ctrl->link->link_params.num_lanes;
1458     phy_configure(phy, &dp_io->phy_opts);
1459     /*
1460      * Disable and re-enable the mainlink clock since the
1461      * link clock might have been adjusted as part of the
1462      * link maintenance.
1463      */
1464     dev_pm_opp_set_rate(ctrl->dev, 0);
1465     ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1466     if (ret) {
1467         DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
1468         return ret;
1469     }
1470     phy_power_off(phy);
1471     /* hw recommended delay before re-enabling clocks */
1472     msleep(20);
1473 
1474     ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1475     if (ret) {
1476         DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1477         return ret;
1478     }
1479 
1480     return ret;
1481 }
1482 
1483 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
1484 {
1485     struct dp_io *dp_io;
1486     struct phy *phy;
1487     int ret;
1488 
1489     dp_io = &ctrl->parser->io;
1490     phy = dp_io->phy;
1491 
1492     dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1493 
1494     dp_catalog_ctrl_reset(ctrl->catalog);
1495 
1496     dev_pm_opp_set_rate(ctrl->dev, 0);
1497     ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1498     if (ret) {
1499         DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1500     }
1501 
1502     phy_power_off(phy);
1503 
1504     /* aux channel down, reinit phy */
1505     phy_exit(phy);
1506     phy_init(phy);
1507 
1508     drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1509             phy, phy->init_count, phy->power_count);
1510     return 0;
1511 }
1512 
1513 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
1514 {
1515     int ret = 0;
1516     int training_step = DP_TRAINING_NONE;
1517 
1518     dp_ctrl_push_idle(&ctrl->dp_ctrl);
1519 
1520     ctrl->link->phy_params.p_level = 0;
1521     ctrl->link->phy_params.v_level = 0;
1522 
1523     ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1524 
1525     ret = dp_ctrl_setup_main_link(ctrl, &training_step);
1526     if (ret)
1527         goto end;
1528 
1529     dp_ctrl_clear_training_pattern(ctrl);
1530 
1531     dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1532 
1533     ret = dp_ctrl_wait4video_ready(ctrl);
1534 end:
1535     return ret;
1536 }
1537 
1538 static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl);
1539 
1540 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1541 {
1542     int ret = 0;
1543 
1544     if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1545         drm_dbg_dp(ctrl->drm_dev,
1546             "no test pattern selected by sink\n");
1547         return ret;
1548     }
1549 
1550     /*
1551      * The global reset will need DP link related clocks to be
1552      * running. Add the global reset just before disabling the
1553      * link clocks and core clocks.
1554      */
1555     ret = dp_ctrl_off(&ctrl->dp_ctrl);
1556     if (ret) {
1557         DRM_ERROR("failed to disable DP controller\n");
1558         return ret;
1559     }
1560 
1561     ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1562     if (!ret)
1563         ret = dp_ctrl_on_stream_phy_test_report(&ctrl->dp_ctrl);
1564     else
1565         DRM_ERROR("failed to enable DP link controller\n");
1566 
1567     return ret;
1568 }
1569 
1570 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
1571 {
1572     bool success = false;
1573     u32 pattern_sent = 0x0;
1574     u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1575 
1576     drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
1577 
1578     if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1579             ctrl->link->phy_params.v_level,
1580             ctrl->link->phy_params.p_level)) {
1581         DRM_ERROR("Failed to set v/p levels\n");
1582         return false;
1583     }
1584     dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1585     dp_ctrl_update_vx_px(ctrl);
1586     dp_link_send_test_response(ctrl->link);
1587 
1588     pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1589 
1590     switch (pattern_sent) {
1591     case MR_LINK_TRAINING1:
1592         success = (pattern_requested ==
1593                 DP_PHY_TEST_PATTERN_D10_2);
1594         break;
1595     case MR_LINK_SYMBOL_ERM:
1596         success = ((pattern_requested ==
1597             DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1598                 (pattern_requested ==
1599                 DP_PHY_TEST_PATTERN_CP2520));
1600         break;
1601     case MR_LINK_PRBS7:
1602         success = (pattern_requested ==
1603                 DP_PHY_TEST_PATTERN_PRBS7);
1604         break;
1605     case MR_LINK_CUSTOM80:
1606         success = (pattern_requested ==
1607                 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1608         break;
1609     case MR_LINK_TRAINING4:
1610         success = (pattern_requested ==
1611                 DP_PHY_TEST_PATTERN_SEL_MASK);
1612         break;
1613     default:
1614         success = false;
1615     }
1616 
1617     drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n",
1618         success ? "success" : "failed", pattern_requested);
1619     return success;
1620 }
1621 
1622 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
1623 {
1624     struct dp_ctrl_private *ctrl;
1625     u32 sink_request = 0x0;
1626 
1627     if (!dp_ctrl) {
1628         DRM_ERROR("invalid input\n");
1629         return;
1630     }
1631 
1632     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1633     sink_request = ctrl->link->sink_request;
1634 
1635     if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1636         drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n");
1637         if (dp_ctrl_process_phy_test_request(ctrl)) {
1638             DRM_ERROR("process phy_test_req failed\n");
1639             return;
1640         }
1641     }
1642 
1643     if (sink_request & DP_LINK_STATUS_UPDATED) {
1644         if (dp_ctrl_link_maintenance(ctrl)) {
1645             DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1646             return;
1647         }
1648     }
1649 
1650     if (sink_request & DP_TEST_LINK_TRAINING) {
1651         dp_link_send_test_response(ctrl->link);
1652         if (dp_ctrl_link_maintenance(ctrl)) {
1653             DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1654             return;
1655         }
1656     }
1657 }
1658 
1659 static bool dp_ctrl_clock_recovery_any_ok(
1660             const u8 link_status[DP_LINK_STATUS_SIZE],
1661             int lane_count)
1662 {
1663     int reduced_cnt;
1664 
1665     if (lane_count <= 1)
1666         return false;
1667 
1668     /*
1669      * only interested in the lane number after reduced
1670      * lane_count = 4, then only interested in 2 lanes
1671      * lane_count = 2, then only interested in 1 lane
1672      */
1673     reduced_cnt = lane_count >> 1;
1674 
1675     return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
1676 }
1677 
1678 static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
1679 {
1680     u8 link_status[DP_LINK_STATUS_SIZE];
1681     int num_lanes = ctrl->link->link_params.num_lanes;
1682 
1683     dp_ctrl_read_link_status(ctrl, link_status);
1684 
1685     return drm_dp_channel_eq_ok(link_status, num_lanes);
1686 }
1687 
1688 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1689 {
1690     int rc = 0;
1691     struct dp_ctrl_private *ctrl;
1692     u32 rate = 0;
1693     int link_train_max_retries = 5;
1694     u32 const phy_cts_pixel_clk_khz = 148500;
1695     u8 link_status[DP_LINK_STATUS_SIZE];
1696     unsigned int training_step;
1697 
1698     if (!dp_ctrl)
1699         return -EINVAL;
1700 
1701     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1702 
1703     rate = ctrl->panel->link_info.rate;
1704 
1705     dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
1706 
1707     if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1708         drm_dbg_dp(ctrl->drm_dev,
1709                 "using phy test link parameters\n");
1710         if (!ctrl->panel->dp_mode.drm_mode.clock)
1711             ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz;
1712     } else {
1713         ctrl->link->link_params.rate = rate;
1714         ctrl->link->link_params.num_lanes =
1715             ctrl->panel->link_info.num_lanes;
1716         ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1717     }
1718 
1719     drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%d\n",
1720         ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes,
1721         ctrl->dp_ctrl.pixel_rate);
1722 
1723 
1724     rc = dp_ctrl_enable_mainlink_clocks(ctrl);
1725     if (rc)
1726         return rc;
1727 
1728     while (--link_train_max_retries) {
1729         rc = dp_ctrl_reinitialize_mainlink(ctrl);
1730         if (rc) {
1731             DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n",
1732                     rc);
1733             break;
1734         }
1735 
1736         training_step = DP_TRAINING_NONE;
1737         rc = dp_ctrl_setup_main_link(ctrl, &training_step);
1738         if (rc == 0) {
1739             /* training completed successfully */
1740             break;
1741         } else if (training_step == DP_TRAINING_1) {
1742             /* link train_1 failed */
1743             if (!dp_catalog_link_is_connected(ctrl->catalog))
1744                 break;
1745 
1746             dp_ctrl_read_link_status(ctrl, link_status);
1747 
1748             rc = dp_ctrl_link_rate_down_shift(ctrl);
1749             if (rc < 0) { /* already in RBR = 1.6G */
1750                 if (dp_ctrl_clock_recovery_any_ok(link_status,
1751                     ctrl->link->link_params.num_lanes)) {
1752                     /*
1753                      * some lanes are ready,
1754                      * reduce lane number
1755                      */
1756                     rc = dp_ctrl_link_lane_down_shift(ctrl);
1757                     if (rc < 0) { /* lane == 1 already */
1758                         /* end with failure */
1759                         break;
1760                     }
1761                 } else {
1762                     /* end with failure */
1763                     break; /* lane == 1 already */
1764                 }
1765             }
1766         } else if (training_step == DP_TRAINING_2) {
1767             /* link train_2 failed */
1768             if (!dp_catalog_link_is_connected(ctrl->catalog))
1769                 break;
1770 
1771             dp_ctrl_read_link_status(ctrl, link_status);
1772 
1773             if (!drm_dp_clock_recovery_ok(link_status,
1774                     ctrl->link->link_params.num_lanes))
1775                 rc = dp_ctrl_link_rate_down_shift(ctrl);
1776             else
1777                 rc = dp_ctrl_link_lane_down_shift(ctrl);
1778 
1779             if (rc < 0) {
1780                 /* end with failure */
1781                 break; /* lane == 1 already */
1782             }
1783 
1784             /* stop link training before start re training  */
1785             dp_ctrl_clear_training_pattern(ctrl);
1786         }
1787     }
1788 
1789     if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1790         return rc;
1791 
1792     if (rc == 0) {  /* link train successfully */
1793         /*
1794          * do not stop train pattern here
1795          * stop link training at on_stream
1796          * to pass compliance test
1797          */
1798     } else  {
1799         /*
1800          * link training failed
1801          * end txing train pattern here
1802          */
1803         dp_ctrl_clear_training_pattern(ctrl);
1804 
1805         dp_ctrl_deinitialize_mainlink(ctrl);
1806         rc = -ECONNRESET;
1807     }
1808 
1809     return rc;
1810 }
1811 
1812 static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
1813 {
1814     int training_step = DP_TRAINING_NONE;
1815 
1816     return dp_ctrl_setup_main_link(ctrl, &training_step);
1817 }
1818 
1819 static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl)
1820 {
1821     int ret;
1822     struct dp_ctrl_private *ctrl;
1823 
1824     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1825 
1826     ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1827 
1828     ret = dp_ctrl_enable_stream_clocks(ctrl);
1829     if (ret) {
1830         DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1831         return ret;
1832     }
1833 
1834     dp_ctrl_send_phy_test_pattern(ctrl);
1835 
1836     return 0;
1837 }
1838 
1839 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
1840 {
1841     int ret = 0;
1842     bool mainlink_ready = false;
1843     struct dp_ctrl_private *ctrl;
1844     unsigned long pixel_rate_orig;
1845 
1846     if (!dp_ctrl)
1847         return -EINVAL;
1848 
1849     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1850 
1851     ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1852 
1853     pixel_rate_orig = ctrl->dp_ctrl.pixel_rate;
1854     if (dp_ctrl->wide_bus_en)
1855         ctrl->dp_ctrl.pixel_rate >>= 1;
1856 
1857     drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%d\n",
1858         ctrl->link->link_params.rate,
1859         ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1860 
1861     if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
1862         ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1863         if (ret) {
1864             DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1865             goto end;
1866         }
1867     }
1868 
1869     ret = dp_ctrl_enable_stream_clocks(ctrl);
1870     if (ret) {
1871         DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1872         goto end;
1873     }
1874 
1875     if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl))
1876         dp_ctrl_link_retrain(ctrl);
1877 
1878     /* stop txing train pattern to end link training */
1879     dp_ctrl_clear_training_pattern(ctrl);
1880 
1881     /*
1882      * Set up transfer unit values and set controller state to send
1883      * video.
1884      */
1885     reinit_completion(&ctrl->video_comp);
1886 
1887     dp_ctrl_configure_source_params(ctrl);
1888 
1889     dp_catalog_ctrl_config_msa(ctrl->catalog,
1890         ctrl->link->link_params.rate,
1891         pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl));
1892 
1893     dp_ctrl_setup_tr_unit(ctrl);
1894 
1895     dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1896 
1897     ret = dp_ctrl_wait4video_ready(ctrl);
1898     if (ret)
1899         return ret;
1900 
1901     mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1902     drm_dbg_dp(ctrl->drm_dev,
1903         "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1904 
1905 end:
1906     return ret;
1907 }
1908 
1909 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1910 {
1911     struct dp_ctrl_private *ctrl;
1912     struct dp_io *dp_io;
1913     struct phy *phy;
1914     int ret;
1915 
1916     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1917     dp_io = &ctrl->parser->io;
1918     phy = dp_io->phy;
1919 
1920     /* set dongle to D3 (power off) mode */
1921     dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1922 
1923     dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1924 
1925     if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1926         ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1927         if (ret) {
1928             DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1929             return ret;
1930         }
1931     }
1932 
1933     dev_pm_opp_set_rate(ctrl->dev, 0);
1934     ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1935     if (ret) {
1936         DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1937         return ret;
1938     }
1939 
1940     phy_power_off(phy);
1941 
1942     /* aux channel down, reinit phy */
1943     phy_exit(phy);
1944     phy_init(phy);
1945 
1946     drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1947             phy, phy->init_count, phy->power_count);
1948     return ret;
1949 }
1950 
1951 int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl)
1952 {
1953     struct dp_ctrl_private *ctrl;
1954     struct dp_io *dp_io;
1955     struct phy *phy;
1956     int ret;
1957 
1958     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1959     dp_io = &ctrl->parser->io;
1960     phy = dp_io->phy;
1961 
1962     dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1963 
1964     ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1965     if (ret) {
1966         DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1967     }
1968 
1969     DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n",
1970         phy, phy->init_count, phy->power_count);
1971 
1972     phy_power_off(phy);
1973 
1974     DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n",
1975         phy, phy->init_count, phy->power_count);
1976 
1977     return ret;
1978 }
1979 
1980 int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
1981 {
1982     struct dp_ctrl_private *ctrl;
1983     struct dp_io *dp_io;
1984     struct phy *phy;
1985     int ret = 0;
1986 
1987     if (!dp_ctrl)
1988         return -EINVAL;
1989 
1990     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1991     dp_io = &ctrl->parser->io;
1992     phy = dp_io->phy;
1993 
1994     dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1995 
1996     dp_catalog_ctrl_reset(ctrl->catalog);
1997 
1998     ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1999     if (ret)
2000         DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
2001 
2002     dev_pm_opp_set_rate(ctrl->dev, 0);
2003     ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
2004     if (ret) {
2005         DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
2006     }
2007 
2008     phy_power_off(phy);
2009     drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
2010             phy, phy->init_count, phy->power_count);
2011 
2012     return ret;
2013 }
2014 
2015 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
2016 {
2017     struct dp_ctrl_private *ctrl;
2018     u32 isr;
2019 
2020     if (!dp_ctrl)
2021         return;
2022 
2023     ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
2024 
2025     isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
2026 
2027     if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
2028         drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n");
2029         complete(&ctrl->video_comp);
2030     }
2031 
2032     if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
2033         drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n");
2034         complete(&ctrl->idle_comp);
2035     }
2036 }
2037 
2038 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
2039             struct dp_panel *panel, struct drm_dp_aux *aux,
2040             struct dp_power *power, struct dp_catalog *catalog,
2041             struct dp_parser *parser)
2042 {
2043     struct dp_ctrl_private *ctrl;
2044     int ret;
2045 
2046     if (!dev || !panel || !aux ||
2047         !link || !catalog) {
2048         DRM_ERROR("invalid input\n");
2049         return ERR_PTR(-EINVAL);
2050     }
2051 
2052     ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2053     if (!ctrl) {
2054         DRM_ERROR("Mem allocation failure\n");
2055         return ERR_PTR(-ENOMEM);
2056     }
2057 
2058     ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
2059     if (ret) {
2060         dev_err(dev, "invalid DP OPP table in device tree\n");
2061         /* caller do PTR_ERR(opp_table) */
2062         return (struct dp_ctrl *)ERR_PTR(ret);
2063     }
2064 
2065     /* OPP table is optional */
2066     ret = devm_pm_opp_of_add_table(dev);
2067     if (ret)
2068         dev_err(dev, "failed to add DP OPP table\n");
2069 
2070     init_completion(&ctrl->idle_comp);
2071     init_completion(&ctrl->video_comp);
2072 
2073     /* in parameters */
2074     ctrl->parser   = parser;
2075     ctrl->panel    = panel;
2076     ctrl->power    = power;
2077     ctrl->aux      = aux;
2078     ctrl->link     = link;
2079     ctrl->catalog  = catalog;
2080     ctrl->dev      = dev;
2081 
2082     return &ctrl->dp_ctrl;
2083 }
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