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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
0007 
0008 #include <linux/delay.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/phy/phy.h>
0011 #include <linux/phy/phy-dp.h>
0012 #include <linux/rational.h>
0013 #include <drm/display/drm_dp_helper.h>
0014 #include <drm/drm_print.h>
0015 
0016 #include "dp_catalog.h"
0017 #include "dp_reg.h"
0018 
0019 #define POLLING_SLEEP_US            1000
0020 #define POLLING_TIMEOUT_US          10000
0021 
0022 #define SCRAMBLER_RESET_COUNT_VALUE     0xFC
0023 
0024 #define DP_INTERRUPT_STATUS_ACK_SHIFT   1
0025 #define DP_INTERRUPT_STATUS_MASK_SHIFT  2
0026 
0027 #define DP_INTF_CONFIG_DATABUS_WIDEN     BIT(4)
0028 
0029 #define DP_INTERRUPT_STATUS1 \
0030     (DP_INTR_AUX_I2C_DONE| \
0031     DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
0032     DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \
0033     DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \
0034     DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR)
0035 
0036 #define DP_INTERRUPT_STATUS1_ACK \
0037     (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_ACK_SHIFT)
0038 #define DP_INTERRUPT_STATUS1_MASK \
0039     (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_MASK_SHIFT)
0040 
0041 #define DP_INTERRUPT_STATUS2 \
0042     (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
0043     DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
0044 
0045 #define DP_INTERRUPT_STATUS2_ACK \
0046     (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_ACK_SHIFT)
0047 #define DP_INTERRUPT_STATUS2_MASK \
0048     (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
0049 
0050 struct dp_catalog_private {
0051     struct device *dev;
0052     struct drm_device *drm_dev;
0053     struct dp_io *io;
0054     u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
0055     struct dp_catalog dp_catalog;
0056     u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX];
0057 };
0058 
0059 void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state)
0060 {
0061     struct dp_catalog_private *catalog = container_of(dp_catalog,
0062             struct dp_catalog_private, dp_catalog);
0063     struct dss_io_data *dss = &catalog->io->dp_controller;
0064 
0065     msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_ahb");
0066     msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base, "dp_aux");
0067     msm_disp_snapshot_add_block(disp_state, dss->link.len, dss->link.base, "dp_link");
0068     msm_disp_snapshot_add_block(disp_state, dss->p0.len, dss->p0.base, "dp_p0");
0069 }
0070 
0071 static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset)
0072 {
0073     return readl_relaxed(catalog->io->dp_controller.aux.base + offset);
0074 }
0075 
0076 static inline void dp_write_aux(struct dp_catalog_private *catalog,
0077                    u32 offset, u32 data)
0078 {
0079     /*
0080      * To make sure aux reg writes happens before any other operation,
0081      * this function uses writel() instread of writel_relaxed()
0082      */
0083     writel(data, catalog->io->dp_controller.aux.base + offset);
0084 }
0085 
0086 static inline u32 dp_read_ahb(const struct dp_catalog_private *catalog, u32 offset)
0087 {
0088     return readl_relaxed(catalog->io->dp_controller.ahb.base + offset);
0089 }
0090 
0091 static inline void dp_write_ahb(struct dp_catalog_private *catalog,
0092                    u32 offset, u32 data)
0093 {
0094     /*
0095      * To make sure phy reg writes happens before any other operation,
0096      * this function uses writel() instread of writel_relaxed()
0097      */
0098     writel(data, catalog->io->dp_controller.ahb.base + offset);
0099 }
0100 
0101 static inline void dp_write_p0(struct dp_catalog_private *catalog,
0102                    u32 offset, u32 data)
0103 {
0104     /*
0105      * To make sure interface reg writes happens before any other operation,
0106      * this function uses writel() instread of writel_relaxed()
0107      */
0108     writel(data, catalog->io->dp_controller.p0.base + offset);
0109 }
0110 
0111 static inline u32 dp_read_p0(struct dp_catalog_private *catalog,
0112                    u32 offset)
0113 {
0114     /*
0115      * To make sure interface reg writes happens before any other operation,
0116      * this function uses writel() instread of writel_relaxed()
0117      */
0118     return readl_relaxed(catalog->io->dp_controller.p0.base + offset);
0119 }
0120 
0121 static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset)
0122 {
0123     return readl_relaxed(catalog->io->dp_controller.link.base + offset);
0124 }
0125 
0126 static inline void dp_write_link(struct dp_catalog_private *catalog,
0127                    u32 offset, u32 data)
0128 {
0129     /*
0130      * To make sure link reg writes happens before any other operation,
0131      * this function uses writel() instread of writel_relaxed()
0132      */
0133     writel(data, catalog->io->dp_controller.link.base + offset);
0134 }
0135 
0136 /* aux related catalog functions */
0137 u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog)
0138 {
0139     struct dp_catalog_private *catalog = container_of(dp_catalog,
0140                 struct dp_catalog_private, dp_catalog);
0141 
0142     return dp_read_aux(catalog, REG_DP_AUX_DATA);
0143 }
0144 
0145 int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog)
0146 {
0147     struct dp_catalog_private *catalog = container_of(dp_catalog,
0148                 struct dp_catalog_private, dp_catalog);
0149 
0150     dp_write_aux(catalog, REG_DP_AUX_DATA, dp_catalog->aux_data);
0151     return 0;
0152 }
0153 
0154 int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog)
0155 {
0156     struct dp_catalog_private *catalog = container_of(dp_catalog,
0157                 struct dp_catalog_private, dp_catalog);
0158 
0159     dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, dp_catalog->aux_data);
0160     return 0;
0161 }
0162 
0163 int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read)
0164 {
0165     u32 data;
0166     struct dp_catalog_private *catalog = container_of(dp_catalog,
0167                 struct dp_catalog_private, dp_catalog);
0168 
0169     if (read) {
0170         data = dp_read_aux(catalog, REG_DP_AUX_TRANS_CTRL);
0171         data &= ~DP_AUX_TRANS_CTRL_GO;
0172         dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data);
0173     } else {
0174         dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, 0);
0175     }
0176     return 0;
0177 }
0178 
0179 int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog)
0180 {
0181     struct dp_catalog_private *catalog = container_of(dp_catalog,
0182                 struct dp_catalog_private, dp_catalog);
0183 
0184     dp_read_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS);
0185     dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f);
0186     dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f);
0187     dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0);
0188     return 0;
0189 }
0190 
0191 /**
0192  * dp_catalog_aux_reset() - reset AUX controller
0193  *
0194  * @dp_catalog: DP catalog structure
0195  *
0196  * return: void
0197  *
0198  * This function reset AUX controller
0199  *
0200  * NOTE: reset AUX controller will also clear any pending HPD related interrupts
0201  * 
0202  */
0203 void dp_catalog_aux_reset(struct dp_catalog *dp_catalog)
0204 {
0205     u32 aux_ctrl;
0206     struct dp_catalog_private *catalog = container_of(dp_catalog,
0207                 struct dp_catalog_private, dp_catalog);
0208 
0209     aux_ctrl = dp_read_aux(catalog, REG_DP_AUX_CTRL);
0210 
0211     aux_ctrl |= DP_AUX_CTRL_RESET;
0212     dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
0213     usleep_range(1000, 1100); /* h/w recommended delay */
0214 
0215     aux_ctrl &= ~DP_AUX_CTRL_RESET;
0216     dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
0217 }
0218 
0219 void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable)
0220 {
0221     u32 aux_ctrl;
0222     struct dp_catalog_private *catalog = container_of(dp_catalog,
0223                 struct dp_catalog_private, dp_catalog);
0224 
0225     aux_ctrl = dp_read_aux(catalog, REG_DP_AUX_CTRL);
0226 
0227     if (enable) {
0228         dp_write_aux(catalog, REG_DP_TIMEOUT_COUNT, 0xffff);
0229         dp_write_aux(catalog, REG_DP_AUX_LIMITS, 0xffff);
0230         aux_ctrl |= DP_AUX_CTRL_ENABLE;
0231     } else {
0232         aux_ctrl &= ~DP_AUX_CTRL_ENABLE;
0233     }
0234 
0235     dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
0236 }
0237 
0238 void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog)
0239 {
0240     struct dp_catalog_private *catalog = container_of(dp_catalog,
0241                 struct dp_catalog_private, dp_catalog);
0242     struct dp_io *dp_io = catalog->io;
0243     struct phy *phy = dp_io->phy;
0244 
0245     phy_calibrate(phy);
0246 }
0247 
0248 int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog)
0249 {
0250     u32 state;
0251     struct dp_catalog_private *catalog = container_of(dp_catalog,
0252                 struct dp_catalog_private, dp_catalog);
0253 
0254     /* poll for hpd connected status every 2ms and timeout after 500ms */
0255     return readl_poll_timeout(catalog->io->dp_controller.aux.base +
0256                 REG_DP_DP_HPD_INT_STATUS,
0257                 state, state & DP_DP_HPD_STATE_STATUS_CONNECTED,
0258                 2000, 500000);
0259 }
0260 
0261 static void dump_regs(void __iomem *base, int len)
0262 {
0263     int i;
0264     u32 x0, x4, x8, xc;
0265     u32 addr_off = 0;
0266 
0267     len = DIV_ROUND_UP(len, 16);
0268     for (i = 0; i < len; i++) {
0269         x0 = readl_relaxed(base + addr_off);
0270         x4 = readl_relaxed(base + addr_off + 0x04);
0271         x8 = readl_relaxed(base + addr_off + 0x08);
0272         xc = readl_relaxed(base + addr_off + 0x0c);
0273 
0274         pr_info("%08x: %08x %08x %08x %08x", addr_off, x0, x4, x8, xc);
0275         addr_off += 16;
0276     }
0277 }
0278 
0279 void dp_catalog_dump_regs(struct dp_catalog *dp_catalog)
0280 {
0281     struct dp_catalog_private *catalog = container_of(dp_catalog,
0282         struct dp_catalog_private, dp_catalog);
0283     struct dss_io_data *io = &catalog->io->dp_controller;
0284 
0285     pr_info("AHB regs\n");
0286     dump_regs(io->ahb.base, io->ahb.len);
0287 
0288     pr_info("AUXCLK regs\n");
0289     dump_regs(io->aux.base, io->aux.len);
0290 
0291     pr_info("LCLK regs\n");
0292     dump_regs(io->link.base, io->link.len);
0293 
0294     pr_info("P0CLK regs\n");
0295     dump_regs(io->p0.base, io->p0.len);
0296 }
0297 
0298 u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
0299 {
0300     struct dp_catalog_private *catalog = container_of(dp_catalog,
0301                 struct dp_catalog_private, dp_catalog);
0302     u32 intr, intr_ack;
0303 
0304     intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS);
0305     intr &= ~DP_INTERRUPT_STATUS1_MASK;
0306     intr_ack = (intr & DP_INTERRUPT_STATUS1)
0307             << DP_INTERRUPT_STATUS_ACK_SHIFT;
0308     dp_write_ahb(catalog, REG_DP_INTR_STATUS, intr_ack |
0309             DP_INTERRUPT_STATUS1_MASK);
0310 
0311     return intr;
0312 
0313 }
0314 
0315 /* controller related catalog functions */
0316 void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
0317                 u32 dp_tu, u32 valid_boundary,
0318                 u32 valid_boundary2)
0319 {
0320     struct dp_catalog_private *catalog = container_of(dp_catalog,
0321                 struct dp_catalog_private, dp_catalog);
0322 
0323     dp_write_link(catalog, REG_DP_VALID_BOUNDARY, valid_boundary);
0324     dp_write_link(catalog, REG_DP_TU, dp_tu);
0325     dp_write_link(catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2);
0326 }
0327 
0328 void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state)
0329 {
0330     struct dp_catalog_private *catalog = container_of(dp_catalog,
0331                 struct dp_catalog_private, dp_catalog);
0332 
0333     dp_write_link(catalog, REG_DP_STATE_CTRL, state);
0334 }
0335 
0336 void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 cfg)
0337 {
0338     struct dp_catalog_private *catalog = container_of(dp_catalog,
0339                 struct dp_catalog_private, dp_catalog);
0340 
0341     drm_dbg_dp(catalog->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", cfg);
0342 
0343     dp_write_link(catalog, REG_DP_CONFIGURATION_CTRL, cfg);
0344 }
0345 
0346 void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog)
0347 {
0348     struct dp_catalog_private *catalog = container_of(dp_catalog,
0349                 struct dp_catalog_private, dp_catalog);
0350     u32 ln_0 = 0, ln_1 = 1, ln_2 = 2, ln_3 = 3; /* One-to-One mapping */
0351     u32 ln_mapping;
0352 
0353     ln_mapping = ln_0 << LANE0_MAPPING_SHIFT;
0354     ln_mapping |= ln_1 << LANE1_MAPPING_SHIFT;
0355     ln_mapping |= ln_2 << LANE2_MAPPING_SHIFT;
0356     ln_mapping |= ln_3 << LANE3_MAPPING_SHIFT;
0357 
0358     dp_write_link(catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING,
0359             ln_mapping);
0360 }
0361 
0362 void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
0363                         bool enable)
0364 {
0365     u32 mainlink_ctrl;
0366     struct dp_catalog_private *catalog = container_of(dp_catalog,
0367                 struct dp_catalog_private, dp_catalog);
0368 
0369     drm_dbg_dp(catalog->drm_dev, "enable=%d\n", enable);
0370     if (enable) {
0371         /*
0372          * To make sure link reg writes happens before other operation,
0373          * dp_write_link() function uses writel()
0374          */
0375         mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
0376 
0377         mainlink_ctrl &= ~(DP_MAINLINK_CTRL_RESET |
0378                         DP_MAINLINK_CTRL_ENABLE);
0379         dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
0380 
0381         mainlink_ctrl |= DP_MAINLINK_CTRL_RESET;
0382         dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
0383 
0384         mainlink_ctrl &= ~DP_MAINLINK_CTRL_RESET;
0385         dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
0386 
0387         mainlink_ctrl |= (DP_MAINLINK_CTRL_ENABLE |
0388                     DP_MAINLINK_FB_BOUNDARY_SEL);
0389         dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
0390     } else {
0391         mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
0392         mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE;
0393         dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
0394     }
0395 }
0396 
0397 void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog,
0398                     u32 colorimetry_cfg,
0399                     u32 test_bits_depth)
0400 {
0401     u32 misc_val;
0402     struct dp_catalog_private *catalog = container_of(dp_catalog,
0403                 struct dp_catalog_private, dp_catalog);
0404 
0405     misc_val = dp_read_link(catalog, REG_DP_MISC1_MISC0);
0406 
0407     /* clear bpp bits */
0408     misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT);
0409     misc_val |= colorimetry_cfg << DP_MISC0_COLORIMETRY_CFG_SHIFT;
0410     misc_val |= test_bits_depth << DP_MISC0_TEST_BITS_DEPTH_SHIFT;
0411     /* Configure clock to synchronous mode */
0412     misc_val |= DP_MISC0_SYNCHRONOUS_CLK;
0413 
0414     drm_dbg_dp(catalog->drm_dev, "misc settings = 0x%x\n", misc_val);
0415     dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val);
0416 }
0417 
0418 void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
0419                     u32 rate, u32 stream_rate_khz,
0420                     bool fixed_nvid)
0421 {
0422     u32 pixel_m, pixel_n;
0423     u32 mvid, nvid, pixel_div = 0, dispcc_input_rate;
0424     u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE;
0425     u32 const link_rate_hbr2 = 540000;
0426     u32 const link_rate_hbr3 = 810000;
0427     unsigned long den, num;
0428 
0429     struct dp_catalog_private *catalog = container_of(dp_catalog,
0430                 struct dp_catalog_private, dp_catalog);
0431 
0432     if (rate == link_rate_hbr3)
0433         pixel_div = 6;
0434     else if (rate == 1620000 || rate == 270000)
0435         pixel_div = 2;
0436     else if (rate == link_rate_hbr2)
0437         pixel_div = 4;
0438     else
0439         DRM_ERROR("Invalid pixel mux divider\n");
0440 
0441     dispcc_input_rate = (rate * 10) / pixel_div;
0442 
0443     rational_best_approximation(dispcc_input_rate, stream_rate_khz,
0444             (unsigned long)(1 << 16) - 1,
0445             (unsigned long)(1 << 16) - 1, &den, &num);
0446 
0447     den = ~(den - num);
0448     den = den & 0xFFFF;
0449     pixel_m = num;
0450     pixel_n = den;
0451 
0452     mvid = (pixel_m & 0xFFFF) * 5;
0453     nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
0454 
0455     if (nvid < nvid_fixed) {
0456         u32 temp;
0457 
0458         temp = (nvid_fixed / nvid) * nvid;
0459         mvid = (nvid_fixed / nvid) * mvid;
0460         nvid = temp;
0461     }
0462 
0463     if (link_rate_hbr2 == rate)
0464         nvid *= 2;
0465 
0466     if (link_rate_hbr3 == rate)
0467         nvid *= 3;
0468 
0469     drm_dbg_dp(catalog->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid);
0470     dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid);
0471     dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid);
0472     dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0);
0473 }
0474 
0475 int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog,
0476                     u32 state_bit)
0477 {
0478     int bit, ret;
0479     u32 data;
0480     struct dp_catalog_private *catalog = container_of(dp_catalog,
0481                 struct dp_catalog_private, dp_catalog);
0482 
0483     bit = BIT(state_bit - 1);
0484     drm_dbg_dp(catalog->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit);
0485     dp_catalog_ctrl_state_ctrl(dp_catalog, bit);
0486 
0487     bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT;
0488 
0489     /* Poll for mainlink ready status */
0490     ret = readx_poll_timeout(readl, catalog->io->dp_controller.link.base +
0491                     REG_DP_MAINLINK_READY,
0492                     data, data & bit,
0493                     POLLING_SLEEP_US, POLLING_TIMEOUT_US);
0494     if (ret < 0) {
0495         DRM_ERROR("set state_bit for link_train=%d failed\n", state_bit);
0496         return ret;
0497     }
0498     return 0;
0499 }
0500 
0501 /**
0502  * dp_catalog_hw_revision() - retrieve DP hw revision
0503  *
0504  * @dp_catalog: DP catalog structure
0505  *
0506  * Return: DP controller hw revision
0507  *
0508  */
0509 u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog)
0510 {
0511     const struct dp_catalog_private *catalog = container_of(dp_catalog,
0512                 struct dp_catalog_private, dp_catalog);
0513 
0514     return dp_read_ahb(catalog, REG_DP_HW_VERSION);
0515 }
0516 
0517 /**
0518  * dp_catalog_ctrl_reset() - reset DP controller
0519  *
0520  * @dp_catalog: DP catalog structure
0521  *
0522  * return: void
0523  *
0524  * This function reset the DP controller
0525  *
0526  * NOTE: reset DP controller will also clear any pending HPD related interrupts
0527  * 
0528  */
0529 void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog)
0530 {
0531     u32 sw_reset;
0532     struct dp_catalog_private *catalog = container_of(dp_catalog,
0533                 struct dp_catalog_private, dp_catalog);
0534 
0535     sw_reset = dp_read_ahb(catalog, REG_DP_SW_RESET);
0536 
0537     sw_reset |= DP_SW_RESET;
0538     dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset);
0539     usleep_range(1000, 1100); /* h/w recommended delay */
0540 
0541     sw_reset &= ~DP_SW_RESET;
0542     dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset);
0543 }
0544 
0545 bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog)
0546 {
0547     u32 data;
0548     int ret;
0549     struct dp_catalog_private *catalog = container_of(dp_catalog,
0550                 struct dp_catalog_private, dp_catalog);
0551 
0552     /* Poll for mainlink ready status */
0553     ret = readl_poll_timeout(catalog->io->dp_controller.link.base +
0554                 REG_DP_MAINLINK_READY,
0555                 data, data & DP_MAINLINK_READY_FOR_VIDEO,
0556                 POLLING_SLEEP_US, POLLING_TIMEOUT_US);
0557     if (ret < 0) {
0558         DRM_ERROR("mainlink not ready\n");
0559         return false;
0560     }
0561 
0562     return true;
0563 }
0564 
0565 void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog,
0566                         bool enable)
0567 {
0568     struct dp_catalog_private *catalog = container_of(dp_catalog,
0569                 struct dp_catalog_private, dp_catalog);
0570 
0571     if (enable) {
0572         dp_write_ahb(catalog, REG_DP_INTR_STATUS,
0573                 DP_INTERRUPT_STATUS1_MASK);
0574         dp_write_ahb(catalog, REG_DP_INTR_STATUS2,
0575                 DP_INTERRUPT_STATUS2_MASK);
0576     } else {
0577         dp_write_ahb(catalog, REG_DP_INTR_STATUS, 0x00);
0578         dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 0x00);
0579     }
0580 }
0581 
0582 void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
0583             u32 intr_mask, bool en)
0584 {
0585     struct dp_catalog_private *catalog = container_of(dp_catalog,
0586                 struct dp_catalog_private, dp_catalog);
0587 
0588     u32 config = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK);
0589 
0590     config = (en ? config | intr_mask : config & ~intr_mask);
0591 
0592     drm_dbg_dp(catalog->drm_dev, "intr_mask=%#x config=%#x\n",
0593                     intr_mask, config);
0594     dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK,
0595                 config & DP_DP_HPD_INT_MASK);
0596 }
0597 
0598 void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
0599 {
0600     struct dp_catalog_private *catalog = container_of(dp_catalog,
0601                 struct dp_catalog_private, dp_catalog);
0602 
0603     u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
0604 
0605     /* Configure REFTIMER and enable it */
0606     reftimer |= DP_DP_HPD_REFTIMER_ENABLE;
0607     dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer);
0608 
0609     /* Enable HPD */
0610     dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
0611 }
0612 
0613 u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog)
0614 {
0615     struct dp_catalog_private *catalog = container_of(dp_catalog,
0616                 struct dp_catalog_private, dp_catalog);
0617     u32 status;
0618 
0619     status = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS);
0620     drm_dbg_dp(catalog->drm_dev, "aux status: %#x\n", status);
0621     status >>= DP_DP_HPD_STATE_STATUS_BITS_SHIFT;
0622     status &= DP_DP_HPD_STATE_STATUS_BITS_MASK;
0623 
0624     return status;
0625 }
0626 
0627 u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
0628 {
0629     struct dp_catalog_private *catalog = container_of(dp_catalog,
0630                 struct dp_catalog_private, dp_catalog);
0631     int isr, mask;
0632 
0633     isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS);
0634     dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK,
0635                  (isr & DP_DP_HPD_INT_MASK));
0636     mask = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK);
0637 
0638     /*
0639      * We only want to return interrupts that are unmasked to the caller.
0640      * However, the interrupt status field also contains other
0641      * informational bits about the HPD state status, so we only mask
0642      * out the part of the register that tells us about which interrupts
0643      * are pending.
0644      */
0645     return isr & (mask | ~DP_DP_HPD_INT_MASK);
0646 }
0647 
0648 int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
0649 {
0650     struct dp_catalog_private *catalog = container_of(dp_catalog,
0651                 struct dp_catalog_private, dp_catalog);
0652     u32 intr, intr_ack;
0653 
0654     intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS2);
0655     intr &= ~DP_INTERRUPT_STATUS2_MASK;
0656     intr_ack = (intr & DP_INTERRUPT_STATUS2)
0657             << DP_INTERRUPT_STATUS_ACK_SHIFT;
0658     dp_write_ahb(catalog, REG_DP_INTR_STATUS2,
0659             intr_ack | DP_INTERRUPT_STATUS2_MASK);
0660 
0661     return intr;
0662 }
0663 
0664 void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog)
0665 {
0666     struct dp_catalog_private *catalog = container_of(dp_catalog,
0667                 struct dp_catalog_private, dp_catalog);
0668 
0669     dp_write_ahb(catalog, REG_DP_PHY_CTRL,
0670             DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL);
0671     usleep_range(1000, 1100); /* h/w recommended delay */
0672     dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0);
0673 }
0674 
0675 int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog,
0676         u8 v_level, u8 p_level)
0677 {
0678     struct dp_catalog_private *catalog = container_of(dp_catalog,
0679                 struct dp_catalog_private, dp_catalog);
0680     struct dp_io *dp_io = catalog->io;
0681     struct phy *phy = dp_io->phy;
0682     struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
0683 
0684     /* TODO: Update for all lanes instead of just first one */
0685     opts_dp->voltage[0] = v_level;
0686     opts_dp->pre[0] = p_level;
0687     opts_dp->set_voltages = 1;
0688     phy_configure(phy, &dp_io->phy_opts);
0689     opts_dp->set_voltages = 0;
0690 
0691     return 0;
0692 }
0693 
0694 void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog,
0695             u32 pattern)
0696 {
0697     struct dp_catalog_private *catalog = container_of(dp_catalog,
0698                 struct dp_catalog_private, dp_catalog);
0699     u32 value = 0x0;
0700 
0701     /* Make sure to clear the current pattern before starting a new one */
0702     dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0);
0703 
0704     drm_dbg_dp(catalog->drm_dev, "pattern: %#x\n", pattern);
0705     switch (pattern) {
0706     case DP_PHY_TEST_PATTERN_D10_2:
0707         dp_write_link(catalog, REG_DP_STATE_CTRL,
0708                 DP_STATE_CTRL_LINK_TRAINING_PATTERN1);
0709         break;
0710     case DP_PHY_TEST_PATTERN_ERROR_COUNT:
0711         value &= ~(1 << 16);
0712         dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
0713                     value);
0714         value |= SCRAMBLER_RESET_COUNT_VALUE;
0715         dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
0716                     value);
0717         dp_write_link(catalog, REG_DP_MAINLINK_LEVELS,
0718                     DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2);
0719         dp_write_link(catalog, REG_DP_STATE_CTRL,
0720                     DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE);
0721         break;
0722     case DP_PHY_TEST_PATTERN_PRBS7:
0723         dp_write_link(catalog, REG_DP_STATE_CTRL,
0724                 DP_STATE_CTRL_LINK_PRBS7);
0725         break;
0726     case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
0727         dp_write_link(catalog, REG_DP_STATE_CTRL,
0728                 DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN);
0729         /* 00111110000011111000001111100000 */
0730         dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0,
0731                 0x3E0F83E0);
0732         /* 00001111100000111110000011111000 */
0733         dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1,
0734                 0x0F83E0F8);
0735         /* 1111100000111110 */
0736         dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2,
0737                 0x0000F83E);
0738         break;
0739     case DP_PHY_TEST_PATTERN_CP2520:
0740         value = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
0741         value &= ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER;
0742         dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value);
0743 
0744         value = DP_HBR2_ERM_PATTERN;
0745         dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
0746                 value);
0747         value |= SCRAMBLER_RESET_COUNT_VALUE;
0748         dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
0749                     value);
0750         dp_write_link(catalog, REG_DP_MAINLINK_LEVELS,
0751                     DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2);
0752         dp_write_link(catalog, REG_DP_STATE_CTRL,
0753                     DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE);
0754         value = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
0755         value |= DP_MAINLINK_CTRL_ENABLE;
0756         dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value);
0757         break;
0758     case DP_PHY_TEST_PATTERN_SEL_MASK:
0759         dp_write_link(catalog, REG_DP_MAINLINK_CTRL,
0760                 DP_MAINLINK_CTRL_ENABLE);
0761         dp_write_link(catalog, REG_DP_STATE_CTRL,
0762                 DP_STATE_CTRL_LINK_TRAINING_PATTERN4);
0763         break;
0764     default:
0765         drm_dbg_dp(catalog->drm_dev,
0766                 "No valid test pattern requested: %#x\n", pattern);
0767         break;
0768     }
0769 }
0770 
0771 u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog)
0772 {
0773     struct dp_catalog_private *catalog = container_of(dp_catalog,
0774                 struct dp_catalog_private, dp_catalog);
0775 
0776     return dp_read_link(catalog, REG_DP_MAINLINK_READY);
0777 }
0778 
0779 /* panel related catalog functions */
0780 int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog)
0781 {
0782     struct dp_catalog_private *catalog = container_of(dp_catalog,
0783                 struct dp_catalog_private, dp_catalog);
0784     u32 reg;
0785 
0786     dp_write_link(catalog, REG_DP_TOTAL_HOR_VER,
0787                 dp_catalog->total);
0788     dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC,
0789                 dp_catalog->sync_start);
0790     dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,
0791                 dp_catalog->width_blanking);
0792     dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);
0793 
0794     reg = dp_read_p0(catalog, MMSS_DP_INTF_CONFIG);
0795 
0796     if (dp_catalog->wide_bus_en)
0797         reg |= DP_INTF_CONFIG_DATABUS_WIDEN;
0798     else
0799         reg &= ~DP_INTF_CONFIG_DATABUS_WIDEN;
0800 
0801 
0802     DRM_DEBUG_DP("wide_bus_en=%d reg=%#x\n", dp_catalog->wide_bus_en, reg);
0803 
0804     dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg);
0805     return 0;
0806 }
0807 
0808 void dp_catalog_panel_tpg_enable(struct dp_catalog *dp_catalog,
0809                 struct drm_display_mode *drm_mode)
0810 {
0811     struct dp_catalog_private *catalog = container_of(dp_catalog,
0812                 struct dp_catalog_private, dp_catalog);
0813     u32 hsync_period, vsync_period;
0814     u32 display_v_start, display_v_end;
0815     u32 hsync_start_x, hsync_end_x;
0816     u32 v_sync_width;
0817     u32 hsync_ctl;
0818     u32 display_hctl;
0819 
0820     /* TPG config parameters*/
0821     hsync_period = drm_mode->htotal;
0822     vsync_period = drm_mode->vtotal;
0823 
0824     display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) *
0825                     hsync_period);
0826     display_v_end = ((vsync_period - (drm_mode->vsync_start -
0827                     drm_mode->vdisplay))
0828                     * hsync_period) - 1;
0829 
0830     display_v_start += drm_mode->htotal - drm_mode->hsync_start;
0831     display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay);
0832 
0833     hsync_start_x = drm_mode->htotal - drm_mode->hsync_start;
0834     hsync_end_x = hsync_period - (drm_mode->hsync_start -
0835                     drm_mode->hdisplay) - 1;
0836 
0837     v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start;
0838 
0839     hsync_ctl = (hsync_period << 16) |
0840             (drm_mode->hsync_end - drm_mode->hsync_start);
0841     display_hctl = (hsync_end_x << 16) | hsync_start_x;
0842 
0843 
0844     dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0x0);
0845     dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl);
0846     dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period *
0847             hsync_period);
0848     dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width *
0849             hsync_period);
0850     dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
0851     dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);
0852     dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl);
0853     dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0);
0854     dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start);
0855     dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end);
0856     dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0);
0857     dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
0858     dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
0859     dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
0860     dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
0861     dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
0862     dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0);
0863 
0864     dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL,
0865                 DP_TPG_CHECKERED_RECT_PATTERN);
0866     dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG,
0867                 DP_TPG_VIDEO_CONFIG_BPP_8BIT |
0868                 DP_TPG_VIDEO_CONFIG_RGB);
0869     dp_write_p0(catalog, MMSS_DP_BIST_ENABLE,
0870                 DP_BIST_ENABLE_DPBIST_EN);
0871     dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN,
0872                 DP_TIMING_ENGINE_EN_EN);
0873     drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__);
0874 }
0875 
0876 void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog)
0877 {
0878     struct dp_catalog_private *catalog = container_of(dp_catalog,
0879                 struct dp_catalog_private, dp_catalog);
0880 
0881     dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0);
0882     dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0);
0883     dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0);
0884 }
0885 
0886 struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_io *io)
0887 {
0888     struct dp_catalog_private *catalog;
0889 
0890     if (!io) {
0891         DRM_ERROR("invalid input\n");
0892         return ERR_PTR(-EINVAL);
0893     }
0894 
0895     catalog  = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL);
0896     if (!catalog)
0897         return ERR_PTR(-ENOMEM);
0898 
0899     catalog->dev = dev;
0900     catalog->io = io;
0901 
0902     return &catalog->dp_catalog;
0903 }
0904 
0905 void dp_catalog_audio_get_header(struct dp_catalog *dp_catalog)
0906 {
0907     struct dp_catalog_private *catalog;
0908     u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
0909     enum dp_catalog_audio_sdp_type sdp;
0910     enum dp_catalog_audio_header_type header;
0911 
0912     if (!dp_catalog)
0913         return;
0914 
0915     catalog = container_of(dp_catalog,
0916         struct dp_catalog_private, dp_catalog);
0917 
0918     sdp_map = catalog->audio_map;
0919     sdp     = dp_catalog->sdp_type;
0920     header  = dp_catalog->sdp_header;
0921 
0922     dp_catalog->audio_data = dp_read_link(catalog,
0923             sdp_map[sdp][header]);
0924 }
0925 
0926 void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog)
0927 {
0928     struct dp_catalog_private *catalog;
0929     u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
0930     enum dp_catalog_audio_sdp_type sdp;
0931     enum dp_catalog_audio_header_type header;
0932     u32 data;
0933 
0934     if (!dp_catalog)
0935         return;
0936 
0937     catalog = container_of(dp_catalog,
0938         struct dp_catalog_private, dp_catalog);
0939 
0940     sdp_map = catalog->audio_map;
0941     sdp     = dp_catalog->sdp_type;
0942     header  = dp_catalog->sdp_header;
0943     data    = dp_catalog->audio_data;
0944 
0945     dp_write_link(catalog, sdp_map[sdp][header], data);
0946 }
0947 
0948 void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog)
0949 {
0950     struct dp_catalog_private *catalog;
0951     u32 acr_ctrl, select;
0952 
0953     if (!dp_catalog)
0954         return;
0955 
0956     catalog = container_of(dp_catalog,
0957         struct dp_catalog_private, dp_catalog);
0958 
0959     select = dp_catalog->audio_data;
0960     acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
0961 
0962     drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n",
0963                     select, acr_ctrl);
0964 
0965     dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
0966 }
0967 
0968 void dp_catalog_audio_enable(struct dp_catalog *dp_catalog)
0969 {
0970     struct dp_catalog_private *catalog;
0971     bool enable;
0972     u32 audio_ctrl;
0973 
0974     if (!dp_catalog)
0975         return;
0976 
0977     catalog = container_of(dp_catalog,
0978         struct dp_catalog_private, dp_catalog);
0979 
0980     enable = !!dp_catalog->audio_data;
0981     audio_ctrl = dp_read_link(catalog, MMSS_DP_AUDIO_CFG);
0982 
0983     if (enable)
0984         audio_ctrl |= BIT(0);
0985     else
0986         audio_ctrl &= ~BIT(0);
0987 
0988     drm_dbg_dp(catalog->drm_dev, "dp_audio_cfg = 0x%x\n", audio_ctrl);
0989 
0990     dp_write_link(catalog, MMSS_DP_AUDIO_CFG, audio_ctrl);
0991     /* make sure audio engine is disabled */
0992     wmb();
0993 }
0994 
0995 void dp_catalog_audio_config_sdp(struct dp_catalog *dp_catalog)
0996 {
0997     struct dp_catalog_private *catalog;
0998     u32 sdp_cfg = 0;
0999     u32 sdp_cfg2 = 0;
1000 
1001     if (!dp_catalog)
1002         return;
1003 
1004     catalog = container_of(dp_catalog,
1005         struct dp_catalog_private, dp_catalog);
1006 
1007     sdp_cfg = dp_read_link(catalog, MMSS_DP_SDP_CFG);
1008     /* AUDIO_TIMESTAMP_SDP_EN */
1009     sdp_cfg |= BIT(1);
1010     /* AUDIO_STREAM_SDP_EN */
1011     sdp_cfg |= BIT(2);
1012     /* AUDIO_COPY_MANAGEMENT_SDP_EN */
1013     sdp_cfg |= BIT(5);
1014     /* AUDIO_ISRC_SDP_EN  */
1015     sdp_cfg |= BIT(6);
1016     /* AUDIO_INFOFRAME_SDP_EN  */
1017     sdp_cfg |= BIT(20);
1018 
1019     drm_dbg_dp(catalog->drm_dev, "sdp_cfg = 0x%x\n", sdp_cfg);
1020 
1021     dp_write_link(catalog, MMSS_DP_SDP_CFG, sdp_cfg);
1022 
1023     sdp_cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2);
1024     /* IFRM_REGSRC -> Do not use reg values */
1025     sdp_cfg2 &= ~BIT(0);
1026     /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */
1027     sdp_cfg2 &= ~BIT(1);
1028 
1029     drm_dbg_dp(catalog->drm_dev, "sdp_cfg2 = 0x%x\n", sdp_cfg2);
1030 
1031     dp_write_link(catalog, MMSS_DP_SDP_CFG2, sdp_cfg2);
1032 }
1033 
1034 void dp_catalog_audio_init(struct dp_catalog *dp_catalog)
1035 {
1036     struct dp_catalog_private *catalog;
1037 
1038     static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] = {
1039         {
1040             MMSS_DP_AUDIO_STREAM_0,
1041             MMSS_DP_AUDIO_STREAM_1,
1042             MMSS_DP_AUDIO_STREAM_1,
1043         },
1044         {
1045             MMSS_DP_AUDIO_TIMESTAMP_0,
1046             MMSS_DP_AUDIO_TIMESTAMP_1,
1047             MMSS_DP_AUDIO_TIMESTAMP_1,
1048         },
1049         {
1050             MMSS_DP_AUDIO_INFOFRAME_0,
1051             MMSS_DP_AUDIO_INFOFRAME_1,
1052             MMSS_DP_AUDIO_INFOFRAME_1,
1053         },
1054         {
1055             MMSS_DP_AUDIO_COPYMANAGEMENT_0,
1056             MMSS_DP_AUDIO_COPYMANAGEMENT_1,
1057             MMSS_DP_AUDIO_COPYMANAGEMENT_1,
1058         },
1059         {
1060             MMSS_DP_AUDIO_ISRC_0,
1061             MMSS_DP_AUDIO_ISRC_1,
1062             MMSS_DP_AUDIO_ISRC_1,
1063         },
1064     };
1065 
1066     if (!dp_catalog)
1067         return;
1068 
1069     catalog = container_of(dp_catalog,
1070         struct dp_catalog_private, dp_catalog);
1071 
1072     catalog->audio_map = sdp_map;
1073 }
1074 
1075 void dp_catalog_audio_sfe_level(struct dp_catalog *dp_catalog)
1076 {
1077     struct dp_catalog_private *catalog;
1078     u32 mainlink_levels, safe_to_exit_level;
1079 
1080     if (!dp_catalog)
1081         return;
1082 
1083     catalog = container_of(dp_catalog,
1084         struct dp_catalog_private, dp_catalog);
1085 
1086     safe_to_exit_level = dp_catalog->audio_data;
1087     mainlink_levels = dp_read_link(catalog, REG_DP_MAINLINK_LEVELS);
1088     mainlink_levels &= 0xFE0;
1089     mainlink_levels |= safe_to_exit_level;
1090 
1091     drm_dbg_dp(catalog->drm_dev,
1092             "mainlink_level = 0x%x, safe_to_exit_level = 0x%x\n",
1093              mainlink_levels, safe_to_exit_level);
1094 
1095     dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels);
1096 }
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