disp/mdp5/mdp5_kms.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2013 Red Hat
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  */
0006
0007 #ifndef __MDP5_KMS_H__
0008 #define __MDP5_KMS_H__
0009
0010 #include "msm_drv.h"
0011 #include "msm_kms.h"
0012 #include "disp/mdp_kms.h"
0013 #include "mdp5_cfg.h"   /* must be included before mdp5.xml.h */
0014 #include "mdp5.xml.h"
0015 #include "mdp5_pipe.h"
0016 #include "mdp5_mixer.h"
0017 #include "mdp5_ctl.h"
0018 #include "mdp5_smp.h"
0019
0020 struct mdp5_kms {
0021     struct mdp_kms base;
0022
0023     struct drm_device *dev;
0024
0025     struct platform_device *pdev;
0026
0027     unsigned num_hwpipes;
0028     struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
0029
0030     unsigned num_hwmixers;
0031     struct mdp5_hw_mixer *hwmixers[8];
0032
0033     unsigned num_intfs;
0034     struct mdp5_interface *intfs[5];
0035
0036     struct mdp5_cfg_handler *cfg;
0037     uint32_t caps;  /* MDP capabilities (MDP_CAP_XXX bits) */
0038
0039     /*
0040      * Global private object state, Do not access directly, use
0041      * mdp5_global_get_state()
0042      */
0043     struct drm_modeset_lock glob_state_lock;
0044     struct drm_private_obj glob_state;
0045
0046     struct mdp5_smp *smp;
0047     struct mdp5_ctl_manager *ctlm;
0048
0049     /* io/register spaces: */
0050     void __iomem *mmio;
0051
0052     struct clk *axi_clk;
0053     struct clk *ahb_clk;
0054     struct clk *core_clk;
0055     struct clk *lut_clk;
0056     struct clk *tbu_clk;
0057     struct clk *tbu_rt_clk;
0058     struct clk *vsync_clk;
0059
0060     /*
0061      * lock to protect access to global resources: ie., following register:
0062      *  - REG_MDP5_DISP_INTF_SEL
0063      */
0064     spinlock_t resource_lock;
0065
0066     bool rpm_enabled;
0067
0068     struct mdp_irq error_handler;
0069
0070     int enable_count;
0071 };
0072 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
0073
0074 /* Global private object state for tracking resources that are shared across
0075  * multiple kms objects (planes/crtcs/etc).
0076  */
0077 #define to_mdp5_global_state(x) container_of(x, struct mdp5_global_state, base)
0078 struct mdp5_global_state {
0079     struct drm_private_state base;
0080
0081     struct drm_atomic_state *state;
0082     struct mdp5_kms *mdp5_kms;
0083
0084     struct mdp5_hw_pipe_state hwpipe;
0085     struct mdp5_hw_mixer_state hwmixer;
0086     struct mdp5_smp_state smp;
0087 };
0088
0089 struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms);
0090 struct mdp5_global_state *__must_check mdp5_get_global_state(struct drm_atomic_state *s);
0091
0092 /* Atomic plane state.  Subclasses the base drm_plane_state in order to
0093  * track assigned hwpipe and hw specific state.
0094  */
0095 struct mdp5_plane_state {
0096     struct drm_plane_state base;
0097
0098     struct mdp5_hw_pipe *hwpipe;
0099     struct mdp5_hw_pipe *r_hwpipe;  /* right hwpipe */
0100
0101     /* assigned by crtc blender */
0102     enum mdp_mixer_stage_id stage;
0103
0104     /* whether attached CRTC needs pixel data explicitly flushed to
0105      * display (ex. DSI command mode display)
0106      */
0107     bool needs_dirtyfb;
0108 };
0109 #define to_mdp5_plane_state(x) \
0110         container_of(x, struct mdp5_plane_state, base)
0111
0112 struct mdp5_pipeline {
0113     struct mdp5_interface *intf;
0114     struct mdp5_hw_mixer *mixer;
0115     struct mdp5_hw_mixer *r_mixer;  /* right mixer */
0116 };
0117
0118 struct mdp5_crtc_state {
0119     struct drm_crtc_state base;
0120
0121     struct mdp5_ctl *ctl;
0122     struct mdp5_pipeline pipeline;
0123
0124     /* these are derivatives of intf/mixer state in mdp5_pipeline */
0125     u32 vblank_irqmask;
0126     u32 err_irqmask;
0127     u32 pp_done_irqmask;
0128
0129     bool cmd_mode;
0130
0131     /* should we not write CTL[n].START register on flush?  If the
0132      * encoder has changed this is set to true, since encoder->enable()
0133      * is called after crtc state is committed, but we only want to
0134      * write the CTL[n].START register once.  This lets us defer
0135      * writing CTL[n].START until encoder->enable()
0136      */
0137     bool defer_start;
0138 };
0139 #define to_mdp5_crtc_state(x) \
0140         container_of(x, struct mdp5_crtc_state, base)
0141
0142 enum mdp5_intf_mode {
0143     MDP5_INTF_MODE_NONE = 0,
0144
0145     /* Modes used for DSI interface (INTF_DSI type): */
0146     MDP5_INTF_DSI_MODE_VIDEO,
0147     MDP5_INTF_DSI_MODE_COMMAND,
0148
0149     /* Modes used for WB interface (INTF_WB type):  */
0150     MDP5_INTF_WB_MODE_BLOCK,
0151     MDP5_INTF_WB_MODE_LINE,
0152 };
0153
0154 struct mdp5_interface {
0155     int idx;
0156     int num; /* display interface number */
0157     enum mdp5_intf_type type;
0158     enum mdp5_intf_mode mode;
0159 };
0160
0161 struct mdp5_encoder {
0162     struct drm_encoder base;
0163     spinlock_t intf_lock;   /* protect REG_MDP5_INTF_* registers */
0164     bool enabled;
0165     uint32_t bsc;
0166
0167     struct mdp5_interface *intf;
0168     struct mdp5_ctl *ctl;
0169 };
0170 #define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
0171
0172 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
0173 {
0174     WARN_ON(mdp5_kms->enable_count <= 0);
0175     msm_writel(data, mdp5_kms->mmio + reg);
0176 }
0177
0178 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
0179 {
0180     WARN_ON(mdp5_kms->enable_count <= 0);
0181     return msm_readl(mdp5_kms->mmio + reg);
0182 }
0183
0184 static inline const char *stage2name(enum mdp_mixer_stage_id stage)
0185 {
0186     static const char *names[] = {
0187 #define NAME(n) [n] = #n
0188         NAME(STAGE_UNUSED), NAME(STAGE_BASE),
0189         NAME(STAGE0), NAME(STAGE1), NAME(STAGE2),
0190         NAME(STAGE3), NAME(STAGE4), NAME(STAGE6),
0191 #undef NAME
0192     };
0193     return names[stage];
0194 }
0195
0196 static inline const char *pipe2name(enum mdp5_pipe pipe)
0197 {
0198     static const char *names[] = {
0199 #define NAME(n) [SSPP_ ## n] = #n
0200         NAME(VIG0), NAME(VIG1), NAME(VIG2),
0201         NAME(RGB0), NAME(RGB1), NAME(RGB2),
0202         NAME(DMA0), NAME(DMA1),
0203         NAME(VIG3), NAME(RGB3),
0204         NAME(CURSOR0), NAME(CURSOR1),
0205 #undef NAME
0206     };
0207     return names[pipe];
0208 }
0209
0210 static inline int pipe2nclients(enum mdp5_pipe pipe)
0211 {
0212     switch (pipe) {
0213     case SSPP_RGB0:
0214     case SSPP_RGB1:
0215     case SSPP_RGB2:
0216     case SSPP_RGB3:
0217         return 1;
0218     default:
0219         return 3;
0220     }
0221 }
0222
0223 static inline uint32_t intf2err(int intf_num)
0224 {
0225     switch (intf_num) {
0226     case 0:  return MDP5_IRQ_INTF0_UNDER_RUN;
0227     case 1:  return MDP5_IRQ_INTF1_UNDER_RUN;
0228     case 2:  return MDP5_IRQ_INTF2_UNDER_RUN;
0229     case 3:  return MDP5_IRQ_INTF3_UNDER_RUN;
0230     default: return 0;
0231     }
0232 }
0233
0234 static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer,
0235                    struct mdp5_interface *intf)
0236 {
0237     /*
0238      * In case of DSI Command Mode, the Ping Pong's read pointer IRQ
0239      * acts as a Vblank signal. The Ping Pong buffer used is bound to
0240      * layer mixer.
0241      */
0242
0243     if ((intf->type == INTF_DSI) &&
0244             (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
0245         return MDP5_IRQ_PING_PONG_0_RD_PTR << mixer->pp;
0246
0247     if (intf->type == INTF_WB)
0248         return MDP5_IRQ_WB_2_DONE;
0249
0250     switch (intf->num) {
0251     case 0:  return MDP5_IRQ_INTF0_VSYNC;
0252     case 1:  return MDP5_IRQ_INTF1_VSYNC;
0253     case 2:  return MDP5_IRQ_INTF2_VSYNC;
0254     case 3:  return MDP5_IRQ_INTF3_VSYNC;
0255     default: return 0;
0256     }
0257 }
0258
0259 static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer)
0260 {
0261     return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp;
0262 }
0263
0264 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
0265         uint32_t old_irqmask);
0266 void mdp5_irq_preinstall(struct msm_kms *kms);
0267 int mdp5_irq_postinstall(struct msm_kms *kms);
0268 void mdp5_irq_uninstall(struct msm_kms *kms);
0269 irqreturn_t mdp5_irq(struct msm_kms *kms);
0270 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
0271 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
0272 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
0273 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
0274
0275 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
0276 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
0277 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane);
0278 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
0279                   enum drm_plane_type type);
0280
0281 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
0282 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
0283
0284 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc);
0285 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc);
0286 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc);
0287 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
0288 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
0289                 struct drm_plane *plane,
0290                 struct drm_plane *cursor_plane, int id);
0291
0292 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
0293         struct mdp5_interface *intf, struct mdp5_ctl *ctl);
0294 int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
0295                        struct drm_encoder *slave_encoder);
0296 void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode);
0297 int mdp5_encoder_get_linecount(struct drm_encoder *encoder);
0298 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);
0299
0300 #ifdef CONFIG_DRM_MSM_DSI
0301 void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
0302                    struct drm_display_mode *mode,
0303                    struct drm_display_mode *adjusted_mode);
0304 void mdp5_cmd_encoder_disable(struct drm_encoder *encoder);
0305 void mdp5_cmd_encoder_enable(struct drm_encoder *encoder);
0306 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
0307                        struct drm_encoder *slave_encoder);
0308 #else
0309 static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
0310                          struct drm_display_mode *mode,
0311                          struct drm_display_mode *adjusted_mode)
0312 {
0313 }
0314 static inline void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
0315 {
0316 }
0317 static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
0318 {
0319 }
0320 static inline int mdp5_cmd_encoder_set_split_display(
0321     struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
0322 {
0323     return -EINVAL;
0324 }
0325 #endif
0326
0327 #endif /* __MDP5_KMS_H__ */