disp/mdp5/mdp5_cmd_encoder.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <drm/drm_crtc.h>
0007 #include <drm/drm_probe_helper.h>
0008
0009 #include "mdp5_kms.h"
0010
0011 #ifdef CONFIG_DRM_MSM_DSI
0012
0013 static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
0014 {
0015     struct msm_drm_private *priv = encoder->dev->dev_private;
0016     return to_mdp5_kms(to_mdp_kms(priv->kms));
0017 }
0018
0019 #define VSYNC_CLK_RATE 19200000
0020 static int pingpong_tearcheck_setup(struct drm_encoder *encoder,
0021                     struct drm_display_mode *mode)
0022 {
0023     struct mdp5_kms *mdp5_kms = get_kms(encoder);
0024     struct device *dev = encoder->dev->dev;
0025     u32 total_lines, vclks_line, cfg;
0026     long vsync_clk_speed;
0027     struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
0028     int pp_id = mixer->pp;
0029
0030     if (IS_ERR_OR_NULL(mdp5_kms->vsync_clk)) {
0031         DRM_DEV_ERROR(dev, "vsync_clk is not initialized\n");
0032         return -EINVAL;
0033     }
0034
0035     total_lines = mode->vtotal * drm_mode_vrefresh(mode);
0036     if (!total_lines) {
0037         DRM_DEV_ERROR(dev, "%s: vtotal(%d) or vrefresh(%d) is 0\n",
0038                   __func__, mode->vtotal, drm_mode_vrefresh(mode));
0039         return -EINVAL;
0040     }
0041
0042     vsync_clk_speed = clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE);
0043     if (vsync_clk_speed <= 0) {
0044         DRM_DEV_ERROR(dev, "vsync_clk round rate failed %ld\n",
0045                             vsync_clk_speed);
0046         return -EINVAL;
0047     }
0048     vclks_line = vsync_clk_speed / total_lines;
0049
0050     cfg = MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN
0051         | MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN;
0052     cfg |= MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(vclks_line);
0053
0054     /*
0055      * Tearcheck emits a blanking signal every vclks_line * vtotal * 2 ticks on
0056      * the vsync_clk equating to roughly half the desired panel refresh rate.
0057      * This is only necessary as stability fallback if interrupts from the
0058      * panel arrive too late or not at all, but is currently used by default
0059      * because these panel interrupts are not wired up yet.
0060      */
0061     mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg);
0062     mdp5_write(mdp5_kms,
0063         REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), (2 * mode->vtotal));
0064
0065     mdp5_write(mdp5_kms,
0066         REG_MDP5_PP_VSYNC_INIT_VAL(pp_id), mode->vdisplay);
0067     mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1);
0068     mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay);
0069     mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id),
0070             MDP5_PP_SYNC_THRESH_START(4) |
0071             MDP5_PP_SYNC_THRESH_CONTINUE(4));
0072     mdp5_write(mdp5_kms, REG_MDP5_PP_AUTOREFRESH_CONFIG(pp_id), 0x0);
0073
0074     return 0;
0075 }
0076
0077 static int pingpong_tearcheck_enable(struct drm_encoder *encoder)
0078 {
0079     struct mdp5_kms *mdp5_kms = get_kms(encoder);
0080     struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
0081     int pp_id = mixer->pp;
0082     int ret;
0083
0084     ret = clk_set_rate(mdp5_kms->vsync_clk,
0085         clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE));
0086     if (ret) {
0087         DRM_DEV_ERROR(encoder->dev->dev,
0088             "vsync_clk clk_set_rate failed, %d\n", ret);
0089         return ret;
0090     }
0091     ret = clk_prepare_enable(mdp5_kms->vsync_clk);
0092     if (ret) {
0093         DRM_DEV_ERROR(encoder->dev->dev,
0094             "vsync_clk clk_prepare_enable failed, %d\n", ret);
0095         return ret;
0096     }
0097
0098     mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 1);
0099
0100     return 0;
0101 }
0102
0103 static void pingpong_tearcheck_disable(struct drm_encoder *encoder)
0104 {
0105     struct mdp5_kms *mdp5_kms = get_kms(encoder);
0106     struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
0107     int pp_id = mixer->pp;
0108
0109     mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 0);
0110     clk_disable_unprepare(mdp5_kms->vsync_clk);
0111 }
0112
0113 void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
0114                    struct drm_display_mode *mode,
0115                    struct drm_display_mode *adjusted_mode)
0116 {
0117     mode = adjusted_mode;
0118
0119     DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
0120     pingpong_tearcheck_setup(encoder, mode);
0121     mdp5_crtc_set_pipeline(encoder->crtc);
0122 }
0123
0124 void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
0125 {
0126     struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
0127     struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
0128     struct mdp5_interface *intf = mdp5_cmd_enc->intf;
0129     struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
0130
0131     if (WARN_ON(!mdp5_cmd_enc->enabled))
0132         return;
0133
0134     pingpong_tearcheck_disable(encoder);
0135
0136     mdp5_ctl_set_encoder_state(ctl, pipeline, false);
0137     mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
0138
0139     mdp5_cmd_enc->enabled = false;
0140 }
0141
0142 void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
0143 {
0144     struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
0145     struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
0146     struct mdp5_interface *intf = mdp5_cmd_enc->intf;
0147     struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
0148
0149     if (WARN_ON(mdp5_cmd_enc->enabled))
0150         return;
0151
0152     if (pingpong_tearcheck_enable(encoder))
0153         return;
0154
0155     mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
0156
0157     mdp5_ctl_set_encoder_state(ctl, pipeline, true);
0158
0159     mdp5_cmd_enc->enabled = true;
0160 }
0161
0162 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
0163                        struct drm_encoder *slave_encoder)
0164 {
0165     struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
0166     struct mdp5_kms *mdp5_kms;
0167     struct device *dev;
0168     int intf_num;
0169     u32 data = 0;
0170
0171     if (!encoder || !slave_encoder)
0172         return -EINVAL;
0173
0174     mdp5_kms = get_kms(encoder);
0175     intf_num = mdp5_cmd_enc->intf->num;
0176
0177     /* Switch slave encoder's trigger MUX, to use the master's
0178      * start signal for the slave encoder
0179      */
0180     if (intf_num == 1)
0181         data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX;
0182     else if (intf_num == 2)
0183         data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX;
0184     else
0185         return -EINVAL;
0186
0187     /* Smart Panel, Sync mode */
0188     data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL;
0189
0190     dev = &mdp5_kms->pdev->dev;
0191
0192     /* Make sure clocks are on when connectors calling this function. */
0193     pm_runtime_get_sync(dev);
0194     mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data);
0195
0196     mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER,
0197            MDP5_SPLIT_DPL_LOWER_SMART_PANEL);
0198     mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
0199     pm_runtime_put_sync(dev);
0200
0201     return 0;
0202 }
0203 #endif /* CONFIG_DRM_MSM_DSI */