disp/mdp5/mdp5_cfg.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef __MDP5_CFG_H__
0007 #define __MDP5_CFG_H__
0008
0009 #include "msm_drv.h"
0010
0011 /*
0012  * mdp5_cfg
0013  *
0014  * This module configures the dynamic offsets used by mdp5.xml.h
0015  * (initialized in mdp5_cfg.c)
0016  */
0017 extern const struct mdp5_cfg_hw *mdp5_cfg;
0018
0019 #define MAX_CTL         8
0020 #define MAX_BASES       8
0021 #define MAX_SMP_BLOCKS      44
0022 #define MAX_CLIENTS     32
0023
0024 typedef DECLARE_BITMAP(mdp5_smp_state_t, MAX_SMP_BLOCKS);
0025
0026 #define MDP5_SUB_BLOCK_DEFINITION \
0027     unsigned int count; \
0028     uint32_t base[MAX_BASES]
0029
0030 struct mdp5_sub_block {
0031     MDP5_SUB_BLOCK_DEFINITION;
0032 };
0033
0034 struct mdp5_lm_instance {
0035     int id;
0036     int pp;
0037     int dspp;
0038     uint32_t caps;
0039 };
0040
0041 struct mdp5_lm_block {
0042     MDP5_SUB_BLOCK_DEFINITION;
0043     struct mdp5_lm_instance instances[MAX_BASES];
0044     uint32_t nb_stages;     /* number of stages per blender */
0045     uint32_t max_width;     /* Maximum output resolution */
0046     uint32_t max_height;
0047 };
0048
0049 struct mdp5_pipe_block {
0050     MDP5_SUB_BLOCK_DEFINITION;
0051     uint32_t caps;          /* pipe capabilities */
0052 };
0053
0054 struct mdp5_ctl_block {
0055     MDP5_SUB_BLOCK_DEFINITION;
0056     uint32_t flush_hw_mask;     /* FLUSH register's hardware mask */
0057 };
0058
0059 struct mdp5_smp_block {
0060     int mmb_count;          /* number of SMP MMBs */
0061     int mmb_size;           /* MMB: size in bytes */
0062     uint32_t clients[MAX_CLIENTS];  /* SMP port allocation /pipe */
0063     mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
0064     uint8_t reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
0065 };
0066
0067 struct mdp5_mdp_block {
0068     MDP5_SUB_BLOCK_DEFINITION;
0069     uint32_t caps;          /* MDP capabilities: MDP_CAP_xxx bits */
0070 };
0071
0072 #define MDP5_INTF_NUM_MAX   5
0073
0074 struct mdp5_intf_block {
0075     uint32_t base[MAX_BASES];
0076     u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
0077 };
0078
0079 struct mdp5_perf_block {
0080     u32 ab_inefficiency;
0081     u32 ib_inefficiency;
0082     u32 clk_inefficiency;
0083 };
0084
0085 struct mdp5_cfg_hw {
0086     char  *name;
0087
0088     struct mdp5_mdp_block mdp;
0089     struct mdp5_smp_block smp;
0090     struct mdp5_ctl_block ctl;
0091     struct mdp5_pipe_block pipe_vig;
0092     struct mdp5_pipe_block pipe_rgb;
0093     struct mdp5_pipe_block pipe_dma;
0094     struct mdp5_pipe_block pipe_cursor;
0095     struct mdp5_lm_block  lm;
0096     struct mdp5_sub_block dspp;
0097     struct mdp5_sub_block ad;
0098     struct mdp5_sub_block pp;
0099     struct mdp5_sub_block dsc;
0100     struct mdp5_sub_block cdm;
0101     struct mdp5_intf_block intf;
0102     struct mdp5_perf_block perf;
0103
0104     uint32_t max_clk;
0105 };
0106
0107 struct mdp5_cfg {
0108     const struct mdp5_cfg_hw *hw;
0109 };
0110
0111 struct mdp5_kms;
0112 struct mdp5_cfg_handler;
0113
0114 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_hnd);
0115 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_hnd);
0116 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_hnd);
0117
0118 #define mdp5_cfg_intf_is_virtual(intf_type) ({  \
0119     typeof(intf_type) __val = (intf_type);  \
0120     (__val) >= INTF_VIRTUAL ? true : false; })
0121
0122 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
0123         uint32_t major, uint32_t minor);
0124 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_hnd);
0125
0126 #endif /* __MDP5_CFG_H__ */