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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include "mdp5_kms.h"
0007 #include "mdp5_cfg.h"
0008 
0009 struct mdp5_cfg_handler {
0010     int revision;
0011     struct mdp5_cfg config;
0012 };
0013 
0014 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
0015 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
0016 
0017 static const struct mdp5_cfg_hw msm8x74v1_config = {
0018     .name = "msm8x74v1",
0019     .mdp = {
0020         .count = 1,
0021         .caps = MDP_CAP_SMP |
0022             0,
0023     },
0024     .smp = {
0025         .mmb_count = 22,
0026         .mmb_size = 4096,
0027         .clients = {
0028             [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
0029             [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
0030             [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
0031         },
0032     },
0033     .ctl = {
0034         .count = 5,
0035         .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
0036         .flush_hw_mask = 0x0003ffff,
0037     },
0038     .pipe_vig = {
0039         .count = 3,
0040         .base = { 0x01100, 0x01500, 0x01900 },
0041         .caps = MDP_PIPE_CAP_HFLIP |
0042             MDP_PIPE_CAP_VFLIP |
0043             MDP_PIPE_CAP_SCALE |
0044             MDP_PIPE_CAP_CSC   |
0045             0,
0046     },
0047     .pipe_rgb = {
0048         .count = 3,
0049         .base = { 0x01d00, 0x02100, 0x02500 },
0050         .caps = MDP_PIPE_CAP_HFLIP |
0051             MDP_PIPE_CAP_VFLIP |
0052             MDP_PIPE_CAP_SCALE |
0053             0,
0054     },
0055     .pipe_dma = {
0056         .count = 2,
0057         .base = { 0x02900, 0x02d00 },
0058         .caps = MDP_PIPE_CAP_HFLIP |
0059             MDP_PIPE_CAP_VFLIP |
0060             0,
0061     },
0062     .lm = {
0063         .count = 5,
0064         .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
0065         .instances = {
0066                 { .id = 0, .pp = 0, .dspp = 0,
0067                   .caps = MDP_LM_CAP_DISPLAY, },
0068                 { .id = 1, .pp = 1, .dspp = 1,
0069                   .caps = MDP_LM_CAP_DISPLAY, },
0070                 { .id = 2, .pp = 2, .dspp = 2,
0071                   .caps = MDP_LM_CAP_DISPLAY, },
0072                 { .id = 3, .pp = -1, .dspp = -1,
0073                   .caps = MDP_LM_CAP_WB },
0074                 { .id = 4, .pp = -1, .dspp = -1,
0075                   .caps = MDP_LM_CAP_WB },
0076                  },
0077         .nb_stages = 5,
0078         .max_width = 2048,
0079         .max_height = 0xFFFF,
0080     },
0081     .dspp = {
0082         .count = 3,
0083         .base = { 0x04500, 0x04900, 0x04d00 },
0084     },
0085     .pp = {
0086         .count = 3,
0087         .base = { 0x21a00, 0x21b00, 0x21c00 },
0088     },
0089     .intf = {
0090         .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
0091         .connect = {
0092             [0] = INTF_eDP,
0093             [1] = INTF_DSI,
0094             [2] = INTF_DSI,
0095             [3] = INTF_HDMI,
0096         },
0097     },
0098     .perf = {
0099         .ab_inefficiency = 200,
0100         .ib_inefficiency = 120,
0101         .clk_inefficiency = 125
0102     },
0103     .max_clk = 200000000,
0104 };
0105 
0106 static const struct mdp5_cfg_hw msm8x74v2_config = {
0107     .name = "msm8x74",
0108     .mdp = {
0109         .count = 1,
0110         .caps = MDP_CAP_SMP |
0111             0,
0112     },
0113     .smp = {
0114         .mmb_count = 22,
0115         .mmb_size = 4096,
0116         .clients = {
0117             [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
0118             [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
0119             [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
0120         },
0121     },
0122     .ctl = {
0123         .count = 5,
0124         .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
0125         .flush_hw_mask = 0x0003ffff,
0126     },
0127     .pipe_vig = {
0128         .count = 3,
0129         .base = { 0x01100, 0x01500, 0x01900 },
0130         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0131                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
0132                 MDP_PIPE_CAP_DECIMATION,
0133     },
0134     .pipe_rgb = {
0135         .count = 3,
0136         .base = { 0x01d00, 0x02100, 0x02500 },
0137         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0138                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
0139     },
0140     .pipe_dma = {
0141         .count = 2,
0142         .base = { 0x02900, 0x02d00 },
0143         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
0144     },
0145     .lm = {
0146         .count = 5,
0147         .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
0148         .instances = {
0149                 { .id = 0, .pp = 0, .dspp = 0,
0150                   .caps = MDP_LM_CAP_DISPLAY, },
0151                 { .id = 1, .pp = 1, .dspp = 1,
0152                   .caps = MDP_LM_CAP_DISPLAY, },
0153                 { .id = 2, .pp = 2, .dspp = 2,
0154                   .caps = MDP_LM_CAP_DISPLAY, },
0155                 { .id = 3, .pp = -1, .dspp = -1,
0156                   .caps = MDP_LM_CAP_WB, },
0157                 { .id = 4, .pp = -1, .dspp = -1,
0158                   .caps = MDP_LM_CAP_WB, },
0159                  },
0160         .nb_stages = 5,
0161         .max_width = 2048,
0162         .max_height = 0xFFFF,
0163     },
0164     .dspp = {
0165         .count = 3,
0166         .base = { 0x04500, 0x04900, 0x04d00 },
0167     },
0168     .ad = {
0169         .count = 2,
0170         .base = { 0x13000, 0x13200 },
0171     },
0172     .pp = {
0173         .count = 3,
0174         .base = { 0x12c00, 0x12d00, 0x12e00 },
0175     },
0176     .intf = {
0177         .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
0178         .connect = {
0179             [0] = INTF_eDP,
0180             [1] = INTF_DSI,
0181             [2] = INTF_DSI,
0182             [3] = INTF_HDMI,
0183         },
0184     },
0185     .perf = {
0186         .ab_inefficiency = 200,
0187         .ib_inefficiency = 120,
0188         .clk_inefficiency = 125
0189     },
0190     .max_clk = 320000000,
0191 };
0192 
0193 static const struct mdp5_cfg_hw apq8084_config = {
0194     .name = "apq8084",
0195     .mdp = {
0196         .count = 1,
0197         .caps = MDP_CAP_SMP |
0198             MDP_CAP_SRC_SPLIT |
0199             0,
0200     },
0201     .smp = {
0202         .mmb_count = 44,
0203         .mmb_size = 8192,
0204         .clients = {
0205             [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
0206             [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
0207             [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
0208             [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
0209             [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
0210         },
0211         .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
0212         .reserved = {
0213             /* Two SMP blocks are statically tied to RGB pipes: */
0214             [16] = 2, [17] = 2, [18] = 2, [22] = 2,
0215         },
0216     },
0217     .ctl = {
0218         .count = 5,
0219         .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
0220         .flush_hw_mask = 0x003fffff,
0221     },
0222     .pipe_vig = {
0223         .count = 4,
0224         .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
0225         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0226                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
0227                 MDP_PIPE_CAP_DECIMATION,
0228     },
0229     .pipe_rgb = {
0230         .count = 4,
0231         .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
0232         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0233                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
0234     },
0235     .pipe_dma = {
0236         .count = 2,
0237         .base = { 0x03100, 0x03500 },
0238         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
0239     },
0240     .lm = {
0241         .count = 6,
0242         .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
0243         .instances = {
0244                 { .id = 0, .pp = 0, .dspp = 0,
0245                   .caps = MDP_LM_CAP_DISPLAY |
0246                       MDP_LM_CAP_PAIR, },
0247                 { .id = 1, .pp = 1, .dspp = 1,
0248                   .caps = MDP_LM_CAP_DISPLAY, },
0249                 { .id = 2, .pp = 2, .dspp = 2,
0250                   .caps = MDP_LM_CAP_DISPLAY |
0251                       MDP_LM_CAP_PAIR, },
0252                 { .id = 3, .pp = -1, .dspp = -1,
0253                   .caps = MDP_LM_CAP_WB, },
0254                 { .id = 4, .pp = -1, .dspp = -1,
0255                   .caps = MDP_LM_CAP_WB, },
0256                 { .id = 5, .pp = 3, .dspp = 3,
0257                   .caps = MDP_LM_CAP_DISPLAY, },
0258                  },
0259         .nb_stages = 5,
0260         .max_width = 2048,
0261         .max_height = 0xFFFF,
0262     },
0263     .dspp = {
0264         .count = 4,
0265         .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
0266 
0267     },
0268     .ad = {
0269         .count = 3,
0270         .base = { 0x13400, 0x13600, 0x13800 },
0271     },
0272     .pp = {
0273         .count = 4,
0274         .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
0275     },
0276     .intf = {
0277         .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
0278         .connect = {
0279             [0] = INTF_eDP,
0280             [1] = INTF_DSI,
0281             [2] = INTF_DSI,
0282             [3] = INTF_HDMI,
0283         },
0284     },
0285     .perf = {
0286         .ab_inefficiency = 200,
0287         .ib_inefficiency = 120,
0288         .clk_inefficiency = 105
0289     },
0290     .max_clk = 320000000,
0291 };
0292 
0293 static const struct mdp5_cfg_hw msm8x16_config = {
0294     .name = "msm8x16",
0295     .mdp = {
0296         .count = 1,
0297         .base = { 0x0 },
0298         .caps = MDP_CAP_SMP |
0299             0,
0300     },
0301     .smp = {
0302         .mmb_count = 8,
0303         .mmb_size = 8192,
0304         .clients = {
0305             [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
0306             [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
0307         },
0308     },
0309     .ctl = {
0310         .count = 5,
0311         .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
0312         .flush_hw_mask = 0x4003ffff,
0313     },
0314     .pipe_vig = {
0315         .count = 1,
0316         .base = { 0x04000 },
0317         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0318                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
0319                 MDP_PIPE_CAP_DECIMATION,
0320     },
0321     .pipe_rgb = {
0322         .count = 2,
0323         .base = { 0x14000, 0x16000 },
0324         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0325                 MDP_PIPE_CAP_DECIMATION,
0326     },
0327     .pipe_dma = {
0328         .count = 1,
0329         .base = { 0x24000 },
0330         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
0331     },
0332     .lm = {
0333         .count = 2, /* LM0 and LM3 */
0334         .base = { 0x44000, 0x47000 },
0335         .instances = {
0336                 { .id = 0, .pp = 0, .dspp = 0,
0337                   .caps = MDP_LM_CAP_DISPLAY, },
0338                 { .id = 3, .pp = -1, .dspp = -1,
0339                   .caps = MDP_LM_CAP_WB },
0340                  },
0341         .nb_stages = 8,
0342         .max_width = 2048,
0343         .max_height = 0xFFFF,
0344     },
0345     .dspp = {
0346         .count = 1,
0347         .base = { 0x54000 },
0348 
0349     },
0350     .intf = {
0351         .base = { 0x00000, 0x6a800 },
0352         .connect = {
0353             [0] = INTF_DISABLED,
0354             [1] = INTF_DSI,
0355         },
0356     },
0357     .perf = {
0358         .ab_inefficiency = 100,
0359         .ib_inefficiency = 200,
0360         .clk_inefficiency = 105
0361     },
0362     .max_clk = 320000000,
0363 };
0364 
0365 static const struct mdp5_cfg_hw msm8x36_config = {
0366     .name = "msm8x36",
0367     .mdp = {
0368         .count = 1,
0369         .base = { 0x0 },
0370         .caps = MDP_CAP_SMP |
0371             0,
0372     },
0373     .smp = {
0374         .mmb_count = 8,
0375         .mmb_size = 10240,
0376         .clients = {
0377             [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
0378             [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
0379         },
0380     },
0381     .ctl = {
0382         .count = 3,
0383         .base = { 0x01000, 0x01200, 0x01400 },
0384         .flush_hw_mask = 0x4003ffff,
0385     },
0386     .pipe_vig = {
0387         .count = 1,
0388         .base = { 0x04000 },
0389         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0390                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
0391                 MDP_PIPE_CAP_DECIMATION,
0392     },
0393     .pipe_rgb = {
0394         .count = 2,
0395         .base = { 0x14000, 0x16000 },
0396         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0397                 MDP_PIPE_CAP_DECIMATION,
0398     },
0399     .pipe_dma = {
0400         .count = 1,
0401         .base = { 0x24000 },
0402         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
0403     },
0404     .lm = {
0405         .count = 2,
0406         .base = { 0x44000, 0x47000 },
0407         .instances = {
0408                 { .id = 0, .pp = 0, .dspp = 0,
0409                   .caps = MDP_LM_CAP_DISPLAY, },
0410                 { .id = 1, .pp = -1, .dspp = -1,
0411                   .caps = MDP_LM_CAP_WB, },
0412                 },
0413         .nb_stages = 8,
0414         .max_width = 2560,
0415         .max_height = 0xFFFF,
0416     },
0417     .pp = {
0418         .count = 1,
0419         .base = { 0x70000 },
0420     },
0421     .ad = {
0422         .count = 1,
0423         .base = { 0x78000 },
0424     },
0425     .dspp = {
0426         .count = 1,
0427         .base = { 0x54000 },
0428     },
0429     .intf = {
0430         .base = { 0x00000, 0x6a800, 0x6b000 },
0431         .connect = {
0432             [0] = INTF_DISABLED,
0433             [1] = INTF_DSI,
0434             [2] = INTF_DSI,
0435         },
0436     },
0437     .perf = {
0438         .ab_inefficiency = 100,
0439         .ib_inefficiency = 200,
0440         .clk_inefficiency = 105
0441     },
0442     .max_clk = 366670000,
0443 };
0444 
0445 static const struct mdp5_cfg_hw msm8x94_config = {
0446     .name = "msm8x94",
0447     .mdp = {
0448         .count = 1,
0449         .caps = MDP_CAP_SMP |
0450             MDP_CAP_SRC_SPLIT |
0451             0,
0452     },
0453     .smp = {
0454         .mmb_count = 44,
0455         .mmb_size = 8192,
0456         .clients = {
0457             [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
0458             [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
0459             [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
0460             [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
0461             [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
0462         },
0463         .reserved_state[0] = GENMASK(23, 0),    /* first 24 MMBs */
0464         .reserved = {
0465              [1] = 1,  [4] = 1,  [7] = 1, [19] = 1,
0466             [16] = 5, [17] = 5, [18] = 5, [22] = 5,
0467         },
0468     },
0469     .ctl = {
0470         .count = 5,
0471         .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
0472         .flush_hw_mask = 0xf0ffffff,
0473     },
0474     .pipe_vig = {
0475         .count = 4,
0476         .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
0477         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0478                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
0479                 MDP_PIPE_CAP_DECIMATION,
0480     },
0481     .pipe_rgb = {
0482         .count = 4,
0483         .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
0484         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
0485                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
0486     },
0487     .pipe_dma = {
0488         .count = 2,
0489         .base = { 0x24000, 0x26000 },
0490         .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
0491     },
0492     .lm = {
0493         .count = 6,
0494         .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
0495         .instances = {
0496                 { .id = 0, .pp = 0, .dspp = 0,
0497                   .caps = MDP_LM_CAP_DISPLAY |
0498                       MDP_LM_CAP_PAIR, },
0499                 { .id = 1, .pp = 1, .dspp = 1,
0500                   .caps = MDP_LM_CAP_DISPLAY, },
0501                 { .id = 2, .pp = 2, .dspp = 2,
0502                   .caps = MDP_LM_CAP_DISPLAY |
0503                       MDP_LM_CAP_PAIR, },
0504                 { .id = 3, .pp = -1, .dspp = -1,
0505                   .caps = MDP_LM_CAP_WB, },
0506                 { .id = 4, .pp = -1, .dspp = -1,
0507                   .caps = MDP_LM_CAP_WB, },
0508                 { .id = 5, .pp = 3, .dspp = 3,
0509                   .caps = MDP_LM_CAP_DISPLAY, },
0510                  },
0511         .nb_stages = 8,
0512         .max_width = 2048,
0513         .max_height = 0xFFFF,
0514     },
0515     .dspp = {
0516         .count = 4,
0517         .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
0518 
0519     },
0520     .ad = {
0521         .count = 3,
0522         .base = { 0x78000, 0x78800, 0x79000 },
0523     },
0524     .pp = {
0525         .count = 4,
0526         .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
0527     },
0528     .intf = {
0529         .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
0530         .connect = {
0531             [0] = INTF_DISABLED,
0532             [1] = INTF_DSI,
0533             [2] = INTF_DSI,
0534             [3] = INTF_HDMI,
0535         },
0536     },
0537     .perf = {
0538         .ab_inefficiency = 100,
0539         .ib_inefficiency = 100,
0540         .clk_inefficiency = 105
0541     },
0542     .max_clk = 400000000,
0543 };
0544 
0545 static const struct mdp5_cfg_hw msm8x96_config = {
0546     .name = "msm8x96",
0547     .mdp = {
0548         .count = 1,
0549         .caps = MDP_CAP_DSC |
0550             MDP_CAP_CDM |
0551             MDP_CAP_SRC_SPLIT |
0552             0,
0553     },
0554     .ctl = {
0555         .count = 5,
0556         .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
0557         .flush_hw_mask = 0xf4ffffff,
0558     },
0559     .pipe_vig = {
0560         .count = 4,
0561         .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
0562         .caps = MDP_PIPE_CAP_HFLIP  |
0563             MDP_PIPE_CAP_VFLIP  |
0564             MDP_PIPE_CAP_SCALE  |
0565             MDP_PIPE_CAP_CSC    |
0566             MDP_PIPE_CAP_DECIMATION |
0567             MDP_PIPE_CAP_SW_PIX_EXT |
0568             0,
0569     },
0570     .pipe_rgb = {
0571         .count = 4,
0572         .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
0573         .caps = MDP_PIPE_CAP_HFLIP  |
0574             MDP_PIPE_CAP_VFLIP  |
0575             MDP_PIPE_CAP_SCALE  |
0576             MDP_PIPE_CAP_DECIMATION |
0577             MDP_PIPE_CAP_SW_PIX_EXT |
0578             0,
0579     },
0580     .pipe_dma = {
0581         .count = 2,
0582         .base = { 0x24000, 0x26000 },
0583         .caps = MDP_PIPE_CAP_HFLIP  |
0584             MDP_PIPE_CAP_VFLIP  |
0585             MDP_PIPE_CAP_SW_PIX_EXT |
0586             0,
0587     },
0588     .pipe_cursor = {
0589         .count = 2,
0590         .base = { 0x34000, 0x36000 },
0591         .caps = MDP_PIPE_CAP_HFLIP  |
0592             MDP_PIPE_CAP_VFLIP  |
0593             MDP_PIPE_CAP_SW_PIX_EXT |
0594             MDP_PIPE_CAP_CURSOR |
0595             0,
0596     },
0597 
0598     .lm = {
0599         .count = 6,
0600         .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
0601         .instances = {
0602                 { .id = 0, .pp = 0, .dspp = 0,
0603                   .caps = MDP_LM_CAP_DISPLAY |
0604                       MDP_LM_CAP_PAIR, },
0605                 { .id = 1, .pp = 1, .dspp = 1,
0606                   .caps = MDP_LM_CAP_DISPLAY, },
0607                 { .id = 2, .pp = 2, .dspp = -1,
0608                   .caps = MDP_LM_CAP_DISPLAY |
0609                       MDP_LM_CAP_PAIR, },
0610                 { .id = 3, .pp = -1, .dspp = -1,
0611                   .caps = MDP_LM_CAP_WB, },
0612                 { .id = 4, .pp = -1, .dspp = -1,
0613                   .caps = MDP_LM_CAP_WB, },
0614                 { .id = 5, .pp = 3, .dspp = -1,
0615                   .caps = MDP_LM_CAP_DISPLAY, },
0616                  },
0617         .nb_stages = 8,
0618         .max_width = 2560,
0619         .max_height = 0xFFFF,
0620     },
0621     .dspp = {
0622         .count = 2,
0623         .base = { 0x54000, 0x56000 },
0624     },
0625     .ad = {
0626         .count = 3,
0627         .base = { 0x78000, 0x78800, 0x79000 },
0628     },
0629     .pp = {
0630         .count = 4,
0631         .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
0632     },
0633     .cdm = {
0634         .count = 1,
0635         .base = { 0x79200 },
0636     },
0637     .dsc = {
0638         .count = 2,
0639         .base = { 0x80000, 0x80400 },
0640     },
0641     .intf = {
0642         .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
0643         .connect = {
0644             [0] = INTF_DISABLED,
0645             [1] = INTF_DSI,
0646             [2] = INTF_DSI,
0647             [3] = INTF_HDMI,
0648         },
0649     },
0650     .perf = {
0651         .ab_inefficiency = 100,
0652         .ib_inefficiency = 200,
0653         .clk_inefficiency = 105
0654     },
0655     .max_clk = 412500000,
0656 };
0657 
0658 const struct mdp5_cfg_hw msm8x76_config = {
0659     .name = "msm8x76",
0660     .mdp = {
0661         .count = 1,
0662         .caps = MDP_CAP_SMP |
0663             MDP_CAP_DSC |
0664             MDP_CAP_SRC_SPLIT |
0665             0,
0666     },
0667     .ctl = {
0668         .count = 3,
0669         .base = { 0x01000, 0x01200, 0x01400 },
0670         .flush_hw_mask = 0xffffffff,
0671     },
0672     .smp = {
0673         .mmb_count = 10,
0674         .mmb_size = 10240,
0675         .clients = {
0676             [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
0677             [SSPP_DMA0] = 4,
0678             [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
0679         },
0680     },
0681     .pipe_vig = {
0682         .count = 2,
0683         .base = { 0x04000, 0x06000 },
0684         .caps = MDP_PIPE_CAP_HFLIP  |
0685             MDP_PIPE_CAP_VFLIP  |
0686             MDP_PIPE_CAP_SCALE  |
0687             MDP_PIPE_CAP_CSC    |
0688             MDP_PIPE_CAP_DECIMATION |
0689             MDP_PIPE_CAP_SW_PIX_EXT |
0690             0,
0691     },
0692     .pipe_rgb = {
0693         .count = 2,
0694         .base = { 0x14000, 0x16000 },
0695         .caps = MDP_PIPE_CAP_HFLIP  |
0696             MDP_PIPE_CAP_VFLIP  |
0697             MDP_PIPE_CAP_DECIMATION |
0698             MDP_PIPE_CAP_SW_PIX_EXT |
0699             0,
0700     },
0701     .pipe_dma = {
0702         .count = 1,
0703         .base = { 0x24000 },
0704         .caps = MDP_PIPE_CAP_HFLIP  |
0705             MDP_PIPE_CAP_VFLIP  |
0706             MDP_PIPE_CAP_SW_PIX_EXT |
0707             0,
0708     },
0709     .pipe_cursor = {
0710         .count = 1,
0711         .base = { 0x440DC },
0712         .caps = MDP_PIPE_CAP_HFLIP  |
0713             MDP_PIPE_CAP_VFLIP  |
0714             MDP_PIPE_CAP_SW_PIX_EXT |
0715             MDP_PIPE_CAP_CURSOR |
0716             0,
0717     },
0718     .lm = {
0719         .count = 2,
0720         .base = { 0x44000, 0x45000 },
0721         .instances = {
0722                 { .id = 0, .pp = 0, .dspp = 0,
0723                   .caps = MDP_LM_CAP_DISPLAY, },
0724                 { .id = 1, .pp = -1, .dspp = -1,
0725                   .caps = MDP_LM_CAP_WB },
0726                  },
0727         .nb_stages = 8,
0728         .max_width = 2560,
0729         .max_height = 0xFFFF,
0730     },
0731     .dspp = {
0732         .count = 1,
0733         .base = { 0x54000 },
0734 
0735     },
0736     .pp = {
0737         .count = 3,
0738         .base = { 0x70000, 0x70800, 0x72000 },
0739     },
0740     .dsc = {
0741         .count = 2,
0742         .base = { 0x80000, 0x80400 },
0743     },
0744     .intf = {
0745         .base = { 0x6a000, 0x6a800, 0x6b000 },
0746         .connect = {
0747             [0] = INTF_DISABLED,
0748             [1] = INTF_DSI,
0749             [2] = INTF_DSI,
0750         },
0751     },
0752     .max_clk = 360000000,
0753 };
0754 
0755 static const struct mdp5_cfg_hw msm8x53_config = {
0756     .name = "msm8x53",
0757     .mdp = {
0758         .count = 1,
0759         .caps = MDP_CAP_CDM |
0760             MDP_CAP_SRC_SPLIT,
0761     },
0762     .ctl = {
0763         .count = 3,
0764         .base = { 0x01000, 0x01200, 0x01400 },
0765         .flush_hw_mask = 0xffffffff,
0766     },
0767     .pipe_vig = {
0768         .count = 1,
0769         .base = { 0x04000 },
0770         .caps = MDP_PIPE_CAP_HFLIP  |
0771             MDP_PIPE_CAP_VFLIP  |
0772             MDP_PIPE_CAP_SCALE  |
0773             MDP_PIPE_CAP_CSC    |
0774             MDP_PIPE_CAP_DECIMATION |
0775             MDP_PIPE_CAP_SW_PIX_EXT |
0776             0,
0777     },
0778     .pipe_rgb = {
0779         .count = 2,
0780         .base = { 0x14000, 0x16000 },
0781         .caps = MDP_PIPE_CAP_HFLIP  |
0782             MDP_PIPE_CAP_VFLIP  |
0783             MDP_PIPE_CAP_DECIMATION |
0784             MDP_PIPE_CAP_SW_PIX_EXT |
0785             0,
0786     },
0787     .pipe_dma = {
0788         .count = 1,
0789         .base = { 0x24000 },
0790         .caps = MDP_PIPE_CAP_HFLIP  |
0791             MDP_PIPE_CAP_VFLIP  |
0792             MDP_PIPE_CAP_SW_PIX_EXT |
0793             0,
0794     },
0795     .pipe_cursor = {
0796         .count = 1,
0797         .base = { 0x34000 },
0798         .caps = MDP_PIPE_CAP_HFLIP  |
0799             MDP_PIPE_CAP_VFLIP  |
0800             MDP_PIPE_CAP_SW_PIX_EXT |
0801             MDP_PIPE_CAP_CURSOR |
0802             0,
0803     },
0804 
0805     .lm = {
0806         .count = 3,
0807         .base = { 0x44000, 0x45000 },
0808         .instances = {
0809                 { .id = 0, .pp = 0, .dspp = 0,
0810                   .caps = MDP_LM_CAP_DISPLAY |
0811                       MDP_LM_CAP_PAIR },
0812                 { .id = 1, .pp = 1, .dspp = -1,
0813                   .caps = MDP_LM_CAP_DISPLAY },
0814                  },
0815         .nb_stages = 5,
0816         .max_width = 2048,
0817         .max_height = 0xFFFF,
0818     },
0819     .dspp = {
0820         .count = 1,
0821         .base = { 0x54000 },
0822 
0823     },
0824     .pp = {
0825         .count = 2,
0826         .base = { 0x70000, 0x70800 },
0827     },
0828     .cdm = {
0829         .count = 1,
0830         .base = { 0x79200 },
0831     },
0832     .intf = {
0833         .base = { 0x6a000, 0x6a800, 0x6b000 },
0834         .connect = {
0835             [0] = INTF_DISABLED,
0836             [1] = INTF_DSI,
0837             [2] = INTF_DSI,
0838         },
0839     },
0840     .perf = {
0841         .ab_inefficiency = 100,
0842         .ib_inefficiency = 200,
0843         .clk_inefficiency = 105
0844     },
0845     .max_clk = 400000000,
0846 };
0847 
0848 static const struct mdp5_cfg_hw msm8917_config = {
0849     .name = "msm8917",
0850     .mdp = {
0851         .count = 1,
0852         .caps = MDP_CAP_CDM,
0853     },
0854     .ctl = {
0855         .count = 3,
0856         .base = { 0x01000, 0x01200, 0x01400 },
0857         .flush_hw_mask = 0xffffffff,
0858     },
0859     .pipe_vig = {
0860         .count = 1,
0861         .base = { 0x04000 },
0862         .caps = MDP_PIPE_CAP_HFLIP  |
0863             MDP_PIPE_CAP_VFLIP  |
0864             MDP_PIPE_CAP_SCALE  |
0865             MDP_PIPE_CAP_CSC    |
0866             MDP_PIPE_CAP_DECIMATION |
0867             MDP_PIPE_CAP_SW_PIX_EXT |
0868             0,
0869     },
0870     .pipe_rgb = {
0871         .count = 2,
0872         .base = { 0x14000, 0x16000 },
0873         .caps = MDP_PIPE_CAP_HFLIP  |
0874             MDP_PIPE_CAP_VFLIP  |
0875             MDP_PIPE_CAP_DECIMATION |
0876             MDP_PIPE_CAP_SW_PIX_EXT |
0877             0,
0878     },
0879     .pipe_dma = {
0880         .count = 1,
0881         .base = { 0x24000 },
0882         .caps = MDP_PIPE_CAP_HFLIP  |
0883             MDP_PIPE_CAP_VFLIP  |
0884             MDP_PIPE_CAP_SW_PIX_EXT |
0885             0,
0886     },
0887     .pipe_cursor = {
0888         .count = 1,
0889         .base = { 0x34000 },
0890         .caps = MDP_PIPE_CAP_HFLIP  |
0891             MDP_PIPE_CAP_VFLIP  |
0892             MDP_PIPE_CAP_SW_PIX_EXT |
0893             MDP_PIPE_CAP_CURSOR |
0894             0,
0895     },
0896 
0897     .lm = {
0898         .count = 2,
0899         .base = { 0x44000, 0x45000 },
0900         .instances = {
0901                 { .id = 0, .pp = 0, .dspp = 0,
0902                   .caps = MDP_LM_CAP_DISPLAY, },
0903                 { .id = 1, .pp = -1, .dspp = -1,
0904                   .caps = MDP_LM_CAP_WB },
0905                  },
0906         .nb_stages = 8,
0907         .max_width = 2048,
0908         .max_height = 0xFFFF,
0909     },
0910     .dspp = {
0911         .count = 1,
0912         .base = { 0x54000 },
0913 
0914     },
0915     .pp = {
0916         .count = 1,
0917         .base = { 0x70000 },
0918     },
0919     .cdm = {
0920         .count = 1,
0921         .base = { 0x79200 },
0922     },
0923     .intf = {
0924         .base = { 0x6a000, 0x6a800 },
0925         .connect = {
0926             [0] = INTF_DISABLED,
0927             [1] = INTF_DSI,
0928         },
0929     },
0930     .max_clk = 320000000,
0931 };
0932 
0933 static const struct mdp5_cfg_hw msm8998_config = {
0934     .name = "msm8998",
0935     .mdp = {
0936         .count = 1,
0937         .caps = MDP_CAP_DSC |
0938             MDP_CAP_CDM |
0939             MDP_CAP_SRC_SPLIT |
0940             0,
0941     },
0942     .ctl = {
0943         .count = 5,
0944         .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
0945         .flush_hw_mask = 0xf7ffffff,
0946     },
0947     .pipe_vig = {
0948         .count = 4,
0949         .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
0950         .caps = MDP_PIPE_CAP_HFLIP  |
0951             MDP_PIPE_CAP_VFLIP  |
0952             MDP_PIPE_CAP_SCALE  |
0953             MDP_PIPE_CAP_CSC    |
0954             MDP_PIPE_CAP_DECIMATION |
0955             MDP_PIPE_CAP_SW_PIX_EXT |
0956             0,
0957     },
0958     .pipe_rgb = {
0959         .count = 4,
0960         .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
0961         .caps = MDP_PIPE_CAP_HFLIP  |
0962             MDP_PIPE_CAP_VFLIP  |
0963             MDP_PIPE_CAP_SCALE  |
0964             MDP_PIPE_CAP_DECIMATION |
0965             MDP_PIPE_CAP_SW_PIX_EXT |
0966             0,
0967     },
0968     .pipe_dma = {
0969         .count = 2, /* driver supports max of 2 currently */
0970         .base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
0971         .caps = MDP_PIPE_CAP_HFLIP  |
0972             MDP_PIPE_CAP_VFLIP  |
0973             MDP_PIPE_CAP_SW_PIX_EXT |
0974             0,
0975     },
0976     .pipe_cursor = {
0977         .count = 2,
0978         .base = { 0x34000, 0x36000 },
0979         .caps = MDP_PIPE_CAP_HFLIP  |
0980             MDP_PIPE_CAP_VFLIP  |
0981             MDP_PIPE_CAP_SW_PIX_EXT |
0982             MDP_PIPE_CAP_CURSOR |
0983             0,
0984     },
0985 
0986     .lm = {
0987         .count = 6,
0988         .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
0989         .instances = {
0990                 { .id = 0, .pp = 0, .dspp = 0,
0991                   .caps = MDP_LM_CAP_DISPLAY |
0992                       MDP_LM_CAP_PAIR, },
0993                 { .id = 1, .pp = 1, .dspp = 1,
0994                   .caps = MDP_LM_CAP_DISPLAY, },
0995                 { .id = 2, .pp = 2, .dspp = -1,
0996                   .caps = MDP_LM_CAP_DISPLAY |
0997                       MDP_LM_CAP_PAIR, },
0998                 { .id = 3, .pp = -1, .dspp = -1,
0999                   .caps = MDP_LM_CAP_WB, },
1000                 { .id = 4, .pp = -1, .dspp = -1,
1001                   .caps = MDP_LM_CAP_WB, },
1002                 { .id = 5, .pp = 3, .dspp = -1,
1003                   .caps = MDP_LM_CAP_DISPLAY, },
1004                  },
1005         .nb_stages = 8,
1006         .max_width = 2560,
1007         .max_height = 0xFFFF,
1008     },
1009     .dspp = {
1010         .count = 2,
1011         .base = { 0x54000, 0x56000 },
1012     },
1013     .ad = {
1014         .count = 3,
1015         .base = { 0x78000, 0x78800, 0x79000 },
1016     },
1017     .pp = {
1018         .count = 4,
1019         .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
1020     },
1021     .cdm = {
1022         .count = 1,
1023         .base = { 0x79200 },
1024     },
1025     .dsc = {
1026         .count = 2,
1027         .base = { 0x80000, 0x80400 },
1028     },
1029     .intf = {
1030         .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
1031         .connect = {
1032             [0] = INTF_eDP,
1033             [1] = INTF_DSI,
1034             [2] = INTF_DSI,
1035             [3] = INTF_HDMI,
1036         },
1037     },
1038     .max_clk = 412500000,
1039 };
1040 
1041 static const struct mdp5_cfg_hw sdm630_config = {
1042     .name = "sdm630",
1043     .mdp = {
1044         .count = 1,
1045         .caps = MDP_CAP_CDM |
1046             MDP_CAP_SRC_SPLIT |
1047             0,
1048     },
1049     .ctl = {
1050         .count = 5,
1051         .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1052         .flush_hw_mask = 0xf4ffffff,
1053     },
1054     .pipe_vig = {
1055         .count = 1,
1056         .base = { 0x04000 },
1057         .caps = MDP_PIPE_CAP_HFLIP  |
1058             MDP_PIPE_CAP_VFLIP  |
1059             MDP_PIPE_CAP_SCALE  |
1060             MDP_PIPE_CAP_CSC    |
1061             MDP_PIPE_CAP_DECIMATION |
1062             MDP_PIPE_CAP_SW_PIX_EXT |
1063             0,
1064     },
1065     .pipe_rgb = {
1066         .count = 4,
1067         .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1068         .caps = MDP_PIPE_CAP_HFLIP  |
1069             MDP_PIPE_CAP_VFLIP  |
1070             MDP_PIPE_CAP_SCALE  |
1071             MDP_PIPE_CAP_DECIMATION |
1072             MDP_PIPE_CAP_SW_PIX_EXT |
1073             0,
1074     },
1075     .pipe_dma = {
1076         .count = 2, /* driver supports max of 2 currently */
1077         .base = { 0x24000, 0x26000, 0x28000 },
1078         .caps = MDP_PIPE_CAP_HFLIP  |
1079             MDP_PIPE_CAP_VFLIP  |
1080             MDP_PIPE_CAP_SW_PIX_EXT |
1081             0,
1082     },
1083     .pipe_cursor = {
1084         .count = 1,
1085         .base = { 0x34000 },
1086         .caps = MDP_PIPE_CAP_HFLIP  |
1087             MDP_PIPE_CAP_VFLIP  |
1088             MDP_PIPE_CAP_SW_PIX_EXT |
1089             MDP_PIPE_CAP_CURSOR |
1090             0,
1091     },
1092 
1093     .lm = {
1094         .count = 2,
1095         .base = { 0x44000, 0x46000 },
1096         .instances = {
1097                 { .id = 0, .pp = 0, .dspp = 0,
1098                   .caps = MDP_LM_CAP_DISPLAY |
1099                       MDP_LM_CAP_PAIR, },
1100                 { .id = 1, .pp = 1, .dspp = -1,
1101                   .caps = MDP_LM_CAP_WB, },
1102                 },
1103         .nb_stages = 8,
1104         .max_width = 2048,
1105         .max_height = 0xFFFF,
1106     },
1107     .dspp = {
1108         .count = 1,
1109         .base = { 0x54000 },
1110     },
1111     .ad = {
1112         .count = 2,
1113         .base = { 0x78000, 0x78800 },
1114     },
1115     .pp = {
1116         .count = 3,
1117         .base = { 0x70000, 0x71000, 0x72000 },
1118     },
1119     .cdm = {
1120         .count = 1,
1121         .base = { 0x79200 },
1122     },
1123     .intf = {
1124         .base = { 0x6a000, 0x6a800 },
1125         .connect = {
1126             [0] = INTF_DISABLED,
1127             [1] = INTF_DSI,
1128         },
1129     },
1130     .max_clk = 412500000,
1131 };
1132 
1133 static const struct mdp5_cfg_hw sdm660_config = {
1134     .name = "sdm660",
1135     .mdp = {
1136         .count = 1,
1137         .caps = MDP_CAP_DSC |
1138             MDP_CAP_CDM |
1139             MDP_CAP_SRC_SPLIT |
1140             0,
1141     },
1142     .ctl = {
1143         .count = 5,
1144         .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1145         .flush_hw_mask = 0xf4ffffff,
1146     },
1147     .pipe_vig = {
1148         .count = 2,
1149         .base = { 0x04000, 0x6000 },
1150         .caps = MDP_PIPE_CAP_HFLIP  |
1151             MDP_PIPE_CAP_VFLIP  |
1152             MDP_PIPE_CAP_SCALE  |
1153             MDP_PIPE_CAP_CSC    |
1154             MDP_PIPE_CAP_DECIMATION |
1155             MDP_PIPE_CAP_SW_PIX_EXT |
1156             0,
1157     },
1158     .pipe_rgb = {
1159         .count = 4,
1160         .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1161         .caps = MDP_PIPE_CAP_HFLIP  |
1162             MDP_PIPE_CAP_VFLIP  |
1163             MDP_PIPE_CAP_SCALE  |
1164             MDP_PIPE_CAP_DECIMATION |
1165             MDP_PIPE_CAP_SW_PIX_EXT |
1166             0,
1167     },
1168     .pipe_dma = {
1169         .count = 2, /* driver supports max of 2 currently */
1170         .base = { 0x24000, 0x26000, 0x28000 },
1171         .caps = MDP_PIPE_CAP_HFLIP  |
1172             MDP_PIPE_CAP_VFLIP  |
1173             MDP_PIPE_CAP_SW_PIX_EXT |
1174             0,
1175     },
1176     .pipe_cursor = {
1177         .count = 1,
1178         .base = { 0x34000 },
1179         .caps = MDP_PIPE_CAP_HFLIP  |
1180             MDP_PIPE_CAP_VFLIP  |
1181             MDP_PIPE_CAP_SW_PIX_EXT |
1182             MDP_PIPE_CAP_CURSOR |
1183             0,
1184     },
1185 
1186     .lm = {
1187         .count = 4,
1188         .base = { 0x44000, 0x45000, 0x46000, 0x49000 },
1189         .instances = {
1190                 { .id = 0, .pp = 0, .dspp = 0,
1191                   .caps = MDP_LM_CAP_DISPLAY |
1192                       MDP_LM_CAP_PAIR, },
1193                 { .id = 1, .pp = 1, .dspp = 1,
1194                   .caps = MDP_LM_CAP_DISPLAY, },
1195                 { .id = 2, .pp = 2, .dspp = -1,
1196                   .caps = MDP_LM_CAP_DISPLAY |
1197                       MDP_LM_CAP_PAIR, },
1198                 { .id = 3, .pp = 3, .dspp = -1,
1199                   .caps = MDP_LM_CAP_WB, },
1200                 },
1201         .nb_stages = 8,
1202         .max_width = 2560,
1203         .max_height = 0xFFFF,
1204     },
1205     .dspp = {
1206         .count = 2,
1207         .base = { 0x54000, 0x56000 },
1208     },
1209     .ad = {
1210         .count = 2,
1211         .base = { 0x78000, 0x78800 },
1212     },
1213     .pp = {
1214         .count = 5,
1215         .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
1216     },
1217     .cdm = {
1218         .count = 1,
1219         .base = { 0x79200 },
1220     },
1221     .dsc = {
1222         .count = 2,
1223         .base = { 0x80000, 0x80400 },
1224     },
1225     .intf = {
1226         .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
1227         .connect = {
1228             [0] = INTF_DISABLED,
1229             [1] = INTF_DSI,
1230             [2] = INTF_DSI,
1231             [3] = INTF_HDMI,
1232         },
1233     },
1234     .max_clk = 412500000,
1235 };
1236 
1237 static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
1238     { .revision = 0, .config = { .hw = &msm8x74v1_config } },
1239     { .revision = 2, .config = { .hw = &msm8x74v2_config } },
1240     { .revision = 3, .config = { .hw = &apq8084_config } },
1241     { .revision = 6, .config = { .hw = &msm8x16_config } },
1242     { .revision = 8, .config = { .hw = &msm8x36_config } },
1243     { .revision = 9, .config = { .hw = &msm8x94_config } },
1244     { .revision = 7, .config = { .hw = &msm8x96_config } },
1245     { .revision = 11, .config = { .hw = &msm8x76_config } },
1246     { .revision = 15, .config = { .hw = &msm8917_config } },
1247     { .revision = 16, .config = { .hw = &msm8x53_config } },
1248 };
1249 
1250 static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
1251     { .revision = 0, .config = { .hw = &msm8998_config } },
1252     { .revision = 2, .config = { .hw = &sdm660_config } },
1253     { .revision = 3, .config = { .hw = &sdm630_config } },
1254 };
1255 
1256 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
1257 {
1258     return cfg_handler->config.hw;
1259 }
1260 
1261 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
1262 {
1263     return &cfg_handler->config;
1264 }
1265 
1266 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
1267 {
1268     return cfg_handler->revision;
1269 }
1270 
1271 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
1272 {
1273     kfree(cfg_handler);
1274 }
1275 
1276 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
1277         uint32_t major, uint32_t minor)
1278 {
1279     struct drm_device *dev = mdp5_kms->dev;
1280     struct mdp5_cfg_handler *cfg_handler;
1281     const struct mdp5_cfg_handler *cfg_handlers;
1282     int i, ret = 0, num_handlers;
1283 
1284     cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
1285     if (unlikely(!cfg_handler)) {
1286         ret = -ENOMEM;
1287         goto fail;
1288     }
1289 
1290     switch (major) {
1291     case 1:
1292         cfg_handlers = cfg_handlers_v1;
1293         num_handlers = ARRAY_SIZE(cfg_handlers_v1);
1294         break;
1295     case 3:
1296         cfg_handlers = cfg_handlers_v3;
1297         num_handlers = ARRAY_SIZE(cfg_handlers_v3);
1298         break;
1299     default:
1300         DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
1301                 major, minor);
1302         ret = -ENXIO;
1303         goto fail;
1304     }
1305 
1306     /* only after mdp5_cfg global pointer's init can we access the hw */
1307     for (i = 0; i < num_handlers; i++) {
1308         if (cfg_handlers[i].revision != minor)
1309             continue;
1310         mdp5_cfg = cfg_handlers[i].config.hw;
1311 
1312         break;
1313     }
1314     if (unlikely(!mdp5_cfg)) {
1315         DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
1316                 major, minor);
1317         ret = -ENXIO;
1318         goto fail;
1319     }
1320 
1321     cfg_handler->revision = minor;
1322     cfg_handler->config.hw = mdp5_cfg;
1323 
1324     DBG("MDP5: %s hw config selected", mdp5_cfg->name);
1325 
1326     return cfg_handler;
1327 
1328 fail:
1329     if (cfg_handler)
1330         mdp5_cfg_destroy(cfg_handler);
1331 
1332     return ERR_PTR(ret);
1333 }
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