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0001 #ifndef MDP5_XML
0002 #define MDP5_XML
0003 
0004 /* Autogenerated file, DO NOT EDIT manually!
0005 
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009 
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
0024 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
0025 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
0026 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
0027 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
0028 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)
0029 
0030 Copyright (C) 2013-2021 by the following authors:
0031 - Rob Clark <robdclark@gmail.com> (robclark)
0032 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0033 
0034 Permission is hereby granted, free of charge, to any person obtaining
0035 a copy of this software and associated documentation files (the
0036 "Software"), to deal in the Software without restriction, including
0037 without limitation the rights to use, copy, modify, merge, publish,
0038 distribute, sublicense, and/or sell copies of the Software, and to
0039 permit persons to whom the Software is furnished to do so, subject to
0040 the following conditions:
0041 
0042 The above copyright notice and this permission notice (including the
0043 next paragraph) shall be included in all copies or substantial
0044 portions of the Software.
0045 
0046 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0047 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0048 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0049 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0050 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0051 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0052 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0053 */
0054 
0055 
0056 enum mdp5_intf_type {
0057     INTF_DISABLED = 0,
0058     INTF_DSI = 1,
0059     INTF_HDMI = 3,
0060     INTF_LCDC = 5,
0061     INTF_eDP = 9,
0062     INTF_VIRTUAL = 100,
0063     INTF_WB = 101,
0064 };
0065 
0066 enum mdp5_intfnum {
0067     NO_INTF = 0,
0068     INTF0 = 1,
0069     INTF1 = 2,
0070     INTF2 = 3,
0071     INTF3 = 4,
0072 };
0073 
0074 enum mdp5_pipe {
0075     SSPP_NONE = 0,
0076     SSPP_VIG0 = 1,
0077     SSPP_VIG1 = 2,
0078     SSPP_VIG2 = 3,
0079     SSPP_RGB0 = 4,
0080     SSPP_RGB1 = 5,
0081     SSPP_RGB2 = 6,
0082     SSPP_DMA0 = 7,
0083     SSPP_DMA1 = 8,
0084     SSPP_VIG3 = 9,
0085     SSPP_RGB3 = 10,
0086     SSPP_CURSOR0 = 11,
0087     SSPP_CURSOR1 = 12,
0088 };
0089 
0090 enum mdp5_format {
0091     DUMMY = 0,
0092 };
0093 
0094 enum mdp5_ctl_mode {
0095     MODE_NONE = 0,
0096     MODE_WB_0_BLOCK = 1,
0097     MODE_WB_1_BLOCK = 2,
0098     MODE_WB_0_LINE = 3,
0099     MODE_WB_1_LINE = 4,
0100     MODE_WB_2_LINE = 5,
0101 };
0102 
0103 enum mdp5_pack_3d {
0104     PACK_3D_FRAME_INT = 0,
0105     PACK_3D_H_ROW_INT = 1,
0106     PACK_3D_V_ROW_INT = 2,
0107     PACK_3D_COL_INT = 3,
0108 };
0109 
0110 enum mdp5_scale_filter {
0111     SCALE_FILTER_NEAREST = 0,
0112     SCALE_FILTER_BIL = 1,
0113     SCALE_FILTER_PCMN = 2,
0114     SCALE_FILTER_CA = 3,
0115 };
0116 
0117 enum mdp5_pipe_bwc {
0118     BWC_LOSSLESS = 0,
0119     BWC_Q_HIGH = 1,
0120     BWC_Q_MED = 2,
0121 };
0122 
0123 enum mdp5_cursor_format {
0124     CURSOR_FMT_ARGB8888 = 0,
0125     CURSOR_FMT_ARGB1555 = 2,
0126     CURSOR_FMT_ARGB4444 = 4,
0127 };
0128 
0129 enum mdp5_cursor_alpha {
0130     CURSOR_ALPHA_CONST = 0,
0131     CURSOR_ALPHA_PER_PIXEL = 2,
0132 };
0133 
0134 enum mdp5_igc_type {
0135     IGC_VIG = 0,
0136     IGC_RGB = 1,
0137     IGC_DMA = 2,
0138     IGC_DSPP = 3,
0139 };
0140 
0141 enum mdp5_data_format {
0142     DATA_FORMAT_RGB = 0,
0143     DATA_FORMAT_YUV = 1,
0144 };
0145 
0146 enum mdp5_block_size {
0147     BLOCK_SIZE_64 = 0,
0148     BLOCK_SIZE_128 = 1,
0149 };
0150 
0151 enum mdp5_rotate_mode {
0152     ROTATE_0 = 0,
0153     ROTATE_90 = 1,
0154 };
0155 
0156 enum mdp5_chroma_downsample_method {
0157     DS_MTHD_NO_PIXEL_DROP = 0,
0158     DS_MTHD_PIXEL_DROP = 1,
0159 };
0160 
0161 #define MDP5_IRQ_WB_0_DONE                  0x00000001
0162 #define MDP5_IRQ_WB_1_DONE                  0x00000002
0163 #define MDP5_IRQ_WB_2_DONE                  0x00000010
0164 #define MDP5_IRQ_PING_PONG_0_DONE               0x00000100
0165 #define MDP5_IRQ_PING_PONG_1_DONE               0x00000200
0166 #define MDP5_IRQ_PING_PONG_2_DONE               0x00000400
0167 #define MDP5_IRQ_PING_PONG_3_DONE               0x00000800
0168 #define MDP5_IRQ_PING_PONG_0_RD_PTR             0x00001000
0169 #define MDP5_IRQ_PING_PONG_1_RD_PTR             0x00002000
0170 #define MDP5_IRQ_PING_PONG_2_RD_PTR             0x00004000
0171 #define MDP5_IRQ_PING_PONG_3_RD_PTR             0x00008000
0172 #define MDP5_IRQ_PING_PONG_0_WR_PTR             0x00010000
0173 #define MDP5_IRQ_PING_PONG_1_WR_PTR             0x00020000
0174 #define MDP5_IRQ_PING_PONG_2_WR_PTR             0x00040000
0175 #define MDP5_IRQ_PING_PONG_3_WR_PTR             0x00080000
0176 #define MDP5_IRQ_PING_PONG_0_AUTO_REF               0x00100000
0177 #define MDP5_IRQ_PING_PONG_1_AUTO_REF               0x00200000
0178 #define MDP5_IRQ_PING_PONG_2_AUTO_REF               0x00400000
0179 #define MDP5_IRQ_PING_PONG_3_AUTO_REF               0x00800000
0180 #define MDP5_IRQ_INTF0_UNDER_RUN                0x01000000
0181 #define MDP5_IRQ_INTF0_VSYNC                    0x02000000
0182 #define MDP5_IRQ_INTF1_UNDER_RUN                0x04000000
0183 #define MDP5_IRQ_INTF1_VSYNC                    0x08000000
0184 #define MDP5_IRQ_INTF2_UNDER_RUN                0x10000000
0185 #define MDP5_IRQ_INTF2_VSYNC                    0x20000000
0186 #define MDP5_IRQ_INTF3_UNDER_RUN                0x40000000
0187 #define MDP5_IRQ_INTF3_VSYNC                    0x80000000
0188 #define REG_MDSS_HW_VERSION                 0x00000000
0189 #define MDSS_HW_VERSION_STEP__MASK              0x0000ffff
0190 #define MDSS_HW_VERSION_STEP__SHIFT             0
0191 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
0192 {
0193     return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
0194 }
0195 #define MDSS_HW_VERSION_MINOR__MASK             0x0fff0000
0196 #define MDSS_HW_VERSION_MINOR__SHIFT                16
0197 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
0198 {
0199     return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
0200 }
0201 #define MDSS_HW_VERSION_MAJOR__MASK             0xf0000000
0202 #define MDSS_HW_VERSION_MAJOR__SHIFT                28
0203 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
0204 {
0205     return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
0206 }
0207 
0208 #define REG_MDSS_HW_INTR_STATUS                 0x00000010
0209 #define MDSS_HW_INTR_STATUS_INTR_MDP                0x00000001
0210 #define MDSS_HW_INTR_STATUS_INTR_DSI0               0x00000010
0211 #define MDSS_HW_INTR_STATUS_INTR_DSI1               0x00000020
0212 #define MDSS_HW_INTR_STATUS_INTR_HDMI               0x00000100
0213 #define MDSS_HW_INTR_STATUS_INTR_EDP                0x00001000
0214 
0215 #define REG_MDP5_HW_VERSION                 0x00000000
0216 #define MDP5_HW_VERSION_STEP__MASK              0x0000ffff
0217 #define MDP5_HW_VERSION_STEP__SHIFT             0
0218 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
0219 {
0220     return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK;
0221 }
0222 #define MDP5_HW_VERSION_MINOR__MASK             0x0fff0000
0223 #define MDP5_HW_VERSION_MINOR__SHIFT                16
0224 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
0225 {
0226     return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK;
0227 }
0228 #define MDP5_HW_VERSION_MAJOR__MASK             0xf0000000
0229 #define MDP5_HW_VERSION_MAJOR__SHIFT                28
0230 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
0231 {
0232     return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK;
0233 }
0234 
0235 #define REG_MDP5_DISP_INTF_SEL                  0x00000004
0236 #define MDP5_DISP_INTF_SEL_INTF0__MASK              0x000000ff
0237 #define MDP5_DISP_INTF_SEL_INTF0__SHIFT             0
0238 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
0239 {
0240     return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
0241 }
0242 #define MDP5_DISP_INTF_SEL_INTF1__MASK              0x0000ff00
0243 #define MDP5_DISP_INTF_SEL_INTF1__SHIFT             8
0244 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
0245 {
0246     return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
0247 }
0248 #define MDP5_DISP_INTF_SEL_INTF2__MASK              0x00ff0000
0249 #define MDP5_DISP_INTF_SEL_INTF2__SHIFT             16
0250 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
0251 {
0252     return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
0253 }
0254 #define MDP5_DISP_INTF_SEL_INTF3__MASK              0xff000000
0255 #define MDP5_DISP_INTF_SEL_INTF3__SHIFT             24
0256 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
0257 {
0258     return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
0259 }
0260 
0261 #define REG_MDP5_INTR_EN                    0x00000010
0262 
0263 #define REG_MDP5_INTR_STATUS                    0x00000014
0264 
0265 #define REG_MDP5_INTR_CLEAR                 0x00000018
0266 
0267 #define REG_MDP5_HIST_INTR_EN                   0x0000001c
0268 
0269 #define REG_MDP5_HIST_INTR_STATUS               0x00000020
0270 
0271 #define REG_MDP5_HIST_INTR_CLEAR                0x00000024
0272 
0273 #define REG_MDP5_SPARE_0                    0x00000028
0274 #define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN          0x00000001
0275 
0276 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
0277 
0278 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
0279 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK          0x000000ff
0280 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT         0
0281 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
0282 {
0283     return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
0284 }
0285 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK          0x0000ff00
0286 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT         8
0287 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
0288 {
0289     return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
0290 }
0291 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK          0x00ff0000
0292 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT         16
0293 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
0294 {
0295     return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
0296 }
0297 
0298 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
0299 
0300 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
0301 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK          0x000000ff
0302 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT         0
0303 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
0304 {
0305     return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
0306 }
0307 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK          0x0000ff00
0308 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT         8
0309 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
0310 {
0311     return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
0312 }
0313 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK          0x00ff0000
0314 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT         16
0315 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
0316 {
0317     return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
0318 }
0319 
0320 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
0321 {
0322     switch (idx) {
0323         case IGC_VIG: return 0x00000200;
0324         case IGC_RGB: return 0x00000210;
0325         case IGC_DMA: return 0x00000220;
0326         case IGC_DSPP: return 0x00000300;
0327         default: return INVALID_IDX(idx);
0328     }
0329 }
0330 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
0331 
0332 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
0333 
0334 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
0335 #define MDP5_IGC_LUT_REG_VAL__MASK              0x00000fff
0336 #define MDP5_IGC_LUT_REG_VAL__SHIFT             0
0337 static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
0338 {
0339     return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
0340 }
0341 #define MDP5_IGC_LUT_REG_INDEX_UPDATE               0x02000000
0342 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0             0x10000000
0343 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1             0x20000000
0344 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2             0x40000000
0345 
0346 #define REG_MDP5_SPLIT_DPL_EN                   0x000002f4
0347 
0348 #define REG_MDP5_SPLIT_DPL_UPPER                0x000002f8
0349 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL            0x00000002
0350 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN       0x00000004
0351 #define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX           0x00000010
0352 #define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX           0x00000100
0353 
0354 #define REG_MDP5_SPLIT_DPL_LOWER                0x000003f0
0355 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL            0x00000002
0356 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN       0x00000004
0357 #define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC          0x00000010
0358 #define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC          0x00000100
0359 
0360 static inline uint32_t __offset_CTL(uint32_t idx)
0361 {
0362     switch (idx) {
0363         case 0: return (mdp5_cfg->ctl.base[0]);
0364         case 1: return (mdp5_cfg->ctl.base[1]);
0365         case 2: return (mdp5_cfg->ctl.base[2]);
0366         case 3: return (mdp5_cfg->ctl.base[3]);
0367         case 4: return (mdp5_cfg->ctl.base[4]);
0368         default: return INVALID_IDX(idx);
0369     }
0370 }
0371 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
0372 
0373 static inline uint32_t __offset_LAYER(uint32_t idx)
0374 {
0375     switch (idx) {
0376         case 0: return 0x00000000;
0377         case 1: return 0x00000004;
0378         case 2: return 0x00000008;
0379         case 3: return 0x0000000c;
0380         case 4: return 0x00000010;
0381         case 5: return 0x00000024;
0382         default: return INVALID_IDX(idx);
0383     }
0384 }
0385 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
0386 
0387 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
0388 #define MDP5_CTL_LAYER_REG_VIG0__MASK               0x00000007
0389 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT              0
0390 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
0391 {
0392     return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
0393 }
0394 #define MDP5_CTL_LAYER_REG_VIG1__MASK               0x00000038
0395 #define MDP5_CTL_LAYER_REG_VIG1__SHIFT              3
0396 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
0397 {
0398     return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
0399 }
0400 #define MDP5_CTL_LAYER_REG_VIG2__MASK               0x000001c0
0401 #define MDP5_CTL_LAYER_REG_VIG2__SHIFT              6
0402 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
0403 {
0404     return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
0405 }
0406 #define MDP5_CTL_LAYER_REG_RGB0__MASK               0x00000e00
0407 #define MDP5_CTL_LAYER_REG_RGB0__SHIFT              9
0408 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
0409 {
0410     return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
0411 }
0412 #define MDP5_CTL_LAYER_REG_RGB1__MASK               0x00007000
0413 #define MDP5_CTL_LAYER_REG_RGB1__SHIFT              12
0414 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
0415 {
0416     return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
0417 }
0418 #define MDP5_CTL_LAYER_REG_RGB2__MASK               0x00038000
0419 #define MDP5_CTL_LAYER_REG_RGB2__SHIFT              15
0420 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
0421 {
0422     return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
0423 }
0424 #define MDP5_CTL_LAYER_REG_DMA0__MASK               0x001c0000
0425 #define MDP5_CTL_LAYER_REG_DMA0__SHIFT              18
0426 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
0427 {
0428     return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
0429 }
0430 #define MDP5_CTL_LAYER_REG_DMA1__MASK               0x00e00000
0431 #define MDP5_CTL_LAYER_REG_DMA1__SHIFT              21
0432 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
0433 {
0434     return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
0435 }
0436 #define MDP5_CTL_LAYER_REG_BORDER_COLOR             0x01000000
0437 #define MDP5_CTL_LAYER_REG_CURSOR_OUT               0x02000000
0438 #define MDP5_CTL_LAYER_REG_VIG3__MASK               0x1c000000
0439 #define MDP5_CTL_LAYER_REG_VIG3__SHIFT              26
0440 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
0441 {
0442     return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
0443 }
0444 #define MDP5_CTL_LAYER_REG_RGB3__MASK               0xe0000000
0445 #define MDP5_CTL_LAYER_REG_RGB3__SHIFT              29
0446 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
0447 {
0448     return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
0449 }
0450 
0451 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
0452 #define MDP5_CTL_OP_MODE__MASK                  0x0000000f
0453 #define MDP5_CTL_OP_MODE__SHIFT                 0
0454 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
0455 {
0456     return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
0457 }
0458 #define MDP5_CTL_OP_INTF_NUM__MASK              0x00000070
0459 #define MDP5_CTL_OP_INTF_NUM__SHIFT             4
0460 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
0461 {
0462     return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
0463 }
0464 #define MDP5_CTL_OP_CMD_MODE                    0x00020000
0465 #define MDP5_CTL_OP_PACK_3D_ENABLE              0x00080000
0466 #define MDP5_CTL_OP_PACK_3D__MASK               0x00300000
0467 #define MDP5_CTL_OP_PACK_3D__SHIFT              20
0468 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
0469 {
0470     return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
0471 }
0472 
0473 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
0474 #define MDP5_CTL_FLUSH_VIG0                 0x00000001
0475 #define MDP5_CTL_FLUSH_VIG1                 0x00000002
0476 #define MDP5_CTL_FLUSH_VIG2                 0x00000004
0477 #define MDP5_CTL_FLUSH_RGB0                 0x00000008
0478 #define MDP5_CTL_FLUSH_RGB1                 0x00000010
0479 #define MDP5_CTL_FLUSH_RGB2                 0x00000020
0480 #define MDP5_CTL_FLUSH_LM0                  0x00000040
0481 #define MDP5_CTL_FLUSH_LM1                  0x00000080
0482 #define MDP5_CTL_FLUSH_LM2                  0x00000100
0483 #define MDP5_CTL_FLUSH_LM3                  0x00000200
0484 #define MDP5_CTL_FLUSH_LM4                  0x00000400
0485 #define MDP5_CTL_FLUSH_DMA0                 0x00000800
0486 #define MDP5_CTL_FLUSH_DMA1                 0x00001000
0487 #define MDP5_CTL_FLUSH_DSPP0                    0x00002000
0488 #define MDP5_CTL_FLUSH_DSPP1                    0x00004000
0489 #define MDP5_CTL_FLUSH_DSPP2                    0x00008000
0490 #define MDP5_CTL_FLUSH_WB                   0x00010000
0491 #define MDP5_CTL_FLUSH_CTL                  0x00020000
0492 #define MDP5_CTL_FLUSH_VIG3                 0x00040000
0493 #define MDP5_CTL_FLUSH_RGB3                 0x00080000
0494 #define MDP5_CTL_FLUSH_LM5                  0x00100000
0495 #define MDP5_CTL_FLUSH_DSPP3                    0x00200000
0496 #define MDP5_CTL_FLUSH_CURSOR_0                 0x00400000
0497 #define MDP5_CTL_FLUSH_CURSOR_1                 0x00800000
0498 #define MDP5_CTL_FLUSH_CHROMADOWN_0             0x04000000
0499 #define MDP5_CTL_FLUSH_TIMING_3                 0x10000000
0500 #define MDP5_CTL_FLUSH_TIMING_2                 0x20000000
0501 #define MDP5_CTL_FLUSH_TIMING_1                 0x40000000
0502 #define MDP5_CTL_FLUSH_TIMING_0                 0x80000000
0503 
0504 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
0505 
0506 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
0507 
0508 static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
0509 {
0510     switch (idx) {
0511         case 0: return 0x00000040;
0512         case 1: return 0x00000044;
0513         case 2: return 0x00000048;
0514         case 3: return 0x0000004c;
0515         case 4: return 0x00000050;
0516         case 5: return 0x00000054;
0517         default: return INVALID_IDX(idx);
0518     }
0519 }
0520 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
0521 
0522 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
0523 #define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3            0x00000001
0524 #define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3            0x00000004
0525 #define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3            0x00000010
0526 #define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3            0x00000040
0527 #define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3            0x00000100
0528 #define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3            0x00000400
0529 #define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3            0x00001000
0530 #define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3            0x00004000
0531 #define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3            0x00010000
0532 #define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3            0x00040000
0533 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK            0x00f00000
0534 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT           20
0535 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
0536 {
0537     return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
0538 }
0539 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK            0x3c000000
0540 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT           26
0541 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
0542 {
0543     return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
0544 }
0545 
0546 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
0547 {
0548     switch (idx) {
0549         case SSPP_NONE: return (INVALID_IDX(idx));
0550         case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
0551         case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
0552         case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
0553         case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
0554         case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
0555         case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
0556         case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
0557         case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
0558         case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
0559         case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
0560         case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]);
0561         case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]);
0562         default: return INVALID_IDX(idx);
0563     }
0564 }
0565 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
0566 
0567 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
0568 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK     0x00080000
0569 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT        19
0570 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
0571 {
0572     return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
0573 }
0574 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK     0x00040000
0575 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT        18
0576 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
0577 {
0578     return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
0579 }
0580 #define MDP5_PIPE_OP_MODE_CSC_1_EN              0x00020000
0581 
0582 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
0583 
0584 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
0585 
0586 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
0587 
0588 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
0589 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK       0x00001fff
0590 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT      0
0591 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
0592 {
0593     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
0594 }
0595 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK       0x1fff0000
0596 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT      16
0597 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
0598 {
0599     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
0600 }
0601 
0602 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
0603 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK       0x00001fff
0604 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT      0
0605 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
0606 {
0607     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
0608 }
0609 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK       0x1fff0000
0610 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT      16
0611 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
0612 {
0613     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
0614 }
0615 
0616 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
0617 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK       0x00001fff
0618 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT      0
0619 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
0620 {
0621     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
0622 }
0623 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK       0x1fff0000
0624 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT      16
0625 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
0626 {
0627     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
0628 }
0629 
0630 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
0631 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK       0x00001fff
0632 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT      0
0633 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
0634 {
0635     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
0636 }
0637 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK       0x1fff0000
0638 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT      16
0639 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
0640 {
0641     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
0642 }
0643 
0644 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
0645 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK       0x00001fff
0646 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT      0
0647 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
0648 {
0649     return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
0650 }
0651 
0652 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
0653 
0654 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
0655 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK        0x000000ff
0656 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT       0
0657 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
0658 {
0659     return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
0660 }
0661 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK         0x0000ff00
0662 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT        8
0663 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
0664 {
0665     return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
0666 }
0667 
0668 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
0669 
0670 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
0671 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK       0x000000ff
0672 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT      0
0673 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
0674 {
0675     return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
0676 }
0677 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK        0x0000ff00
0678 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT       8
0679 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
0680 {
0681     return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
0682 }
0683 
0684 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
0685 
0686 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
0687 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK        0x000001ff
0688 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT       0
0689 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
0690 {
0691     return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
0692 }
0693 
0694 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
0695 
0696 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
0697 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK       0x000001ff
0698 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT      0
0699 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
0700 {
0701     return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
0702 }
0703 
0704 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
0705 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK             0xffff0000
0706 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT            16
0707 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
0708 {
0709     return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
0710 }
0711 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK              0x0000ffff
0712 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT             0
0713 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
0714 {
0715     return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
0716 }
0717 
0718 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
0719 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK         0xffff0000
0720 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT            16
0721 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
0722 {
0723     return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
0724 }
0725 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK          0x0000ffff
0726 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT         0
0727 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
0728 {
0729     return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
0730 }
0731 
0732 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
0733 #define MDP5_PIPE_SRC_XY_Y__MASK                0xffff0000
0734 #define MDP5_PIPE_SRC_XY_Y__SHIFT               16
0735 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
0736 {
0737     return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
0738 }
0739 #define MDP5_PIPE_SRC_XY_X__MASK                0x0000ffff
0740 #define MDP5_PIPE_SRC_XY_X__SHIFT               0
0741 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
0742 {
0743     return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
0744 }
0745 
0746 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
0747 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK             0xffff0000
0748 #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT            16
0749 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
0750 {
0751     return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
0752 }
0753 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK              0x0000ffff
0754 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT             0
0755 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
0756 {
0757     return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
0758 }
0759 
0760 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
0761 #define MDP5_PIPE_OUT_XY_Y__MASK                0xffff0000
0762 #define MDP5_PIPE_OUT_XY_Y__SHIFT               16
0763 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
0764 {
0765     return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
0766 }
0767 #define MDP5_PIPE_OUT_XY_X__MASK                0x0000ffff
0768 #define MDP5_PIPE_OUT_XY_X__SHIFT               0
0769 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
0770 {
0771     return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
0772 }
0773 
0774 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
0775 
0776 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
0777 
0778 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
0779 
0780 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
0781 
0782 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
0783 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK             0x0000ffff
0784 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT            0
0785 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
0786 {
0787     return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
0788 }
0789 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK             0xffff0000
0790 #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT            16
0791 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
0792 {
0793     return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
0794 }
0795 
0796 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
0797 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK             0x0000ffff
0798 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT            0
0799 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
0800 {
0801     return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
0802 }
0803 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK             0xffff0000
0804 #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT            16
0805 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
0806 {
0807     return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
0808 }
0809 
0810 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
0811 
0812 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
0813 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK            0x00000003
0814 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT           0
0815 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
0816 {
0817     return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
0818 }
0819 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK            0x0000000c
0820 #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT           2
0821 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
0822 {
0823     return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
0824 }
0825 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK            0x00000030
0826 #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT           4
0827 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
0828 {
0829     return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
0830 }
0831 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK            0x000000c0
0832 #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT           6
0833 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
0834 {
0835     return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
0836 }
0837 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE           0x00000100
0838 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK              0x00000600
0839 #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT             9
0840 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
0841 {
0842     return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
0843 }
0844 #define MDP5_PIPE_SRC_FORMAT_ROT90              0x00000800
0845 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK         0x00003000
0846 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT        12
0847 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
0848 {
0849     return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
0850 }
0851 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT           0x00020000
0852 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB           0x00040000
0853 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK           0x00180000
0854 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT          19
0855 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
0856 {
0857     return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
0858 }
0859 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK          0x01800000
0860 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT         23
0861 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
0862 {
0863     return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
0864 }
0865 
0866 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
0867 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK            0x000000ff
0868 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT           0
0869 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
0870 {
0871     return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
0872 }
0873 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK            0x0000ff00
0874 #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT           8
0875 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
0876 {
0877     return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
0878 }
0879 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK            0x00ff0000
0880 #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT           16
0881 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
0882 {
0883     return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
0884 }
0885 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK            0xff000000
0886 #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT           24
0887 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
0888 {
0889     return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
0890 }
0891 
0892 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
0893 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN                0x00000001
0894 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK             0x00000006
0895 #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT            1
0896 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
0897 {
0898     return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
0899 }
0900 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR               0x00002000
0901 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD               0x00004000
0902 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN                0x00010000
0903 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0             0x00020000
0904 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1             0x00040000
0905 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE           0x00400000
0906 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD           0x00800000
0907 #define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE       0x80000000
0908 
0909 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
0910 
0911 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
0912 
0913 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
0914 
0915 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
0916 
0917 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
0918 
0919 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
0920 
0921 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
0922 
0923 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
0924 
0925 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
0926 
0927 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
0928 
0929 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
0930 
0931 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
0932 #define MDP5_PIPE_DECIMATION_VERT__MASK             0x000000ff
0933 #define MDP5_PIPE_DECIMATION_VERT__SHIFT            0
0934 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
0935 {
0936     return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
0937 }
0938 #define MDP5_PIPE_DECIMATION_HORZ__MASK             0x0000ff00
0939 #define MDP5_PIPE_DECIMATION_HORZ__SHIFT            8
0940 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
0941 {
0942     return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
0943 }
0944 
0945 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
0946 {
0947     switch (idx) {
0948         case COMP_0: return 0x00000100;
0949         case COMP_1_2: return 0x00000110;
0950         case COMP_3: return 0x00000120;
0951         default: return INVALID_IDX(idx);
0952     }
0953 }
0954 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
0955 
0956 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
0957 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK          0x000000ff
0958 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT         0
0959 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
0960 {
0961     return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
0962 }
0963 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK          0x0000ff00
0964 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT         8
0965 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
0966 {
0967     return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
0968 }
0969 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK         0x00ff0000
0970 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT        16
0971 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
0972 {
0973     return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
0974 }
0975 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK         0xff000000
0976 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT        24
0977 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
0978 {
0979     return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
0980 }
0981 
0982 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
0983 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK           0x000000ff
0984 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT          0
0985 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
0986 {
0987     return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
0988 }
0989 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK           0x0000ff00
0990 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT          8
0991 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
0992 {
0993     return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
0994 }
0995 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK        0x00ff0000
0996 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT       16
0997 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
0998 {
0999     return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
1000 }
1001 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK        0xff000000
1002 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT       24
1003 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
1004 {
1005     return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
1006 }
1007 
1008 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
1009 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK    0x0000ffff
1010 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT   0
1011 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
1012 {
1013     return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
1014 }
1015 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK    0xffff0000
1016 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT   16
1017 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
1018 {
1019     return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
1020 }
1021 
1022 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
1023 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN            0x00000001
1024 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN            0x00000002
1025 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK   0x00000300
1026 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT  8
1027 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
1028 {
1029     return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
1030 }
1031 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK   0x00000c00
1032 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT  10
1033 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
1034 {
1035     return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
1036 }
1037 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
1038 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT    12
1039 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1040 {
1041     return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
1042 }
1043 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
1044 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT    14
1045 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1046 {
1047     return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
1048 }
1049 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK   0x00030000
1050 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT  16
1051 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
1052 {
1053     return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
1054 }
1055 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK   0x000c0000
1056 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT  18
1057 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
1058 {
1059     return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
1060 }
1061 
1062 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
1063 
1064 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
1065 
1066 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
1067 
1068 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
1069 
1070 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
1071 
1072 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
1073 
1074 static inline uint32_t __offset_LM(uint32_t idx)
1075 {
1076     switch (idx) {
1077         case 0: return (mdp5_cfg->lm.base[0]);
1078         case 1: return (mdp5_cfg->lm.base[1]);
1079         case 2: return (mdp5_cfg->lm.base[2]);
1080         case 3: return (mdp5_cfg->lm.base[3]);
1081         case 4: return (mdp5_cfg->lm.base[4]);
1082         case 5: return (mdp5_cfg->lm.base[5]);
1083         default: return INVALID_IDX(idx);
1084     }
1085 }
1086 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1087 
1088 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1089 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA         0x00000002
1090 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA         0x00000004
1091 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA         0x00000008
1092 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA         0x00000010
1093 #define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA         0x00000020
1094 #define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA         0x00000040
1095 #define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA         0x00000080
1096 #define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT        0x80000000
1097 
1098 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
1099 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK               0xffff0000
1100 #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT              16
1101 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
1102 {
1103     return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
1104 }
1105 #define MDP5_LM_OUT_SIZE_WIDTH__MASK                0x0000ffff
1106 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT               0
1107 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
1108 {
1109     return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
1110 }
1111 
1112 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
1113 
1114 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
1115 
1116 static inline uint32_t __offset_BLEND(uint32_t idx)
1117 {
1118     switch (idx) {
1119         case 0: return 0x00000020;
1120         case 1: return 0x00000050;
1121         case 2: return 0x00000080;
1122         case 3: return 0x000000b0;
1123         case 4: return 0x00000230;
1124         case 5: return 0x00000260;
1125         case 6: return 0x00000290;
1126         default: return INVALID_IDX(idx);
1127     }
1128 }
1129 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1130 
1131 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1132 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK            0x00000003
1133 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT           0
1134 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
1135 {
1136     return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
1137 }
1138 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA          0x00000004
1139 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA          0x00000008
1140 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA          0x00000010
1141 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN          0x00000020
1142 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK            0x00000300
1143 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT           8
1144 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
1145 {
1146     return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
1147 }
1148 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA          0x00000400
1149 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA          0x00000800
1150 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA          0x00001000
1151 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN          0x00002000
1152 
1153 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
1154 
1155 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
1156 
1157 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
1158 
1159 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
1160 
1161 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
1162 
1163 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
1164 
1165 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
1166 
1167 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
1168 
1169 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
1170 
1171 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
1172 
1173 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
1174 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK         0x0000ffff
1175 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT            0
1176 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1177 {
1178     return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1179 }
1180 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK         0xffff0000
1181 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT            16
1182 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1183 {
1184     return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1185 }
1186 
1187 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1188 #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK             0x0000ffff
1189 #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT            0
1190 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1191 {
1192     return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1193 }
1194 #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK             0xffff0000
1195 #define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT            16
1196 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1197 {
1198     return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1199 }
1200 
1201 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1202 #define MDP5_LM_CURSOR_XY_SRC_X__MASK               0x0000ffff
1203 #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT              0
1204 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1205 {
1206     return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1207 }
1208 #define MDP5_LM_CURSOR_XY_SRC_Y__MASK               0xffff0000
1209 #define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT              16
1210 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1211 {
1212     return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1213 }
1214 
1215 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1216 #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK          0x0000ffff
1217 #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT         0
1218 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1219 {
1220     return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1221 }
1222 
1223 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1224 #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK          0x00000007
1225 #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT         0
1226 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1227 {
1228     return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1229 }
1230 
1231 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1232 
1233 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1234 #define MDP5_LM_CURSOR_START_XY_X_START__MASK           0x0000ffff
1235 #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT          0
1236 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1237 {
1238     return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1239 }
1240 #define MDP5_LM_CURSOR_START_XY_Y_START__MASK           0xffff0000
1241 #define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT          16
1242 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1243 {
1244     return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1245 }
1246 
1247 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1248 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN            0x00000001
1249 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK   0x00000006
1250 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT  1
1251 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1252 {
1253     return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1254 }
1255 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN     0x00000008
1256 
1257 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1258 
1259 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1260 
1261 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1262 
1263 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1264 
1265 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1266 
1267 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1268 
1269 static inline uint32_t __offset_DSPP(uint32_t idx)
1270 {
1271     switch (idx) {
1272         case 0: return (mdp5_cfg->dspp.base[0]);
1273         case 1: return (mdp5_cfg->dspp.base[1]);
1274         case 2: return (mdp5_cfg->dspp.base[2]);
1275         case 3: return (mdp5_cfg->dspp.base[3]);
1276         default: return INVALID_IDX(idx);
1277     }
1278 }
1279 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1280 
1281 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1282 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN                0x00000001
1283 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK         0x0000000e
1284 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT            1
1285 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1286 {
1287     return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1288 }
1289 #define MDP5_DSPP_OP_MODE_PCC_EN                0x00000010
1290 #define MDP5_DSPP_OP_MODE_DITHER_EN             0x00000100
1291 #define MDP5_DSPP_OP_MODE_HIST_EN               0x00010000
1292 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR                0x00020000
1293 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN               0x00080000
1294 #define MDP5_DSPP_OP_MODE_PA_EN                 0x00100000
1295 #define MDP5_DSPP_OP_MODE_GAMUT_EN              0x00800000
1296 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER               0x01000000
1297 
1298 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1299 
1300 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1301 
1302 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1303 
1304 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1305 
1306 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1307 
1308 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1309 
1310 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1311 
1312 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1313 
1314 static inline uint32_t __offset_PP(uint32_t idx)
1315 {
1316     switch (idx) {
1317         case 0: return (mdp5_cfg->pp.base[0]);
1318         case 1: return (mdp5_cfg->pp.base[1]);
1319         case 2: return (mdp5_cfg->pp.base[2]);
1320         case 3: return (mdp5_cfg->pp.base[3]);
1321         default: return INVALID_IDX(idx);
1322     }
1323 }
1324 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1325 
1326 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1327 
1328 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1329 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK           0x0007ffff
1330 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT          0
1331 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1332 {
1333     return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1334 }
1335 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN            0x00080000
1336 #define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN             0x00100000
1337 
1338 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1339 
1340 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1341 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK           0x0000ffff
1342 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT          0
1343 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1344 {
1345     return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1346 }
1347 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK          0xffff0000
1348 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT         16
1349 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1350 {
1351     return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1352 }
1353 
1354 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1355 
1356 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1357 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK          0x0000ffff
1358 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT         0
1359 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1360 {
1361     return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1362 }
1363 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK         0xffff0000
1364 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT        16
1365 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1366 {
1367     return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1368 }
1369 
1370 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1371 #define MDP5_PP_SYNC_THRESH_START__MASK             0x0000ffff
1372 #define MDP5_PP_SYNC_THRESH_START__SHIFT            0
1373 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1374 {
1375     return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1376 }
1377 #define MDP5_PP_SYNC_THRESH_CONTINUE__MASK          0xffff0000
1378 #define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT         16
1379 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1380 {
1381     return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1382 }
1383 
1384 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1385 
1386 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1387 
1388 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1389 
1390 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1391 
1392 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1393 
1394 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1395 
1396 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1397 
1398 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1399 
1400 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1401 
1402 static inline uint32_t __offset_WB(uint32_t idx)
1403 {
1404     switch (idx) {
1405 #if 0  /* TEMPORARY until patch that adds wb.base[] is merged */
1406         case 0: return (mdp5_cfg->wb.base[0]);
1407         case 1: return (mdp5_cfg->wb.base[1]);
1408         case 2: return (mdp5_cfg->wb.base[2]);
1409         case 3: return (mdp5_cfg->wb.base[3]);
1410         case 4: return (mdp5_cfg->wb.base[4]);
1411 #endif
1412         default: return INVALID_IDX(idx);
1413     }
1414 }
1415 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1416 
1417 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1418 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK          0x00000003
1419 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT         0
1420 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
1421 {
1422     return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
1423 }
1424 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK          0x0000000c
1425 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT         2
1426 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
1427 {
1428     return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
1429 }
1430 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK          0x00000030
1431 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT         4
1432 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
1433 {
1434     return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
1435 }
1436 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK          0x000000c0
1437 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT         6
1438 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
1439 {
1440     return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
1441 }
1442 #define MDP5_WB_DST_FORMAT_DSTC3_EN             0x00000100
1443 #define MDP5_WB_DST_FORMAT_DST_BPP__MASK            0x00000600
1444 #define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT           9
1445 static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
1446 {
1447     return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
1448 }
1449 #define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK         0x00003000
1450 #define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT            12
1451 static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
1452 {
1453     return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
1454 }
1455 #define MDP5_WB_DST_FORMAT_DST_ALPHA_X              0x00004000
1456 #define MDP5_WB_DST_FORMAT_PACK_TIGHT               0x00020000
1457 #define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB           0x00040000
1458 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK           0x00180000
1459 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT          19
1460 static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
1461 {
1462     return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
1463 }
1464 #define MDP5_WB_DST_FORMAT_DST_DITHER_EN            0x00400000
1465 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK        0x03800000
1466 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT       23
1467 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
1468 {
1469     return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
1470 }
1471 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK        0x3c000000
1472 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT       26
1473 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
1474 {
1475     return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
1476 }
1477 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK           0xc0000000
1478 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT          30
1479 static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
1480 {
1481     return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
1482 }
1483 
1484 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
1485 #define MDP5_WB_DST_OP_MODE_BWC_ENC_EN              0x00000001
1486 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK            0x00000006
1487 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT           1
1488 static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
1489 {
1490     return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
1491 }
1492 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK            0x00000010
1493 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT           4
1494 static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
1495 {
1496     return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
1497 }
1498 #define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK          0x00000020
1499 #define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT         5
1500 static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
1501 {
1502     return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
1503 }
1504 #define MDP5_WB_DST_OP_MODE_ROT_EN              0x00000040
1505 #define MDP5_WB_DST_OP_MODE_CSC_EN              0x00000100
1506 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK       0x00000200
1507 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT      9
1508 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
1509 {
1510     return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
1511 }
1512 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK       0x00000400
1513 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT      10
1514 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
1515 {
1516     return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
1517 }
1518 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN        0x00000800
1519 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK  0x00001000
1520 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
1521 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
1522 {
1523     return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
1524 }
1525 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK  0x00002000
1526 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
1527 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
1528 {
1529     return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
1530 }
1531 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK  0x00004000
1532 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
1533 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
1534 {
1535     return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
1536 }
1537 
1538 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
1539 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK         0x00000003
1540 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT        0
1541 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
1542 {
1543     return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
1544 }
1545 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK         0x00000300
1546 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT        8
1547 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
1548 {
1549     return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
1550 }
1551 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK         0x00030000
1552 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT        16
1553 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
1554 {
1555     return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
1556 }
1557 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK         0x03000000
1558 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT        24
1559 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
1560 {
1561     return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
1562 }
1563 
1564 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
1565 
1566 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
1567 
1568 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
1569 
1570 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
1571 
1572 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
1573 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK         0x0000ffff
1574 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT        0
1575 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
1576 {
1577     return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
1578 }
1579 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK         0xffff0000
1580 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT        16
1581 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
1582 {
1583     return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
1584 }
1585 
1586 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
1587 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK         0x0000ffff
1588 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT        0
1589 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
1590 {
1591     return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
1592 }
1593 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK         0xffff0000
1594 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT        16
1595 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
1596 {
1597     return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
1598 }
1599 
1600 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
1601 
1602 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
1603 
1604 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
1605 
1606 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
1607 
1608 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
1609 
1610 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
1611 
1612 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
1613 
1614 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
1615 
1616 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
1617 
1618 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
1619 
1620 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
1621 
1622 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
1623 #define MDP5_WB_OUT_SIZE_DST_W__MASK                0x0000ffff
1624 #define MDP5_WB_OUT_SIZE_DST_W__SHIFT               0
1625 static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
1626 {
1627     return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
1628 }
1629 #define MDP5_WB_OUT_SIZE_DST_H__MASK                0xffff0000
1630 #define MDP5_WB_OUT_SIZE_DST_H__SHIFT               16
1631 static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
1632 {
1633     return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
1634 }
1635 
1636 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
1637 
1638 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
1639 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK       0x00001fff
1640 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT      0
1641 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
1642 {
1643     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
1644 }
1645 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK       0x1fff0000
1646 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT      16
1647 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
1648 {
1649     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
1650 }
1651 
1652 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
1653 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK       0x00001fff
1654 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT      0
1655 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
1656 {
1657     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
1658 }
1659 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK       0x1fff0000
1660 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT      16
1661 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
1662 {
1663     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
1664 }
1665 
1666 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
1667 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK       0x00001fff
1668 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT      0
1669 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
1670 {
1671     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
1672 }
1673 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK       0x1fff0000
1674 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT      16
1675 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
1676 {
1677     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
1678 }
1679 
1680 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
1681 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK       0x00001fff
1682 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT      0
1683 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
1684 {
1685     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
1686 }
1687 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK       0x1fff0000
1688 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT      16
1689 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
1690 {
1691     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
1692 }
1693 
1694 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
1695 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK       0x00001fff
1696 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT      0
1697 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
1698 {
1699     return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
1700 }
1701 
1702 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1703 
1704 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1705 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK        0x000000ff
1706 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT       0
1707 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
1708 {
1709     return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
1710 }
1711 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK         0x0000ff00
1712 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT        8
1713 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
1714 {
1715     return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
1716 }
1717 
1718 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1719 
1720 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1721 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK       0x000000ff
1722 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT      0
1723 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
1724 {
1725     return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
1726 }
1727 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK        0x0000ff00
1728 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT       8
1729 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
1730 {
1731     return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
1732 }
1733 
1734 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1735 
1736 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1737 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK        0x000001ff
1738 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT       0
1739 static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
1740 {
1741     return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
1742 }
1743 
1744 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1745 
1746 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1747 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK       0x000001ff
1748 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT      0
1749 static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
1750 {
1751     return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
1752 }
1753 
1754 static inline uint32_t __offset_INTF(uint32_t idx)
1755 {
1756     switch (idx) {
1757         case 0: return (mdp5_cfg->intf.base[0]);
1758         case 1: return (mdp5_cfg->intf.base[1]);
1759         case 2: return (mdp5_cfg->intf.base[2]);
1760         case 3: return (mdp5_cfg->intf.base[3]);
1761         case 4: return (mdp5_cfg->intf.base[4]);
1762         default: return INVALID_IDX(idx);
1763     }
1764 }
1765 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1766 
1767 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1768 
1769 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1770 
1771 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1772 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK            0x0000ffff
1773 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT           0
1774 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1775 {
1776     return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1777 }
1778 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK            0xffff0000
1779 #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT           16
1780 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1781 {
1782     return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1783 }
1784 
1785 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1786 
1787 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1788 
1789 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1790 
1791 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1792 
1793 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1794 
1795 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1796 
1797 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1798 
1799 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1800 
1801 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1802 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK            0x7fffffff
1803 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT           0
1804 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1805 {
1806     return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1807 }
1808 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE      0x80000000
1809 
1810 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1811 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK            0x7fffffff
1812 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT           0
1813 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1814 {
1815     return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1816 }
1817 
1818 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1819 
1820 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1821 
1822 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1823 #define MDP5_INTF_DISPLAY_HCTL_START__MASK          0x0000ffff
1824 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT         0
1825 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1826 {
1827     return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1828 }
1829 #define MDP5_INTF_DISPLAY_HCTL_END__MASK            0xffff0000
1830 #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT           16
1831 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1832 {
1833     return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1834 }
1835 
1836 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1837 #define MDP5_INTF_ACTIVE_HCTL_START__MASK           0x00007fff
1838 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT          0
1839 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1840 {
1841     return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1842 }
1843 #define MDP5_INTF_ACTIVE_HCTL_END__MASK             0x7fff0000
1844 #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT            16
1845 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1846 {
1847     return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1848 }
1849 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE           0x80000000
1850 
1851 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1852 
1853 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1854 
1855 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1856 
1857 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1858 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW            0x00000001
1859 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW            0x00000002
1860 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW          0x00000004
1861 
1862 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1863 
1864 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1865 
1866 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1867 
1868 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1869 
1870 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1871 
1872 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1873 
1874 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1875 
1876 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1877 
1878 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1879 
1880 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1881 
1882 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1883 
1884 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1885 
1886 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1887 
1888 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1889 
1890 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1891 
1892 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1893 
1894 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1895 
1896 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1897 
1898 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1899 
1900 static inline uint32_t __offset_AD(uint32_t idx)
1901 {
1902     switch (idx) {
1903         case 0: return (mdp5_cfg->ad.base[0]);
1904         case 1: return (mdp5_cfg->ad.base[1]);
1905         default: return INVALID_IDX(idx);
1906     }
1907 }
1908 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1909 
1910 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1911 
1912 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1913 
1914 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1915 
1916 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1917 
1918 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1919 
1920 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1921 
1922 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1923 
1924 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1925 
1926 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1927 
1928 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1929 
1930 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1931 
1932 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1933 
1934 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1935 
1936 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1937 
1938 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1939 
1940 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1941 
1942 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1943 
1944 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1945 
1946 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1947 
1948 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1949 
1950 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1951 
1952 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1953 
1954 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1955 
1956 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1957 
1958 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1959 
1960 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1961 
1962 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1963 
1964 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1965 
1966 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1967 
1968 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1969 
1970 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1971 
1972 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1973 
1974 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1975 
1976 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1977 
1978 
1979 #endif /* MDP5_XML */
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