disp/mdp4/mdp4_lvds_pll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 Red Hat
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  */
0006
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009
0010 #include "mdp4_kms.h"
0011
0012 struct mdp4_lvds_pll {
0013     struct clk_hw pll_hw;
0014     struct drm_device *dev;
0015     unsigned long pixclk;
0016 };
0017 #define to_mdp4_lvds_pll(x) container_of(x, struct mdp4_lvds_pll, pll_hw)
0018
0019 static struct mdp4_kms *get_kms(struct mdp4_lvds_pll *lvds_pll)
0020 {
0021     struct msm_drm_private *priv = lvds_pll->dev->dev_private;
0022     return to_mdp4_kms(to_mdp_kms(priv->kms));
0023 }
0024
0025 struct pll_rate {
0026     unsigned long rate;
0027     struct {
0028         uint32_t val;
0029         uint32_t reg;
0030     } conf[32];
0031 };
0032
0033 /* NOTE: keep sorted highest freq to lowest: */
0034 static const struct pll_rate freqtbl[] = {
0035     { 72000000, {
0036         { 0x8f, REG_MDP4_LVDS_PHY_PLL_CTRL_1 },
0037         { 0x30, REG_MDP4_LVDS_PHY_PLL_CTRL_2 },
0038         { 0xc6, REG_MDP4_LVDS_PHY_PLL_CTRL_3 },
0039         { 0x10, REG_MDP4_LVDS_PHY_PLL_CTRL_5 },
0040         { 0x07, REG_MDP4_LVDS_PHY_PLL_CTRL_6 },
0041         { 0x62, REG_MDP4_LVDS_PHY_PLL_CTRL_7 },
0042         { 0x41, REG_MDP4_LVDS_PHY_PLL_CTRL_8 },
0043         { 0x0d, REG_MDP4_LVDS_PHY_PLL_CTRL_9 },
0044         { 0, 0 } }
0045     },
0046 };
0047
0048 static const struct pll_rate *find_rate(unsigned long rate)
0049 {
0050     int i;
0051     for (i = 1; i < ARRAY_SIZE(freqtbl); i++)
0052         if (rate > freqtbl[i].rate)
0053             return &freqtbl[i-1];
0054     return &freqtbl[i-1];
0055 }
0056
0057 static int mpd4_lvds_pll_enable(struct clk_hw *hw)
0058 {
0059     struct mdp4_lvds_pll *lvds_pll = to_mdp4_lvds_pll(hw);
0060     struct mdp4_kms *mdp4_kms = get_kms(lvds_pll);
0061     const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk);
0062     int i;
0063
0064     DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate);
0065
0066     if (WARN_ON(!pll_rate))
0067         return -EINVAL;
0068
0069     mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33);
0070
0071     for (i = 0; pll_rate->conf[i].reg; i++)
0072         mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val);
0073
0074     mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01);
0075
0076     /* Wait until LVDS PLL is locked and ready */
0077     while (!mdp4_read(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_LOCKED))
0078         cpu_relax();
0079
0080     return 0;
0081 }
0082
0083 static void mpd4_lvds_pll_disable(struct clk_hw *hw)
0084 {
0085     struct mdp4_lvds_pll *lvds_pll = to_mdp4_lvds_pll(hw);
0086     struct mdp4_kms *mdp4_kms = get_kms(lvds_pll);
0087
0088     DBG("");
0089
0090     mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0);
0091     mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0);
0092 }
0093
0094 static unsigned long mpd4_lvds_pll_recalc_rate(struct clk_hw *hw,
0095                 unsigned long parent_rate)
0096 {
0097     struct mdp4_lvds_pll *lvds_pll = to_mdp4_lvds_pll(hw);
0098     return lvds_pll->pixclk;
0099 }
0100
0101 static long mpd4_lvds_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0102         unsigned long *parent_rate)
0103 {
0104     const struct pll_rate *pll_rate = find_rate(rate);
0105     return pll_rate->rate;
0106 }
0107
0108 static int mpd4_lvds_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0109         unsigned long parent_rate)
0110 {
0111     struct mdp4_lvds_pll *lvds_pll = to_mdp4_lvds_pll(hw);
0112     lvds_pll->pixclk = rate;
0113     return 0;
0114 }
0115
0116
0117 static const struct clk_ops mpd4_lvds_pll_ops = {
0118     .enable = mpd4_lvds_pll_enable,
0119     .disable = mpd4_lvds_pll_disable,
0120     .recalc_rate = mpd4_lvds_pll_recalc_rate,
0121     .round_rate = mpd4_lvds_pll_round_rate,
0122     .set_rate = mpd4_lvds_pll_set_rate,
0123 };
0124
0125 static const char *mpd4_lvds_pll_parents[] = {
0126     "pxo",
0127 };
0128
0129 static struct clk_init_data pll_init = {
0130     .name = "mpd4_lvds_pll",
0131     .ops = &mpd4_lvds_pll_ops,
0132     .parent_names = mpd4_lvds_pll_parents,
0133     .num_parents = ARRAY_SIZE(mpd4_lvds_pll_parents),
0134 };
0135
0136 struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
0137 {
0138     struct mdp4_lvds_pll *lvds_pll;
0139     struct clk *clk;
0140     int ret;
0141
0142     lvds_pll = devm_kzalloc(dev->dev, sizeof(*lvds_pll), GFP_KERNEL);
0143     if (!lvds_pll) {
0144         ret = -ENOMEM;
0145         goto fail;
0146     }
0147
0148     lvds_pll->dev = dev;
0149
0150     lvds_pll->pll_hw.init = &pll_init;
0151     clk = devm_clk_register(dev->dev, &lvds_pll->pll_hw);
0152     if (IS_ERR(clk)) {
0153         ret = PTR_ERR(clk);
0154         goto fail;
0155     }
0156
0157     return clk;
0158
0159 fail:
0160     return ERR_PTR(ret);
0161 }