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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 Red Hat
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  */
0006 
0007 #include <linux/delay.h>
0008 
0009 #include <drm/drm_vblank.h>
0010 
0011 #include "msm_drv.h"
0012 #include "msm_gem.h"
0013 #include "msm_mmu.h"
0014 #include "mdp4_kms.h"
0015 
0016 static int mdp4_hw_init(struct msm_kms *kms)
0017 {
0018     struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
0019     struct drm_device *dev = mdp4_kms->dev;
0020     u32 dmap_cfg, vg_cfg;
0021     unsigned long clk;
0022 
0023     pm_runtime_get_sync(dev->dev);
0024 
0025     if (mdp4_kms->rev > 1) {
0026         mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
0027         mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
0028     }
0029 
0030     mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
0031 
0032     /* max read pending cmd config, 3 pending requests: */
0033     mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
0034 
0035     clk = clk_get_rate(mdp4_kms->clk);
0036 
0037     if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
0038         dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
0039         vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
0040     } else {
0041         dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
0042         vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
0043     }
0044 
0045     DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
0046 
0047     mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
0048     mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
0049 
0050     mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
0051     mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
0052     mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
0053     mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
0054 
0055     if (mdp4_kms->rev >= 2)
0056         mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
0057     mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
0058 
0059     /* disable CSC matrix / YUV by default: */
0060     mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
0061     mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
0062     mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
0063     mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
0064     mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
0065     mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
0066 
0067     if (mdp4_kms->rev > 1)
0068         mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
0069 
0070     pm_runtime_put_sync(dev->dev);
0071 
0072     return 0;
0073 }
0074 
0075 static void mdp4_enable_commit(struct msm_kms *kms)
0076 {
0077     struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
0078     mdp4_enable(mdp4_kms);
0079 }
0080 
0081 static void mdp4_disable_commit(struct msm_kms *kms)
0082 {
0083     struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
0084     mdp4_disable(mdp4_kms);
0085 }
0086 
0087 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
0088 {
0089 }
0090 
0091 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
0092 {
0093     /* TODO */
0094 }
0095 
0096 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
0097 {
0098     struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
0099     struct drm_crtc *crtc;
0100 
0101     for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
0102         mdp4_crtc_wait_for_commit_done(crtc);
0103 }
0104 
0105 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
0106 {
0107 }
0108 
0109 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
0110         struct drm_encoder *encoder)
0111 {
0112     /* if we had >1 encoder, we'd need something more clever: */
0113     switch (encoder->encoder_type) {
0114     case DRM_MODE_ENCODER_TMDS:
0115         return mdp4_dtv_round_pixclk(encoder, rate);
0116     case DRM_MODE_ENCODER_LVDS:
0117     case DRM_MODE_ENCODER_DSI:
0118     default:
0119         return rate;
0120     }
0121 }
0122 
0123 static void mdp4_destroy(struct msm_kms *kms)
0124 {
0125     struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
0126     struct device *dev = mdp4_kms->dev->dev;
0127     struct msm_gem_address_space *aspace = kms->aspace;
0128 
0129     if (mdp4_kms->blank_cursor_iova)
0130         msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
0131     drm_gem_object_put(mdp4_kms->blank_cursor_bo);
0132 
0133     if (aspace) {
0134         aspace->mmu->funcs->detach(aspace->mmu);
0135         msm_gem_address_space_put(aspace);
0136     }
0137 
0138     if (mdp4_kms->rpm_enabled)
0139         pm_runtime_disable(dev);
0140 
0141     mdp_kms_destroy(&mdp4_kms->base);
0142 
0143     kfree(mdp4_kms);
0144 }
0145 
0146 static const struct mdp_kms_funcs kms_funcs = {
0147     .base = {
0148         .hw_init         = mdp4_hw_init,
0149         .irq_preinstall  = mdp4_irq_preinstall,
0150         .irq_postinstall = mdp4_irq_postinstall,
0151         .irq_uninstall   = mdp4_irq_uninstall,
0152         .irq             = mdp4_irq,
0153         .enable_vblank   = mdp4_enable_vblank,
0154         .disable_vblank  = mdp4_disable_vblank,
0155         .enable_commit   = mdp4_enable_commit,
0156         .disable_commit  = mdp4_disable_commit,
0157         .prepare_commit  = mdp4_prepare_commit,
0158         .flush_commit    = mdp4_flush_commit,
0159         .wait_flush      = mdp4_wait_flush,
0160         .complete_commit = mdp4_complete_commit,
0161         .get_format      = mdp_get_format,
0162         .round_pixclk    = mdp4_round_pixclk,
0163         .destroy         = mdp4_destroy,
0164     },
0165     .set_irqmask         = mdp4_set_irqmask,
0166 };
0167 
0168 int mdp4_disable(struct mdp4_kms *mdp4_kms)
0169 {
0170     DBG("");
0171 
0172     clk_disable_unprepare(mdp4_kms->clk);
0173     clk_disable_unprepare(mdp4_kms->pclk);
0174     clk_disable_unprepare(mdp4_kms->lut_clk);
0175     clk_disable_unprepare(mdp4_kms->axi_clk);
0176 
0177     return 0;
0178 }
0179 
0180 int mdp4_enable(struct mdp4_kms *mdp4_kms)
0181 {
0182     DBG("");
0183 
0184     clk_prepare_enable(mdp4_kms->clk);
0185     clk_prepare_enable(mdp4_kms->pclk);
0186     clk_prepare_enable(mdp4_kms->lut_clk);
0187     clk_prepare_enable(mdp4_kms->axi_clk);
0188 
0189     return 0;
0190 }
0191 
0192 
0193 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
0194                   int intf_type)
0195 {
0196     struct drm_device *dev = mdp4_kms->dev;
0197     struct msm_drm_private *priv = dev->dev_private;
0198     struct drm_encoder *encoder;
0199     struct drm_connector *connector;
0200     struct device_node *panel_node;
0201     int dsi_id;
0202     int ret;
0203 
0204     switch (intf_type) {
0205     case DRM_MODE_ENCODER_LVDS:
0206         /*
0207          * bail out early if there is no panel node (no need to
0208          * initialize LCDC encoder and LVDS connector)
0209          */
0210         panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
0211         if (!panel_node)
0212             return 0;
0213 
0214         encoder = mdp4_lcdc_encoder_init(dev, panel_node);
0215         if (IS_ERR(encoder)) {
0216             DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
0217             of_node_put(panel_node);
0218             return PTR_ERR(encoder);
0219         }
0220 
0221         /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
0222         encoder->possible_crtcs = 1 << DMA_P;
0223 
0224         connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
0225         if (IS_ERR(connector)) {
0226             DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
0227             of_node_put(panel_node);
0228             return PTR_ERR(connector);
0229         }
0230 
0231         break;
0232     case DRM_MODE_ENCODER_TMDS:
0233         encoder = mdp4_dtv_encoder_init(dev);
0234         if (IS_ERR(encoder)) {
0235             DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
0236             return PTR_ERR(encoder);
0237         }
0238 
0239         /* DTV can be hooked to DMA_E: */
0240         encoder->possible_crtcs = 1 << 1;
0241 
0242         if (priv->hdmi) {
0243             /* Construct bridge/connector for HDMI: */
0244             ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
0245             if (ret) {
0246                 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
0247                 return ret;
0248             }
0249         }
0250 
0251         break;
0252     case DRM_MODE_ENCODER_DSI:
0253         /* only DSI1 supported for now */
0254         dsi_id = 0;
0255 
0256         if (!priv->dsi[dsi_id])
0257             break;
0258 
0259         encoder = mdp4_dsi_encoder_init(dev);
0260         if (IS_ERR(encoder)) {
0261             ret = PTR_ERR(encoder);
0262             DRM_DEV_ERROR(dev->dev,
0263                 "failed to construct DSI encoder: %d\n", ret);
0264             return ret;
0265         }
0266 
0267         /* TODO: Add DMA_S later? */
0268         encoder->possible_crtcs = 1 << DMA_P;
0269 
0270         ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
0271         if (ret) {
0272             DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
0273                 ret);
0274             return ret;
0275         }
0276 
0277         break;
0278     default:
0279         DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
0280         return -EINVAL;
0281     }
0282 
0283     return 0;
0284 }
0285 
0286 static int modeset_init(struct mdp4_kms *mdp4_kms)
0287 {
0288     struct drm_device *dev = mdp4_kms->dev;
0289     struct msm_drm_private *priv = dev->dev_private;
0290     struct drm_plane *plane;
0291     struct drm_crtc *crtc;
0292     int i, ret;
0293     static const enum mdp4_pipe rgb_planes[] = {
0294         RGB1, RGB2,
0295     };
0296     static const enum mdp4_pipe vg_planes[] = {
0297         VG1, VG2,
0298     };
0299     static const enum mdp4_dma mdp4_crtcs[] = {
0300         DMA_P, DMA_E,
0301     };
0302     static const char * const mdp4_crtc_names[] = {
0303         "DMA_P", "DMA_E",
0304     };
0305     static const int mdp4_intfs[] = {
0306         DRM_MODE_ENCODER_LVDS,
0307         DRM_MODE_ENCODER_DSI,
0308         DRM_MODE_ENCODER_TMDS,
0309     };
0310 
0311     /* construct non-private planes: */
0312     for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
0313         plane = mdp4_plane_init(dev, vg_planes[i], false);
0314         if (IS_ERR(plane)) {
0315             DRM_DEV_ERROR(dev->dev,
0316                 "failed to construct plane for VG%d\n", i + 1);
0317             ret = PTR_ERR(plane);
0318             goto fail;
0319         }
0320     }
0321 
0322     for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
0323         plane = mdp4_plane_init(dev, rgb_planes[i], true);
0324         if (IS_ERR(plane)) {
0325             DRM_DEV_ERROR(dev->dev,
0326                 "failed to construct plane for RGB%d\n", i + 1);
0327             ret = PTR_ERR(plane);
0328             goto fail;
0329         }
0330 
0331         crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
0332                 mdp4_crtcs[i]);
0333         if (IS_ERR(crtc)) {
0334             DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
0335                 mdp4_crtc_names[i]);
0336             ret = PTR_ERR(crtc);
0337             goto fail;
0338         }
0339 
0340         priv->crtcs[priv->num_crtcs++] = crtc;
0341     }
0342 
0343     /*
0344      * we currently set up two relatively fixed paths:
0345      *
0346      * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
0347      *          or
0348      * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
0349      *
0350      * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
0351      */
0352 
0353     for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
0354         ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
0355         if (ret) {
0356             DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
0357                 i, ret);
0358             goto fail;
0359         }
0360     }
0361 
0362     return 0;
0363 
0364 fail:
0365     return ret;
0366 }
0367 
0368 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
0369                  u32 *major, u32 *minor)
0370 {
0371     struct drm_device *dev = mdp4_kms->dev;
0372     u32 version;
0373 
0374     mdp4_enable(mdp4_kms);
0375     version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
0376     mdp4_disable(mdp4_kms);
0377 
0378     *major = FIELD(version, MDP4_VERSION_MAJOR);
0379     *minor = FIELD(version, MDP4_VERSION_MINOR);
0380 
0381     DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
0382 }
0383 
0384 static int mdp4_kms_init(struct drm_device *dev)
0385 {
0386     struct platform_device *pdev = to_platform_device(dev->dev);
0387     struct msm_drm_private *priv = dev->dev_private;
0388     struct mdp4_kms *mdp4_kms;
0389     struct msm_kms *kms = NULL;
0390     struct iommu_domain *iommu;
0391     struct msm_gem_address_space *aspace;
0392     int irq, ret;
0393     u32 major, minor;
0394     unsigned long max_clk;
0395 
0396     /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
0397     max_clk = 266667000;
0398 
0399     mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
0400     if (!mdp4_kms) {
0401         DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n");
0402         return -ENOMEM;
0403     }
0404 
0405     ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
0406     if (ret) {
0407         DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
0408         goto fail;
0409     }
0410 
0411     priv->kms = &mdp4_kms->base.base;
0412     kms = priv->kms;
0413 
0414     mdp4_kms->dev = dev;
0415 
0416     mdp4_kms->mmio = msm_ioremap(pdev, NULL);
0417     if (IS_ERR(mdp4_kms->mmio)) {
0418         ret = PTR_ERR(mdp4_kms->mmio);
0419         goto fail;
0420     }
0421 
0422     irq = platform_get_irq(pdev, 0);
0423     if (irq < 0) {
0424         ret = irq;
0425         DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
0426         goto fail;
0427     }
0428 
0429     kms->irq = irq;
0430 
0431     /* NOTE: driver for this regulator still missing upstream.. use
0432      * _get_exclusive() and ignore the error if it does not exist
0433      * (and hope that the bootloader left it on for us)
0434      */
0435     mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
0436     if (IS_ERR(mdp4_kms->vdd))
0437         mdp4_kms->vdd = NULL;
0438 
0439     if (mdp4_kms->vdd) {
0440         ret = regulator_enable(mdp4_kms->vdd);
0441         if (ret) {
0442             DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
0443             goto fail;
0444         }
0445     }
0446 
0447     mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
0448     if (IS_ERR(mdp4_kms->clk)) {
0449         DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n");
0450         ret = PTR_ERR(mdp4_kms->clk);
0451         goto fail;
0452     }
0453 
0454     mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
0455     if (IS_ERR(mdp4_kms->pclk))
0456         mdp4_kms->pclk = NULL;
0457 
0458     mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
0459     if (IS_ERR(mdp4_kms->axi_clk)) {
0460         DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n");
0461         ret = PTR_ERR(mdp4_kms->axi_clk);
0462         goto fail;
0463     }
0464 
0465     clk_set_rate(mdp4_kms->clk, max_clk);
0466 
0467     read_mdp_hw_revision(mdp4_kms, &major, &minor);
0468 
0469     if (major != 4) {
0470         DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
0471                   major, minor);
0472         ret = -ENXIO;
0473         goto fail;
0474     }
0475 
0476     mdp4_kms->rev = minor;
0477 
0478     if (mdp4_kms->rev >= 2) {
0479         mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
0480         if (IS_ERR(mdp4_kms->lut_clk)) {
0481             DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
0482             ret = PTR_ERR(mdp4_kms->lut_clk);
0483             goto fail;
0484         }
0485         clk_set_rate(mdp4_kms->lut_clk, max_clk);
0486     }
0487 
0488     pm_runtime_enable(dev->dev);
0489     mdp4_kms->rpm_enabled = true;
0490 
0491     /* make sure things are off before attaching iommu (bootloader could
0492      * have left things on, in which case we'll start getting faults if
0493      * we don't disable):
0494      */
0495     mdp4_enable(mdp4_kms);
0496     mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
0497     mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
0498     mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
0499     mdp4_disable(mdp4_kms);
0500     mdelay(16);
0501 
0502     iommu = iommu_domain_alloc(pdev->dev.bus);
0503     if (iommu) {
0504         struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, iommu);
0505 
0506         aspace  = msm_gem_address_space_create(mmu,
0507             "mdp4", 0x1000, 0x100000000 - 0x1000);
0508 
0509         if (IS_ERR(aspace)) {
0510             if (!IS_ERR(mmu))
0511                 mmu->funcs->destroy(mmu);
0512             ret = PTR_ERR(aspace);
0513             goto fail;
0514         }
0515 
0516         kms->aspace = aspace;
0517     } else {
0518         DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
0519                 "contig buffers for scanout\n");
0520         aspace = NULL;
0521     }
0522 
0523     ret = modeset_init(mdp4_kms);
0524     if (ret) {
0525         DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
0526         goto fail;
0527     }
0528 
0529     mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
0530     if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
0531         ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
0532         DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
0533         mdp4_kms->blank_cursor_bo = NULL;
0534         goto fail;
0535     }
0536 
0537     ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
0538             &mdp4_kms->blank_cursor_iova);
0539     if (ret) {
0540         DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
0541         goto fail;
0542     }
0543 
0544     dev->mode_config.min_width = 0;
0545     dev->mode_config.min_height = 0;
0546     dev->mode_config.max_width = 2048;
0547     dev->mode_config.max_height = 2048;
0548 
0549     return 0;
0550 
0551 fail:
0552     if (kms)
0553         mdp4_destroy(kms);
0554 
0555     return ret;
0556 }
0557 
0558 static const struct dev_pm_ops mdp4_pm_ops = {
0559     .prepare = msm_pm_prepare,
0560     .complete = msm_pm_complete,
0561 };
0562 
0563 static int mdp4_probe(struct platform_device *pdev)
0564 {
0565     return msm_drv_probe(&pdev->dev, mdp4_kms_init);
0566 }
0567 
0568 static int mdp4_remove(struct platform_device *pdev)
0569 {
0570     component_master_del(&pdev->dev, &msm_drm_ops);
0571 
0572     return 0;
0573 }
0574 
0575 static const struct of_device_id mdp4_dt_match[] = {
0576     { .compatible = "qcom,mdp4" },
0577     { /* sentinel */ }
0578 };
0579 MODULE_DEVICE_TABLE(of, mdp4_dt_match);
0580 
0581 static struct platform_driver mdp4_platform_driver = {
0582     .probe      = mdp4_probe,
0583     .remove     = mdp4_remove,
0584     .shutdown   = msm_drv_shutdown,
0585     .driver     = {
0586         .name   = "mdp4",
0587         .of_match_table = mdp4_dt_match,
0588         .pm     = &mdp4_pm_ops,
0589     },
0590 };
0591 
0592 void __init msm_mdp4_register(void)
0593 {
0594     platform_driver_register(&mdp4_platform_driver);
0595 }
0596 
0597 void __exit msm_mdp4_unregister(void)
0598 {
0599     platform_driver_unregister(&mdp4_platform_driver);
0600 }
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