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0001 #ifndef MDP4_XML
0002 #define MDP4_XML
0003 
0004 /* Autogenerated file, DO NOT EDIT manually!
0005 
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009 
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
0024 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
0025 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
0026 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
0027 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
0028 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)
0029 
0030 Copyright (C) 2013-2021 by the following authors:
0031 - Rob Clark <robdclark@gmail.com> (robclark)
0032 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0033 
0034 Permission is hereby granted, free of charge, to any person obtaining
0035 a copy of this software and associated documentation files (the
0036 "Software"), to deal in the Software without restriction, including
0037 without limitation the rights to use, copy, modify, merge, publish,
0038 distribute, sublicense, and/or sell copies of the Software, and to
0039 permit persons to whom the Software is furnished to do so, subject to
0040 the following conditions:
0041 
0042 The above copyright notice and this permission notice (including the
0043 next paragraph) shall be included in all copies or substantial
0044 portions of the Software.
0045 
0046 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0047 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0048 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0049 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0050 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0051 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0052 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0053 */
0054 
0055 
0056 enum mdp4_pipe {
0057     VG1 = 0,
0058     VG2 = 1,
0059     RGB1 = 2,
0060     RGB2 = 3,
0061     RGB3 = 4,
0062     VG3 = 5,
0063     VG4 = 6,
0064 };
0065 
0066 enum mdp4_mixer {
0067     MIXER0 = 0,
0068     MIXER1 = 1,
0069     MIXER2 = 2,
0070 };
0071 
0072 enum mdp4_intf {
0073     INTF_LCDC_DTV = 0,
0074     INTF_DSI_VIDEO = 1,
0075     INTF_DSI_CMD = 2,
0076     INTF_EBI2_TV = 3,
0077 };
0078 
0079 enum mdp4_cursor_format {
0080     CURSOR_ARGB = 1,
0081     CURSOR_XRGB = 2,
0082 };
0083 
0084 enum mdp4_frame_format {
0085     FRAME_LINEAR = 0,
0086     FRAME_TILE_ARGB_4X4 = 1,
0087     FRAME_TILE_YCBCR_420 = 2,
0088 };
0089 
0090 enum mdp4_scale_unit {
0091     SCALE_FIR = 0,
0092     SCALE_MN_PHASE = 1,
0093     SCALE_PIXEL_RPT = 2,
0094 };
0095 
0096 enum mdp4_dma {
0097     DMA_P = 0,
0098     DMA_S = 1,
0099     DMA_E = 2,
0100 };
0101 
0102 #define MDP4_IRQ_OVERLAY0_DONE                  0x00000001
0103 #define MDP4_IRQ_OVERLAY1_DONE                  0x00000002
0104 #define MDP4_IRQ_DMA_S_DONE                 0x00000004
0105 #define MDP4_IRQ_DMA_E_DONE                 0x00000008
0106 #define MDP4_IRQ_DMA_P_DONE                 0x00000010
0107 #define MDP4_IRQ_VG1_HISTOGRAM                  0x00000020
0108 #define MDP4_IRQ_VG2_HISTOGRAM                  0x00000040
0109 #define MDP4_IRQ_PRIMARY_VSYNC                  0x00000080
0110 #define MDP4_IRQ_PRIMARY_INTF_UDERRUN               0x00000100
0111 #define MDP4_IRQ_EXTERNAL_VSYNC                 0x00000200
0112 #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN              0x00000400
0113 #define MDP4_IRQ_PRIMARY_RDPTR                  0x00000800
0114 #define MDP4_IRQ_DMA_P_HISTOGRAM                0x00020000
0115 #define MDP4_IRQ_DMA_S_HISTOGRAM                0x04000000
0116 #define MDP4_IRQ_OVERLAY2_DONE                  0x40000000
0117 #define REG_MDP4_VERSION                    0x00000000
0118 #define MDP4_VERSION_MINOR__MASK                0x00ff0000
0119 #define MDP4_VERSION_MINOR__SHIFT               16
0120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
0121 {
0122     return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
0123 }
0124 #define MDP4_VERSION_MAJOR__MASK                0xff000000
0125 #define MDP4_VERSION_MAJOR__SHIFT               24
0126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
0127 {
0128     return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
0129 }
0130 
0131 #define REG_MDP4_OVLP0_KICK                 0x00000004
0132 
0133 #define REG_MDP4_OVLP1_KICK                 0x00000008
0134 
0135 #define REG_MDP4_OVLP2_KICK                 0x000000d0
0136 
0137 #define REG_MDP4_DMA_P_KICK                 0x0000000c
0138 
0139 #define REG_MDP4_DMA_S_KICK                 0x00000010
0140 
0141 #define REG_MDP4_DMA_E_KICK                 0x00000014
0142 
0143 #define REG_MDP4_DISP_STATUS                    0x00000018
0144 
0145 #define REG_MDP4_DISP_INTF_SEL                  0x00000038
0146 #define MDP4_DISP_INTF_SEL_PRIM__MASK               0x00000003
0147 #define MDP4_DISP_INTF_SEL_PRIM__SHIFT              0
0148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
0149 {
0150     return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
0151 }
0152 #define MDP4_DISP_INTF_SEL_SEC__MASK                0x0000000c
0153 #define MDP4_DISP_INTF_SEL_SEC__SHIFT               2
0154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
0155 {
0156     return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
0157 }
0158 #define MDP4_DISP_INTF_SEL_EXT__MASK                0x00000030
0159 #define MDP4_DISP_INTF_SEL_EXT__SHIFT               4
0160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
0161 {
0162     return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
0163 }
0164 #define MDP4_DISP_INTF_SEL_DSI_VIDEO                0x00000040
0165 #define MDP4_DISP_INTF_SEL_DSI_CMD              0x00000080
0166 
0167 #define REG_MDP4_RESET_STATUS                   0x0000003c
0168 
0169 #define REG_MDP4_READ_CNFG                  0x0000004c
0170 
0171 #define REG_MDP4_INTR_ENABLE                    0x00000050
0172 
0173 #define REG_MDP4_INTR_STATUS                    0x00000054
0174 
0175 #define REG_MDP4_INTR_CLEAR                 0x00000058
0176 
0177 #define REG_MDP4_EBI2_LCD0                  0x00000060
0178 
0179 #define REG_MDP4_EBI2_LCD1                  0x00000064
0180 
0181 #define REG_MDP4_PORTMAP_MODE                   0x00000070
0182 
0183 #define REG_MDP4_CS_CONTROLLER0                 0x000000c0
0184 
0185 #define REG_MDP4_CS_CONTROLLER1                 0x000000c4
0186 
0187 #define REG_MDP4_LAYERMIXER2_IN_CFG             0x000100f0
0188 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK         0x00000007
0189 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT            0
0190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
0191 {
0192     return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
0193 }
0194 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1            0x00000008
0195 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK         0x00000070
0196 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT            4
0197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
0198 {
0199     return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
0200 }
0201 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1            0x00000080
0202 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK         0x00000700
0203 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT            8
0204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
0205 {
0206     return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
0207 }
0208 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1            0x00000800
0209 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK         0x00007000
0210 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT            12
0211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
0212 {
0213     return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
0214 }
0215 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1            0x00008000
0216 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK         0x00070000
0217 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT            16
0218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
0219 {
0220     return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
0221 }
0222 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1            0x00080000
0223 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK         0x00700000
0224 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT            20
0225 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
0226 {
0227     return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
0228 }
0229 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1            0x00800000
0230 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK         0x07000000
0231 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT            24
0232 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
0233 {
0234     return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
0235 }
0236 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1            0x08000000
0237 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK         0x70000000
0238 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT            28
0239 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
0240 {
0241     return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
0242 }
0243 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1            0x80000000
0244 
0245 #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD        0x000100fc
0246 
0247 #define REG_MDP4_LAYERMIXER_IN_CFG              0x00010100
0248 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK          0x00000007
0249 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT         0
0250 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
0251 {
0252     return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
0253 }
0254 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1         0x00000008
0255 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK          0x00000070
0256 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT         4
0257 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
0258 {
0259     return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
0260 }
0261 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1         0x00000080
0262 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK          0x00000700
0263 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT         8
0264 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
0265 {
0266     return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
0267 }
0268 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1         0x00000800
0269 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK          0x00007000
0270 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT         12
0271 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
0272 {
0273     return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
0274 }
0275 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1         0x00008000
0276 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK          0x00070000
0277 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT         16
0278 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
0279 {
0280     return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
0281 }
0282 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1         0x00080000
0283 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK          0x00700000
0284 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT         20
0285 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
0286 {
0287     return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
0288 }
0289 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1         0x00800000
0290 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK          0x07000000
0291 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT         24
0292 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
0293 {
0294     return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
0295 }
0296 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1         0x08000000
0297 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK          0x70000000
0298 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT         28
0299 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
0300 {
0301     return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
0302 }
0303 #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1         0x80000000
0304 
0305 #define REG_MDP4_VG2_SRC_FORMAT                 0x00030050
0306 
0307 #define REG_MDP4_VG2_CONST_COLOR                0x00031008
0308 
0309 #define REG_MDP4_OVERLAY_FLUSH                  0x00018000
0310 #define MDP4_OVERLAY_FLUSH_OVLP0                0x00000001
0311 #define MDP4_OVERLAY_FLUSH_OVLP1                0x00000002
0312 #define MDP4_OVERLAY_FLUSH_VG1                  0x00000004
0313 #define MDP4_OVERLAY_FLUSH_VG2                  0x00000008
0314 #define MDP4_OVERLAY_FLUSH_RGB1                 0x00000010
0315 #define MDP4_OVERLAY_FLUSH_RGB2                 0x00000020
0316 
0317 static inline uint32_t __offset_OVLP(uint32_t idx)
0318 {
0319     switch (idx) {
0320         case 0: return 0x00010000;
0321         case 1: return 0x00018000;
0322         case 2: return 0x00088000;
0323         default: return INVALID_IDX(idx);
0324     }
0325 }
0326 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
0327 
0328 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
0329 
0330 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
0331 #define MDP4_OVLP_SIZE_HEIGHT__MASK             0xffff0000
0332 #define MDP4_OVLP_SIZE_HEIGHT__SHIFT                16
0333 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
0334 {
0335     return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
0336 }
0337 #define MDP4_OVLP_SIZE_WIDTH__MASK              0x0000ffff
0338 #define MDP4_OVLP_SIZE_WIDTH__SHIFT             0
0339 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
0340 {
0341     return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
0342 }
0343 
0344 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
0345 
0346 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
0347 
0348 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
0349 
0350 static inline uint32_t __offset_STAGE(uint32_t idx)
0351 {
0352     switch (idx) {
0353         case 0: return 0x00000104;
0354         case 1: return 0x00000124;
0355         case 2: return 0x00000144;
0356         case 3: return 0x00000160;
0357         default: return INVALID_IDX(idx);
0358     }
0359 }
0360 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
0361 
0362 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
0363 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK           0x00000003
0364 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT          0
0365 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
0366 {
0367     return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
0368 }
0369 #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA             0x00000004
0370 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA             0x00000008
0371 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK           0x00000030
0372 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT          4
0373 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
0374 {
0375     return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
0376 }
0377 #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA             0x00000040
0378 #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA             0x00000080
0379 #define MDP4_OVLP_STAGE_OP_FG_TRANSP                0x00000100
0380 #define MDP4_OVLP_STAGE_OP_BG_TRANSP                0x00000200
0381 
0382 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
0383 
0384 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
0385 
0386 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
0387 
0388 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
0389 
0390 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
0391 
0392 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
0393 
0394 static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
0395 {
0396     switch (idx) {
0397         case 0: return 0x00001004;
0398         case 1: return 0x00001404;
0399         case 2: return 0x00001804;
0400         case 3: return 0x00001b84;
0401         default: return INVALID_IDX(idx);
0402     }
0403 }
0404 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
0405 
0406 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
0407 #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA            0x00000001
0408 
0409 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
0410 
0411 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
0412 
0413 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
0414 
0415 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
0416 
0417 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
0418 
0419 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
0420 
0421 
0422 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
0423 
0424 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
0425 
0426 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
0427 
0428 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
0429 
0430 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
0431 
0432 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
0433 
0434 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
0435 
0436 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
0437 
0438 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
0439 
0440 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
0441 
0442 #define REG_MDP4_DMA_P_OP_MODE                  0x00090070
0443 
0444 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
0445 
0446 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
0447 
0448 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
0449 
0450 #define REG_MDP4_DMA_S_OP_MODE                  0x000a0028
0451 
0452 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
0453 
0454 static inline uint32_t __offset_DMA(enum mdp4_dma idx)
0455 {
0456     switch (idx) {
0457         case DMA_P: return 0x00090000;
0458         case DMA_S: return 0x000a0000;
0459         case DMA_E: return 0x000b0000;
0460         default: return INVALID_IDX(idx);
0461     }
0462 }
0463 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
0464 
0465 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
0466 #define MDP4_DMA_CONFIG_G_BPC__MASK             0x00000003
0467 #define MDP4_DMA_CONFIG_G_BPC__SHIFT                0
0468 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
0469 {
0470     return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
0471 }
0472 #define MDP4_DMA_CONFIG_B_BPC__MASK             0x0000000c
0473 #define MDP4_DMA_CONFIG_B_BPC__SHIFT                2
0474 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
0475 {
0476     return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
0477 }
0478 #define MDP4_DMA_CONFIG_R_BPC__MASK             0x00000030
0479 #define MDP4_DMA_CONFIG_R_BPC__SHIFT                4
0480 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
0481 {
0482     return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
0483 }
0484 #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB              0x00000080
0485 #define MDP4_DMA_CONFIG_PACK__MASK              0x0000ff00
0486 #define MDP4_DMA_CONFIG_PACK__SHIFT             8
0487 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
0488 {
0489     return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
0490 }
0491 #define MDP4_DMA_CONFIG_DEFLKR_EN               0x01000000
0492 #define MDP4_DMA_CONFIG_DITHER_EN               0x01000000
0493 
0494 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
0495 #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK              0xffff0000
0496 #define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT             16
0497 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
0498 {
0499     return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
0500 }
0501 #define MDP4_DMA_SRC_SIZE_WIDTH__MASK               0x0000ffff
0502 #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT              0
0503 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
0504 {
0505     return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
0506 }
0507 
0508 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
0509 
0510 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
0511 
0512 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
0513 #define MDP4_DMA_DST_SIZE_HEIGHT__MASK              0xffff0000
0514 #define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT             16
0515 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
0516 {
0517     return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
0518 }
0519 #define MDP4_DMA_DST_SIZE_WIDTH__MASK               0x0000ffff
0520 #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT              0
0521 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
0522 {
0523     return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
0524 }
0525 
0526 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
0527 #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK            0x0000007f
0528 #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT           0
0529 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
0530 {
0531     return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
0532 }
0533 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK           0x007f0000
0534 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT          16
0535 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
0536 {
0537     return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
0538 }
0539 
0540 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
0541 
0542 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
0543 #define MDP4_DMA_CURSOR_POS_X__MASK             0x0000ffff
0544 #define MDP4_DMA_CURSOR_POS_X__SHIFT                0
0545 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
0546 {
0547     return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
0548 }
0549 #define MDP4_DMA_CURSOR_POS_Y__MASK             0xffff0000
0550 #define MDP4_DMA_CURSOR_POS_Y__SHIFT                16
0551 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
0552 {
0553     return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
0554 }
0555 
0556 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
0557 #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN          0x00000001
0558 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK       0x00000006
0559 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT      1
0560 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
0561 {
0562     return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
0563 }
0564 #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN          0x00000008
0565 
0566 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
0567 
0568 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
0569 
0570 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
0571 
0572 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
0573 
0574 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
0575 
0576 
0577 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
0578 
0579 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
0580 
0581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
0582 
0583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
0584 
0585 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
0586 
0587 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
0588 
0589 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
0590 
0591 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
0592 
0593 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
0594 
0595 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
0596 
0597 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
0598 
0599 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
0600 #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK             0xffff0000
0601 #define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT            16
0602 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
0603 {
0604     return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
0605 }
0606 #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK              0x0000ffff
0607 #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT             0
0608 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
0609 {
0610     return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
0611 }
0612 
0613 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
0614 #define MDP4_PIPE_SRC_XY_Y__MASK                0xffff0000
0615 #define MDP4_PIPE_SRC_XY_Y__SHIFT               16
0616 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
0617 {
0618     return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
0619 }
0620 #define MDP4_PIPE_SRC_XY_X__MASK                0x0000ffff
0621 #define MDP4_PIPE_SRC_XY_X__SHIFT               0
0622 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
0623 {
0624     return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
0625 }
0626 
0627 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
0628 #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK             0xffff0000
0629 #define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT            16
0630 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
0631 {
0632     return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
0633 }
0634 #define MDP4_PIPE_DST_SIZE_WIDTH__MASK              0x0000ffff
0635 #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT             0
0636 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
0637 {
0638     return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
0639 }
0640 
0641 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
0642 #define MDP4_PIPE_DST_XY_Y__MASK                0xffff0000
0643 #define MDP4_PIPE_DST_XY_Y__SHIFT               16
0644 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
0645 {
0646     return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
0647 }
0648 #define MDP4_PIPE_DST_XY_X__MASK                0x0000ffff
0649 #define MDP4_PIPE_DST_XY_X__SHIFT               0
0650 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
0651 {
0652     return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
0653 }
0654 
0655 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
0656 
0657 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
0658 
0659 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
0660 
0661 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
0662 
0663 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
0664 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK             0x0000ffff
0665 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT            0
0666 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
0667 {
0668     return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
0669 }
0670 #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK             0xffff0000
0671 #define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT            16
0672 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
0673 {
0674     return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
0675 }
0676 
0677 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
0678 #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK             0x0000ffff
0679 #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT            0
0680 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
0681 {
0682     return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
0683 }
0684 #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK             0xffff0000
0685 #define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT            16
0686 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
0687 {
0688     return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
0689 }
0690 
0691 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
0692 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK        0xffff0000
0693 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT       16
0694 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
0695 {
0696     return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
0697 }
0698 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK         0x0000ffff
0699 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT        0
0700 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
0701 {
0702     return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
0703 }
0704 
0705 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
0706 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK            0x00000003
0707 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT           0
0708 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
0709 {
0710     return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
0711 }
0712 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK            0x0000000c
0713 #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT           2
0714 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
0715 {
0716     return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
0717 }
0718 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK            0x00000030
0719 #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT           4
0720 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
0721 {
0722     return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
0723 }
0724 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK            0x000000c0
0725 #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT           6
0726 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
0727 {
0728     return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
0729 }
0730 #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE           0x00000100
0731 #define MDP4_PIPE_SRC_FORMAT_CPP__MASK              0x00000600
0732 #define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT             9
0733 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
0734 {
0735     return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
0736 }
0737 #define MDP4_PIPE_SRC_FORMAT_ROTATED_90             0x00001000
0738 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK         0x00006000
0739 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT        13
0740 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
0741 {
0742     return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
0743 }
0744 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT           0x00020000
0745 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB           0x00040000
0746 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK         0x00180000
0747 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT        19
0748 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
0749 {
0750     return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
0751 }
0752 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL             0x00400000
0753 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK          0x0c000000
0754 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT         26
0755 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
0756 {
0757     return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
0758 }
0759 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK         0x60000000
0760 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT        29
0761 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
0762 {
0763     return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
0764 }
0765 
0766 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
0767 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK            0x000000ff
0768 #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT           0
0769 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
0770 {
0771     return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
0772 }
0773 #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK            0x0000ff00
0774 #define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT           8
0775 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
0776 {
0777     return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
0778 }
0779 #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK            0x00ff0000
0780 #define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT           16
0781 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
0782 {
0783     return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
0784 }
0785 #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK            0xff000000
0786 #define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT           24
0787 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
0788 {
0789     return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
0790 }
0791 
0792 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
0793 #define MDP4_PIPE_OP_MODE_SCALEX_EN             0x00000001
0794 #define MDP4_PIPE_OP_MODE_SCALEY_EN             0x00000002
0795 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK         0x0000000c
0796 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT        2
0797 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
0798 {
0799     return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
0800 }
0801 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK         0x00000030
0802 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT        4
0803 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
0804 {
0805     return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
0806 }
0807 #define MDP4_PIPE_OP_MODE_SRC_YCBCR             0x00000200
0808 #define MDP4_PIPE_OP_MODE_DST_YCBCR             0x00000400
0809 #define MDP4_PIPE_OP_MODE_CSC_EN                0x00000800
0810 #define MDP4_PIPE_OP_MODE_FLIP_LR               0x00002000
0811 #define MDP4_PIPE_OP_MODE_FLIP_UD               0x00004000
0812 #define MDP4_PIPE_OP_MODE_DITHER_EN             0x00008000
0813 #define MDP4_PIPE_OP_MODE_IGC_LUT_EN                0x00010000
0814 #define MDP4_PIPE_OP_MODE_DEINT_EN              0x00040000
0815 #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF             0x00080000
0816 
0817 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
0818 
0819 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
0820 
0821 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
0822 
0823 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
0824 
0825 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
0826 
0827 
0828 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
0829 
0830 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
0831 
0832 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
0833 
0834 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
0835 
0836 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
0837 
0838 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
0839 
0840 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
0841 
0842 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
0843 
0844 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
0845 
0846 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
0847 
0848 #define REG_MDP4_LCDC                       0x000c0000
0849 
0850 #define REG_MDP4_LCDC_ENABLE                    0x000c0000
0851 
0852 #define REG_MDP4_LCDC_HSYNC_CTRL                0x000c0004
0853 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK           0x0000ffff
0854 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT          0
0855 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
0856 {
0857     return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
0858 }
0859 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK           0xffff0000
0860 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT          16
0861 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
0862 {
0863     return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
0864 }
0865 
0866 #define REG_MDP4_LCDC_VSYNC_PERIOD              0x000c0008
0867 
0868 #define REG_MDP4_LCDC_VSYNC_LEN                 0x000c000c
0869 
0870 #define REG_MDP4_LCDC_DISPLAY_HCTRL             0x000c0010
0871 #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK         0x0000ffff
0872 #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT            0
0873 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
0874 {
0875     return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
0876 }
0877 #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK           0xffff0000
0878 #define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT          16
0879 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
0880 {
0881     return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
0882 }
0883 
0884 #define REG_MDP4_LCDC_DISPLAY_VSTART                0x000c0014
0885 
0886 #define REG_MDP4_LCDC_DISPLAY_VEND              0x000c0018
0887 
0888 #define REG_MDP4_LCDC_ACTIVE_HCTL               0x000c001c
0889 #define MDP4_LCDC_ACTIVE_HCTL_START__MASK           0x00007fff
0890 #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT          0
0891 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
0892 {
0893     return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
0894 }
0895 #define MDP4_LCDC_ACTIVE_HCTL_END__MASK             0x7fff0000
0896 #define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT            16
0897 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
0898 {
0899     return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
0900 }
0901 #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X            0x80000000
0902 
0903 #define REG_MDP4_LCDC_ACTIVE_VSTART             0x000c0020
0904 
0905 #define REG_MDP4_LCDC_ACTIVE_VEND               0x000c0024
0906 
0907 #define REG_MDP4_LCDC_BORDER_CLR                0x000c0028
0908 
0909 #define REG_MDP4_LCDC_UNDERFLOW_CLR             0x000c002c
0910 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK         0x00ffffff
0911 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT            0
0912 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
0913 {
0914     return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
0915 }
0916 #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY         0x80000000
0917 
0918 #define REG_MDP4_LCDC_HSYNC_SKEW                0x000c0030
0919 
0920 #define REG_MDP4_LCDC_TEST_CNTL                 0x000c0034
0921 
0922 #define REG_MDP4_LCDC_CTRL_POLARITY             0x000c0038
0923 #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW           0x00000001
0924 #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW           0x00000002
0925 #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW         0x00000004
0926 
0927 #define REG_MDP4_LCDC_LVDS_INTF_CTL             0x000c2000
0928 #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL            0x00000004
0929 #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT             0x00000008
0930 #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP             0x00000010
0931 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT         0x00000020
0932 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT         0x00000040
0933 #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE              0x00000080
0934 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN       0x00000100
0935 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN       0x00000200
0936 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN       0x00000400
0937 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN       0x00000800
0938 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN       0x00001000
0939 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN       0x00002000
0940 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN       0x00004000
0941 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN       0x00008000
0942 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN         0x00010000
0943 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN         0x00020000
0944 
0945 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
0946 
0947 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
0948 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK        0x000000ff
0949 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT       0
0950 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)
0951 {
0952     return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK;
0953 }
0954 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK        0x0000ff00
0955 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT       8
0956 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)
0957 {
0958     return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK;
0959 }
0960 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK        0x00ff0000
0961 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT       16
0962 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)
0963 {
0964     return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK;
0965 }
0966 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK        0xff000000
0967 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT       24
0968 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)
0969 {
0970     return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK;
0971 }
0972 
0973 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; }
0974 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK        0x000000ff
0975 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT       0
0976 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)
0977 {
0978     return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK;
0979 }
0980 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK        0x0000ff00
0981 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT       8
0982 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)
0983 {
0984     return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK;
0985 }
0986 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK        0x00ff0000
0987 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT       16
0988 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)
0989 {
0990     return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK;
0991 }
0992 
0993 #define REG_MDP4_LCDC_LVDS_PHY_RESET                0x000c2034
0994 
0995 #define REG_MDP4_LVDS_PHY_PLL_CTRL_0                0x000c3000
0996 
0997 #define REG_MDP4_LVDS_PHY_PLL_CTRL_1                0x000c3004
0998 
0999 #define REG_MDP4_LVDS_PHY_PLL_CTRL_2                0x000c3008
1000 
1001 #define REG_MDP4_LVDS_PHY_PLL_CTRL_3                0x000c300c
1002 
1003 #define REG_MDP4_LVDS_PHY_PLL_CTRL_5                0x000c3014
1004 
1005 #define REG_MDP4_LVDS_PHY_PLL_CTRL_6                0x000c3018
1006 
1007 #define REG_MDP4_LVDS_PHY_PLL_CTRL_7                0x000c301c
1008 
1009 #define REG_MDP4_LVDS_PHY_PLL_CTRL_8                0x000c3020
1010 
1011 #define REG_MDP4_LVDS_PHY_PLL_CTRL_9                0x000c3024
1012 
1013 #define REG_MDP4_LVDS_PHY_PLL_LOCKED                0x000c3080
1014 
1015 #define REG_MDP4_LVDS_PHY_CFG2                  0x000c3108
1016 
1017 #define REG_MDP4_LVDS_PHY_CFG0                  0x000c3100
1018 #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE          0x00000010
1019 #define MDP4_LVDS_PHY_CFG0_CHANNEL0             0x00000040
1020 #define MDP4_LVDS_PHY_CFG0_CHANNEL1             0x00000080
1021 
1022 #define REG_MDP4_DTV                        0x000d0000
1023 
1024 #define REG_MDP4_DTV_ENABLE                 0x000d0000
1025 
1026 #define REG_MDP4_DTV_HSYNC_CTRL                 0x000d0004
1027 #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK            0x0000ffff
1028 #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT           0
1029 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
1030 {
1031     return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
1032 }
1033 #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK            0xffff0000
1034 #define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT           16
1035 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
1036 {
1037     return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
1038 }
1039 
1040 #define REG_MDP4_DTV_VSYNC_PERIOD               0x000d0008
1041 
1042 #define REG_MDP4_DTV_VSYNC_LEN                  0x000d000c
1043 
1044 #define REG_MDP4_DTV_DISPLAY_HCTRL              0x000d0018
1045 #define MDP4_DTV_DISPLAY_HCTRL_START__MASK          0x0000ffff
1046 #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT         0
1047 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
1048 {
1049     return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
1050 }
1051 #define MDP4_DTV_DISPLAY_HCTRL_END__MASK            0xffff0000
1052 #define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT           16
1053 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
1054 {
1055     return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
1056 }
1057 
1058 #define REG_MDP4_DTV_DISPLAY_VSTART             0x000d001c
1059 
1060 #define REG_MDP4_DTV_DISPLAY_VEND               0x000d0020
1061 
1062 #define REG_MDP4_DTV_ACTIVE_HCTL                0x000d002c
1063 #define MDP4_DTV_ACTIVE_HCTL_START__MASK            0x00007fff
1064 #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT           0
1065 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
1066 {
1067     return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
1068 }
1069 #define MDP4_DTV_ACTIVE_HCTL_END__MASK              0x7fff0000
1070 #define MDP4_DTV_ACTIVE_HCTL_END__SHIFT             16
1071 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
1072 {
1073     return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
1074 }
1075 #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X         0x80000000
1076 
1077 #define REG_MDP4_DTV_ACTIVE_VSTART              0x000d0030
1078 
1079 #define REG_MDP4_DTV_ACTIVE_VEND                0x000d0038
1080 
1081 #define REG_MDP4_DTV_BORDER_CLR                 0x000d0040
1082 
1083 #define REG_MDP4_DTV_UNDERFLOW_CLR              0x000d0044
1084 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK          0x00ffffff
1085 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT         0
1086 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
1087 {
1088     return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
1089 }
1090 #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY          0x80000000
1091 
1092 #define REG_MDP4_DTV_HSYNC_SKEW                 0x000d0048
1093 
1094 #define REG_MDP4_DTV_TEST_CNTL                  0x000d004c
1095 
1096 #define REG_MDP4_DTV_CTRL_POLARITY              0x000d0050
1097 #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW            0x00000001
1098 #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW            0x00000002
1099 #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW          0x00000004
1100 
1101 #define REG_MDP4_DSI                        0x000e0000
1102 
1103 #define REG_MDP4_DSI_ENABLE                 0x000e0000
1104 
1105 #define REG_MDP4_DSI_HSYNC_CTRL                 0x000e0004
1106 #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK            0x0000ffff
1107 #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT           0
1108 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
1109 {
1110     return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
1111 }
1112 #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK            0xffff0000
1113 #define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT           16
1114 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
1115 {
1116     return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
1117 }
1118 
1119 #define REG_MDP4_DSI_VSYNC_PERIOD               0x000e0008
1120 
1121 #define REG_MDP4_DSI_VSYNC_LEN                  0x000e000c
1122 
1123 #define REG_MDP4_DSI_DISPLAY_HCTRL              0x000e0010
1124 #define MDP4_DSI_DISPLAY_HCTRL_START__MASK          0x0000ffff
1125 #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT         0
1126 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
1127 {
1128     return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
1129 }
1130 #define MDP4_DSI_DISPLAY_HCTRL_END__MASK            0xffff0000
1131 #define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT           16
1132 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
1133 {
1134     return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
1135 }
1136 
1137 #define REG_MDP4_DSI_DISPLAY_VSTART             0x000e0014
1138 
1139 #define REG_MDP4_DSI_DISPLAY_VEND               0x000e0018
1140 
1141 #define REG_MDP4_DSI_ACTIVE_HCTL                0x000e001c
1142 #define MDP4_DSI_ACTIVE_HCTL_START__MASK            0x00007fff
1143 #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT           0
1144 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
1145 {
1146     return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
1147 }
1148 #define MDP4_DSI_ACTIVE_HCTL_END__MASK              0x7fff0000
1149 #define MDP4_DSI_ACTIVE_HCTL_END__SHIFT             16
1150 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
1151 {
1152     return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
1153 }
1154 #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X         0x80000000
1155 
1156 #define REG_MDP4_DSI_ACTIVE_VSTART              0x000e0020
1157 
1158 #define REG_MDP4_DSI_ACTIVE_VEND                0x000e0024
1159 
1160 #define REG_MDP4_DSI_BORDER_CLR                 0x000e0028
1161 
1162 #define REG_MDP4_DSI_UNDERFLOW_CLR              0x000e002c
1163 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK          0x00ffffff
1164 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT         0
1165 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
1166 {
1167     return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
1168 }
1169 #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY          0x80000000
1170 
1171 #define REG_MDP4_DSI_HSYNC_SKEW                 0x000e0030
1172 
1173 #define REG_MDP4_DSI_TEST_CNTL                  0x000e0034
1174 
1175 #define REG_MDP4_DSI_CTRL_POLARITY              0x000e0038
1176 #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW            0x00000001
1177 #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW            0x00000002
1178 #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW          0x00000004
1179 
1180 
1181 #endif /* MDP4_XML */
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