disp/dpu1/dpu_rm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef __DPU_RM_H__
0007 #define __DPU_RM_H__
0008
0009 #include <linux/list.h>
0010
0011 #include "msm_kms.h"
0012 #include "dpu_hw_top.h"
0013
0014 struct dpu_global_state;
0015
0016 /**
0017  * struct dpu_rm - DPU dynamic hardware resource manager
0018  * @pingpong_blks: array of pingpong hardware resources
0019  * @mixer_blks: array of layer mixer hardware resources
0020  * @ctl_blks: array of ctl hardware resources
0021  * @hw_intf: array of intf hardware resources
0022  * @hw_wb: array of wb hardware resources
0023  * @dspp_blks: array of dspp hardware resources
0024  */
0025 struct dpu_rm {
0026     struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
0027     struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
0028     struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
0029     struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
0030     struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
0031     struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
0032     struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
0033     struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
0034 };
0035
0036 /**
0037  * dpu_rm_init - Read hardware catalog and create reservation tracking objects
0038  *  for all HW blocks.
0039  * @rm: DPU Resource Manager handle
0040  * @cat: Pointer to hardware catalog
0041  * @mmio: mapped register io address of MDP
0042  * @Return: 0 on Success otherwise -ERROR
0043  */
0044 int dpu_rm_init(struct dpu_rm *rm,
0045         const struct dpu_mdss_cfg *cat,
0046         void __iomem *mmio);
0047
0048 /**
0049  * dpu_rm_destroy - Free all memory allocated by dpu_rm_init
0050  * @rm: DPU Resource Manager handle
0051  * @Return: 0 on Success otherwise -ERROR
0052  */
0053 int dpu_rm_destroy(struct dpu_rm *rm);
0054
0055 /**
0056  * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
0057  *  the use connections and user requirements, specified through related
0058  *  topology control properties, and reserve hardware blocks to that
0059  *  display chain.
0060  *  HW blocks can then be accessed through dpu_rm_get_* functions.
0061  *  HW Reservations should be released via dpu_rm_release_hw.
0062  * @rm: DPU Resource Manager handle
0063  * @drm_enc: DRM Encoder handle
0064  * @crtc_state: Proposed Atomic DRM CRTC State handle
0065  * @topology: Pointer to topology info for the display
0066  * @Return: 0 on Success otherwise -ERROR
0067  */
0068 int dpu_rm_reserve(struct dpu_rm *rm,
0069         struct dpu_global_state *global_state,
0070         struct drm_encoder *drm_enc,
0071         struct drm_crtc_state *crtc_state,
0072         struct msm_display_topology topology);
0073
0074 /**
0075  * dpu_rm_reserve - Given the encoder for the display chain, release any
0076  *  HW blocks previously reserved for that use case.
0077  * @rm: DPU Resource Manager handle
0078  * @enc: DRM Encoder handle
0079  * @Return: 0 on Success otherwise -ERROR
0080  */
0081 void dpu_rm_release(struct dpu_global_state *global_state,
0082         struct drm_encoder *enc);
0083
0084 /**
0085  * Get hw resources of the given type that are assigned to this encoder.
0086  */
0087 int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
0088     struct dpu_global_state *global_state, uint32_t enc_id,
0089     enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
0090
0091 /**
0092  * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
0093  * @rm: DPU Resource Manager handle
0094  * @intf_idx: INTF's index
0095  */
0096 static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
0097 {
0098     return rm->hw_intf[intf_idx - INTF_0];
0099 }
0100
0101 /**
0102  * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index.
0103  * @rm: DPU Resource Manager handle
0104  * @wb_idx: WB index
0105  */
0106 static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx)
0107 {
0108     return rm->hw_wb[wb_idx - WB_0];
0109 }
0110
0111 #endif /* __DPU_RM_H__ */
0112