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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
0004  * Copyright (C) 2013 Red Hat
0005  * Author: Rob Clark <robdclark@gmail.com>
0006  */
0007 
0008 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
0009 
0010 #include <linux/debugfs.h>
0011 #include <linux/dma-buf.h>
0012 
0013 #include <drm/drm_atomic.h>
0014 #include <drm/drm_atomic_uapi.h>
0015 #include <drm/drm_blend.h>
0016 #include <drm/drm_damage_helper.h>
0017 #include <drm/drm_framebuffer.h>
0018 #include <drm/drm_gem_atomic_helper.h>
0019 
0020 #include "msm_drv.h"
0021 #include "dpu_kms.h"
0022 #include "dpu_formats.h"
0023 #include "dpu_hw_sspp.h"
0024 #include "dpu_trace.h"
0025 #include "dpu_crtc.h"
0026 #include "dpu_vbif.h"
0027 #include "dpu_plane.h"
0028 
0029 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
0030         (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
0031 
0032 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
0033         (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
0034 
0035 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
0036 #define PHASE_STEP_SHIFT    21
0037 #define PHASE_STEP_UNIT_SCALE   ((int) (1 << PHASE_STEP_SHIFT))
0038 #define PHASE_RESIDUAL      15
0039 
0040 #define SHARP_STRENGTH_DEFAULT  32
0041 #define SHARP_EDGE_THR_DEFAULT  112
0042 #define SHARP_SMOOTH_THR_DEFAULT    8
0043 #define SHARP_NOISE_THR_DEFAULT 2
0044 
0045 #define DPU_NAME_SIZE  12
0046 
0047 #define DPU_PLANE_COLOR_FILL_FLAG   BIT(31)
0048 #define DPU_ZPOS_MAX 255
0049 
0050 /* multirect rect index */
0051 enum {
0052     R0,
0053     R1,
0054     R_MAX
0055 };
0056 
0057 /*
0058  * Default Preload Values
0059  */
0060 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
0061 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
0062 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2
0063 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4
0064 
0065 #define DEFAULT_REFRESH_RATE    60
0066 
0067 static const uint32_t qcom_compressed_supported_formats[] = {
0068     DRM_FORMAT_ABGR8888,
0069     DRM_FORMAT_ARGB8888,
0070     DRM_FORMAT_XBGR8888,
0071     DRM_FORMAT_XRGB8888,
0072     DRM_FORMAT_BGR565,
0073 
0074     DRM_FORMAT_NV12,
0075 };
0076 
0077 /**
0078  * enum dpu_plane_qos - Different qos configurations for each pipe
0079  *
0080  * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
0081  * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
0082  *  this configuration is mutually exclusive from VBLANK_CTRL.
0083  * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
0084  */
0085 enum dpu_plane_qos {
0086     DPU_PLANE_QOS_VBLANK_CTRL = BIT(0),
0087     DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
0088     DPU_PLANE_QOS_PANIC_CTRL = BIT(2),
0089 };
0090 
0091 /*
0092  * struct dpu_plane - local dpu plane structure
0093  * @aspace: address space pointer
0094  * @mplane_list: List of multirect planes of the same pipe
0095  * @catalog: Points to dpu catalog structure
0096  * @revalidate: force revalidation of all the plane properties
0097  */
0098 struct dpu_plane {
0099     struct drm_plane base;
0100 
0101     struct mutex lock;
0102 
0103     enum dpu_sspp pipe;
0104 
0105     struct dpu_hw_pipe *pipe_hw;
0106     uint32_t color_fill;
0107     bool is_error;
0108     bool is_rt_pipe;
0109     bool is_virtual;
0110     struct list_head mplane_list;
0111     const struct dpu_mdss_cfg *catalog;
0112 };
0113 
0114 static const uint64_t supported_format_modifiers[] = {
0115     DRM_FORMAT_MOD_QCOM_COMPRESSED,
0116     DRM_FORMAT_MOD_LINEAR,
0117     DRM_FORMAT_MOD_INVALID
0118 };
0119 
0120 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
0121 
0122 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
0123 {
0124     struct msm_drm_private *priv = plane->dev->dev_private;
0125 
0126     return to_dpu_kms(priv->kms);
0127 }
0128 
0129 /**
0130  * _dpu_plane_calc_bw - calculate bandwidth required for a plane
0131  * @plane: Pointer to drm plane.
0132  * @fb:   Pointer to framebuffer associated with the given plane
0133  * @pipe_cfg: Pointer to pipe configuration
0134  * Result: Updates calculated bandwidth in the plane state.
0135  * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
0136  * Prefill BW Equation: line src bytes * line_time
0137  */
0138 static void _dpu_plane_calc_bw(struct drm_plane *plane,
0139     struct drm_framebuffer *fb,
0140     struct dpu_hw_pipe_cfg *pipe_cfg)
0141 {
0142     struct dpu_plane_state *pstate;
0143     struct drm_display_mode *mode;
0144     const struct dpu_format *fmt = NULL;
0145     struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
0146     int src_width, src_height, dst_height, fps;
0147     u64 plane_prefill_bw;
0148     u64 plane_bw;
0149     u32 hw_latency_lines;
0150     u64 scale_factor;
0151     int vbp, vpw, vfp;
0152 
0153     pstate = to_dpu_plane_state(plane->state);
0154     mode = &plane->state->crtc->mode;
0155 
0156     fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
0157 
0158     src_width = drm_rect_width(&pipe_cfg->src_rect);
0159     src_height = drm_rect_height(&pipe_cfg->src_rect);
0160     dst_height = drm_rect_height(&pipe_cfg->dst_rect);
0161     fps = drm_mode_vrefresh(mode);
0162     vbp = mode->vtotal - mode->vsync_end;
0163     vpw = mode->vsync_end - mode->vsync_start;
0164     vfp = mode->vsync_start - mode->vdisplay;
0165     hw_latency_lines =  dpu_kms->catalog->perf->min_prefill_lines;
0166     scale_factor = src_height > dst_height ?
0167         mult_frac(src_height, 1, dst_height) : 1;
0168 
0169     plane_bw =
0170         src_width * mode->vtotal * fps * fmt->bpp *
0171         scale_factor;
0172 
0173     plane_prefill_bw =
0174         src_width * hw_latency_lines * fps * fmt->bpp *
0175         scale_factor * mode->vtotal;
0176 
0177     if ((vbp+vpw) > hw_latency_lines)
0178         do_div(plane_prefill_bw, (vbp+vpw));
0179     else if ((vbp+vpw+vfp) < hw_latency_lines)
0180         do_div(plane_prefill_bw, (vbp+vpw+vfp));
0181     else
0182         do_div(plane_prefill_bw, hw_latency_lines);
0183 
0184 
0185     pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
0186 }
0187 
0188 /**
0189  * _dpu_plane_calc_clk - calculate clock required for a plane
0190  * @plane: Pointer to drm plane.
0191  * @pipe_cfg: Pointer to pipe configuration
0192  * Result: Updates calculated clock in the plane state.
0193  * Clock equation: dst_w * v_total * fps * (src_h / dst_h)
0194  */
0195 static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg)
0196 {
0197     struct dpu_plane_state *pstate;
0198     struct drm_display_mode *mode;
0199     int dst_width, src_height, dst_height, fps;
0200 
0201     pstate = to_dpu_plane_state(plane->state);
0202     mode = &plane->state->crtc->mode;
0203 
0204     src_height = drm_rect_height(&pipe_cfg->src_rect);
0205     dst_width = drm_rect_width(&pipe_cfg->dst_rect);
0206     dst_height = drm_rect_height(&pipe_cfg->dst_rect);
0207     fps = drm_mode_vrefresh(mode);
0208 
0209     pstate->plane_clk =
0210         dst_width * mode->vtotal * fps;
0211 
0212     if (src_height > dst_height) {
0213         pstate->plane_clk *= src_height;
0214         do_div(pstate->plane_clk, dst_height);
0215     }
0216 }
0217 
0218 /**
0219  * _dpu_plane_calc_fill_level - calculate fill level of the given source format
0220  * @plane:      Pointer to drm plane
0221  * @fmt:        Pointer to source buffer format
0222  * @src_width:      width of source buffer
0223  * Return: fill level corresponding to the source buffer/format or 0 if error
0224  */
0225 static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
0226         const struct dpu_format *fmt, u32 src_width)
0227 {
0228     struct dpu_plane *pdpu, *tmp;
0229     struct dpu_plane_state *pstate;
0230     u32 fixed_buff_size;
0231     u32 total_fl;
0232 
0233     if (!fmt || !plane->state || !src_width || !fmt->bpp) {
0234         DPU_ERROR("invalid arguments\n");
0235         return 0;
0236     }
0237 
0238     pdpu = to_dpu_plane(plane);
0239     pstate = to_dpu_plane_state(plane->state);
0240     fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
0241 
0242     list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
0243         u32 tmp_width;
0244 
0245         if (!tmp->base.state->visible)
0246             continue;
0247         tmp_width = drm_rect_width(&tmp->base.state->src) >> 16;
0248         DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
0249                 pdpu->base.base.id, tmp->base.base.id,
0250                 src_width,
0251                 tmp_width);
0252         src_width = max_t(u32, src_width,
0253                   tmp_width);
0254     }
0255 
0256     if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
0257         if (fmt->chroma_sample == DPU_CHROMA_420) {
0258             /* NV12 */
0259             total_fl = (fixed_buff_size / 2) /
0260                 ((src_width + 32) * fmt->bpp);
0261         } else {
0262             /* non NV12 */
0263             total_fl = (fixed_buff_size / 2) * 2 /
0264                 ((src_width + 32) * fmt->bpp);
0265         }
0266     } else {
0267         if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
0268             total_fl = (fixed_buff_size / 2) * 2 /
0269                 ((src_width + 32) * fmt->bpp);
0270         } else {
0271             total_fl = (fixed_buff_size) * 2 /
0272                 ((src_width + 32) * fmt->bpp);
0273         }
0274     }
0275 
0276     DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
0277             pdpu->pipe - SSPP_VIG0,
0278             (char *)&fmt->base.pixel_format,
0279             src_width, total_fl);
0280 
0281     return total_fl;
0282 }
0283 
0284 /**
0285  * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
0286  * @plane:      Pointer to drm plane
0287  * @fb:         Pointer to framebuffer associated with the given plane
0288  * @pipe_cfg:       Pointer to pipe configuration
0289  */
0290 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
0291         struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
0292 {
0293     struct dpu_plane *pdpu = to_dpu_plane(plane);
0294     const struct dpu_format *fmt = NULL;
0295     u64 qos_lut;
0296     u32 total_fl = 0, lut_usage;
0297 
0298     if (!pdpu->is_rt_pipe) {
0299         lut_usage = DPU_QOS_LUT_USAGE_NRT;
0300     } else {
0301         fmt = dpu_get_dpu_format_ext(
0302                 fb->format->format,
0303                 fb->modifier);
0304         total_fl = _dpu_plane_calc_fill_level(plane, fmt,
0305                 drm_rect_width(&pipe_cfg->src_rect));
0306 
0307         if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
0308             lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
0309         else
0310             lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
0311     }
0312 
0313     qos_lut = _dpu_hw_get_qos_lut(
0314             &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
0315 
0316     trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
0317             (fmt) ? fmt->base.pixel_format : 0,
0318             pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
0319 
0320     DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
0321             pdpu->pipe - SSPP_VIG0,
0322             fmt ? (char *)&fmt->base.pixel_format : NULL,
0323             pdpu->is_rt_pipe, total_fl, qos_lut);
0324 
0325     pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
0326 }
0327 
0328 /**
0329  * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane
0330  * @plane:      Pointer to drm plane
0331  * @fb:         Pointer to framebuffer associated with the given plane
0332  */
0333 static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
0334         struct drm_framebuffer *fb)
0335 {
0336     struct dpu_plane *pdpu = to_dpu_plane(plane);
0337     const struct dpu_format *fmt = NULL;
0338     u32 danger_lut, safe_lut;
0339 
0340     if (!pdpu->is_rt_pipe) {
0341         danger_lut = pdpu->catalog->perf->danger_lut_tbl
0342                 [DPU_QOS_LUT_USAGE_NRT];
0343         safe_lut = pdpu->catalog->perf->safe_lut_tbl
0344                 [DPU_QOS_LUT_USAGE_NRT];
0345     } else {
0346         fmt = dpu_get_dpu_format_ext(
0347                 fb->format->format,
0348                 fb->modifier);
0349 
0350         if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
0351             danger_lut = pdpu->catalog->perf->danger_lut_tbl
0352                     [DPU_QOS_LUT_USAGE_LINEAR];
0353             safe_lut = pdpu->catalog->perf->safe_lut_tbl
0354                     [DPU_QOS_LUT_USAGE_LINEAR];
0355         } else {
0356             danger_lut = pdpu->catalog->perf->danger_lut_tbl
0357                     [DPU_QOS_LUT_USAGE_MACROTILE];
0358             safe_lut = pdpu->catalog->perf->safe_lut_tbl
0359                     [DPU_QOS_LUT_USAGE_MACROTILE];
0360         }
0361     }
0362 
0363     trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
0364             (fmt) ? fmt->base.pixel_format : 0,
0365             (fmt) ? fmt->fetch_mode : 0,
0366             danger_lut,
0367             safe_lut);
0368 
0369     DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
0370         pdpu->pipe - SSPP_VIG0,
0371         fmt ? (char *)&fmt->base.pixel_format : NULL,
0372         fmt ? fmt->fetch_mode : -1,
0373         danger_lut,
0374         safe_lut);
0375 
0376     pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
0377             danger_lut, safe_lut);
0378 }
0379 
0380 /**
0381  * _dpu_plane_set_qos_ctrl - set QoS control of the given plane
0382  * @plane:      Pointer to drm plane
0383  * @enable:     true to enable QoS control
0384  * @flags:      QoS control mode (enum dpu_plane_qos)
0385  */
0386 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
0387     bool enable, u32 flags)
0388 {
0389     struct dpu_plane *pdpu = to_dpu_plane(plane);
0390     struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
0391 
0392     memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
0393 
0394     if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
0395         pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
0396         pipe_qos_cfg.danger_vblank =
0397                 pdpu->pipe_hw->cap->sblk->danger_vblank;
0398         pipe_qos_cfg.vblank_en = enable;
0399     }
0400 
0401     if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
0402         /* this feature overrules previous VBLANK_CTRL */
0403         pipe_qos_cfg.vblank_en = false;
0404         pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
0405     }
0406 
0407     if (flags & DPU_PLANE_QOS_PANIC_CTRL)
0408         pipe_qos_cfg.danger_safe_en = enable;
0409 
0410     if (!pdpu->is_rt_pipe) {
0411         pipe_qos_cfg.vblank_en = false;
0412         pipe_qos_cfg.danger_safe_en = false;
0413     }
0414 
0415     DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
0416         pdpu->pipe - SSPP_VIG0,
0417         pipe_qos_cfg.danger_safe_en,
0418         pipe_qos_cfg.vblank_en,
0419         pipe_qos_cfg.creq_vblank,
0420         pipe_qos_cfg.danger_vblank,
0421         pdpu->is_rt_pipe);
0422 
0423     pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
0424             &pipe_qos_cfg);
0425 }
0426 
0427 /**
0428  * _dpu_plane_set_ot_limit - set OT limit for the given plane
0429  * @plane:      Pointer to drm plane
0430  * @crtc:       Pointer to drm crtc
0431  * @pipe_cfg:       Pointer to pipe configuration
0432  */
0433 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
0434         struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
0435 {
0436     struct dpu_plane *pdpu = to_dpu_plane(plane);
0437     struct dpu_vbif_set_ot_params ot_params;
0438     struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
0439 
0440     memset(&ot_params, 0, sizeof(ot_params));
0441     ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
0442     ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
0443     ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
0444     ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
0445     ot_params.is_wfd = !pdpu->is_rt_pipe;
0446     ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
0447     ot_params.vbif_idx = VBIF_RT;
0448     ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
0449     ot_params.rd = true;
0450 
0451     dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
0452 }
0453 
0454 /**
0455  * _dpu_plane_set_qos_remap - set vbif QoS for the given plane
0456  * @plane:      Pointer to drm plane
0457  */
0458 static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
0459 {
0460     struct dpu_plane *pdpu = to_dpu_plane(plane);
0461     struct dpu_vbif_set_qos_params qos_params;
0462     struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
0463 
0464     memset(&qos_params, 0, sizeof(qos_params));
0465     qos_params.vbif_idx = VBIF_RT;
0466     qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
0467     qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
0468     qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
0469     qos_params.is_rt = pdpu->is_rt_pipe;
0470 
0471     DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
0472             qos_params.num,
0473             qos_params.vbif_idx,
0474             qos_params.xin_id, qos_params.is_rt,
0475             qos_params.clk_ctrl);
0476 
0477     dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
0478 }
0479 
0480 static void _dpu_plane_set_scanout(struct drm_plane *plane,
0481         struct dpu_plane_state *pstate,
0482         struct dpu_hw_pipe_cfg *pipe_cfg,
0483         struct drm_framebuffer *fb)
0484 {
0485     struct dpu_plane *pdpu = to_dpu_plane(plane);
0486     struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
0487     struct msm_gem_address_space *aspace = kms->base.aspace;
0488     int ret;
0489 
0490     ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
0491     if (ret == -EAGAIN)
0492         DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
0493     else if (ret)
0494         DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
0495     else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
0496         trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
0497                         &pipe_cfg->layout,
0498                         pstate->multirect_index);
0499         pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
0500                         pstate->multirect_index);
0501     }
0502 }
0503 
0504 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
0505         struct dpu_plane_state *pstate,
0506         uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
0507         struct dpu_hw_scaler3_cfg *scale_cfg,
0508         const struct dpu_format *fmt,
0509         uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
0510 {
0511     uint32_t i;
0512     bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90;
0513 
0514     /*
0515      * For inline rotation cases, scaler config is post-rotation,
0516      * so swap the dimensions here. However, pixel extension will
0517      * need pre-rotation settings.
0518      */
0519     if (inline_rotation)
0520         swap(src_w, src_h);
0521 
0522     scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
0523         mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
0524     scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
0525         mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
0526 
0527 
0528     scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
0529         scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v;
0530     scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] =
0531         scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h;
0532 
0533     scale_cfg->phase_step_x[DPU_SSPP_COMP_2] =
0534         scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2];
0535     scale_cfg->phase_step_y[DPU_SSPP_COMP_2] =
0536         scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2];
0537 
0538     scale_cfg->phase_step_x[DPU_SSPP_COMP_3] =
0539         scale_cfg->phase_step_x[DPU_SSPP_COMP_0];
0540     scale_cfg->phase_step_y[DPU_SSPP_COMP_3] =
0541         scale_cfg->phase_step_y[DPU_SSPP_COMP_0];
0542 
0543     for (i = 0; i < DPU_MAX_PLANES; i++) {
0544         scale_cfg->src_width[i] = src_w;
0545         scale_cfg->src_height[i] = src_h;
0546         if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
0547             scale_cfg->src_width[i] /= chroma_subsmpl_h;
0548             scale_cfg->src_height[i] /= chroma_subsmpl_v;
0549         }
0550 
0551         if (pdpu->pipe_hw->cap->features &
0552             BIT(DPU_SSPP_SCALER_QSEED4)) {
0553             scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
0554             scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
0555         } else {
0556             scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
0557             scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
0558         }
0559     }
0560     if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
0561         && (src_w == dst_w))
0562         return;
0563 
0564     scale_cfg->dst_width = dst_w;
0565     scale_cfg->dst_height = dst_h;
0566     scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL;
0567     scale_cfg->uv_filter_cfg = DPU_SCALE_BIL;
0568     scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL;
0569     scale_cfg->lut_flag = 0;
0570     scale_cfg->blend_cfg = 1;
0571     scale_cfg->enable = 1;
0572 }
0573 
0574 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,
0575                 struct dpu_hw_pixel_ext *pixel_ext,
0576                 uint32_t src_w, uint32_t src_h,
0577                 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
0578 {
0579     int i;
0580 
0581     for (i = 0; i < DPU_MAX_PLANES; i++) {
0582         if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
0583             src_w /= chroma_subsmpl_h;
0584             src_h /= chroma_subsmpl_v;
0585         }
0586 
0587         pixel_ext->num_ext_pxls_top[i] = src_h;
0588         pixel_ext->num_ext_pxls_left[i] = src_w;
0589     }
0590 }
0591 
0592 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
0593     {
0594         /* S15.16 format */
0595         0x00012A00, 0x00000000, 0x00019880,
0596         0x00012A00, 0xFFFF9B80, 0xFFFF3000,
0597         0x00012A00, 0x00020480, 0x00000000,
0598     },
0599     /* signed bias */
0600     { 0xfff0, 0xff80, 0xff80,},
0601     { 0x0, 0x0, 0x0,},
0602     /* unsigned clamp */
0603     { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
0604     { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
0605 };
0606 
0607 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
0608     {
0609         /* S15.16 format */
0610         0x00012A00, 0x00000000, 0x00019880,
0611         0x00012A00, 0xFFFF9B80, 0xFFFF3000,
0612         0x00012A00, 0x00020480, 0x00000000,
0613         },
0614     /* signed bias */
0615     { 0xffc0, 0xfe00, 0xfe00,},
0616     { 0x0, 0x0, 0x0,},
0617     /* unsigned clamp */
0618     { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
0619     { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
0620 };
0621 
0622 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
0623 {
0624     const struct dpu_csc_cfg *csc_ptr;
0625 
0626     if (!pdpu) {
0627         DPU_ERROR("invalid plane\n");
0628         return NULL;
0629     }
0630 
0631     if (!DPU_FORMAT_IS_YUV(fmt))
0632         return NULL;
0633 
0634     if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features)
0635         csc_ptr = &dpu_csc10_YUV2RGB_601L;
0636     else
0637         csc_ptr = &dpu_csc_YUV2RGB_601L;
0638 
0639     DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
0640             csc_ptr->csc_mv[0],
0641             csc_ptr->csc_mv[1],
0642             csc_ptr->csc_mv[2]);
0643 
0644     return csc_ptr;
0645 }
0646 
0647 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
0648         struct dpu_plane_state *pstate,
0649         const struct dpu_format *fmt, bool color_fill,
0650         struct dpu_hw_pipe_cfg *pipe_cfg)
0651 {
0652     const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
0653     struct dpu_hw_scaler3_cfg scaler3_cfg;
0654     struct dpu_hw_pixel_ext pixel_ext;
0655     u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
0656     u32 src_height = drm_rect_height(&pipe_cfg->src_rect);
0657     u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect);
0658     u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect);
0659 
0660     memset(&scaler3_cfg, 0, sizeof(scaler3_cfg));
0661     memset(&pixel_ext, 0, sizeof(pixel_ext));
0662 
0663     /* don't chroma subsample if decimating */
0664     /* update scaler. calculate default config for QSEED3 */
0665     _dpu_plane_setup_scaler3(pdpu, pstate,
0666             src_width,
0667             src_height,
0668             dst_width,
0669             dst_height,
0670             &scaler3_cfg, fmt,
0671             info->hsub, info->vsub);
0672 
0673     /* configure pixel extension based on scalar config */
0674     _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
0675             src_width, src_height, info->hsub, info->vsub);
0676 
0677     if (pdpu->pipe_hw->ops.setup_pe)
0678         pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
0679                 &pixel_ext);
0680 
0681     /**
0682      * when programmed in multirect mode, scalar block will be
0683      * bypassed. Still we need to update alpha and bitwidth
0684      * ONLY for RECT0
0685      */
0686     if (pdpu->pipe_hw->ops.setup_scaler &&
0687             pstate->multirect_index != DPU_SSPP_RECT_1)
0688         pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
0689                 pipe_cfg,
0690                 &scaler3_cfg);
0691 }
0692 
0693 /**
0694  * _dpu_plane_color_fill - enables color fill on plane
0695  * @pdpu:   Pointer to DPU plane object
0696  * @color:  RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
0697  * @alpha:  8-bit fill alpha value, 255 selects 100% alpha
0698  * Returns: 0 on success
0699  */
0700 static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
0701         uint32_t color, uint32_t alpha)
0702 {
0703     const struct dpu_format *fmt;
0704     const struct drm_plane *plane = &pdpu->base;
0705     struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
0706     struct dpu_hw_pipe_cfg pipe_cfg;
0707 
0708     DPU_DEBUG_PLANE(pdpu, "\n");
0709 
0710     /*
0711      * select fill format to match user property expectation,
0712      * h/w only supports RGB variants
0713      */
0714     fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
0715 
0716     /* update sspp */
0717     if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
0718         pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
0719                 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
0720                 pstate->multirect_index);
0721 
0722         /* override scaler/decimation if solid fill */
0723         pipe_cfg.dst_rect = pstate->base.dst;
0724 
0725         pipe_cfg.src_rect.x1 = 0;
0726         pipe_cfg.src_rect.y1 = 0;
0727         pipe_cfg.src_rect.x2 =
0728             drm_rect_width(&pipe_cfg.dst_rect);
0729         pipe_cfg.src_rect.y2 =
0730             drm_rect_height(&pipe_cfg.dst_rect);
0731 
0732         if (pdpu->pipe_hw->ops.setup_format)
0733             pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
0734                     fmt, DPU_SSPP_SOLID_FILL,
0735                     pstate->multirect_index);
0736 
0737         if (pdpu->pipe_hw->ops.setup_rects)
0738             pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
0739                     &pipe_cfg,
0740                     pstate->multirect_index);
0741 
0742         _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
0743     }
0744 
0745     return 0;
0746 }
0747 
0748 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
0749 {
0750     struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
0751 
0752     pstate->multirect_index = DPU_SSPP_RECT_SOLO;
0753     pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
0754 }
0755 
0756 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
0757 {
0758     struct dpu_plane_state *pstate[R_MAX];
0759     const struct drm_plane_state *drm_state[R_MAX];
0760     struct drm_rect src[R_MAX], dst[R_MAX];
0761     struct dpu_plane *dpu_plane[R_MAX];
0762     const struct dpu_format *fmt[R_MAX];
0763     int i, buffer_lines;
0764     unsigned int max_tile_height = 1;
0765     bool parallel_fetch_qualified = true;
0766     bool has_tiled_rect = false;
0767 
0768     for (i = 0; i < R_MAX; i++) {
0769         const struct msm_format *msm_fmt;
0770 
0771         drm_state[i] = i ? plane->r1 : plane->r0;
0772         msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
0773         fmt[i] = to_dpu_format(msm_fmt);
0774 
0775         if (DPU_FORMAT_IS_UBWC(fmt[i])) {
0776             has_tiled_rect = true;
0777             if (fmt[i]->tile_height > max_tile_height)
0778                 max_tile_height = fmt[i]->tile_height;
0779         }
0780     }
0781 
0782     for (i = 0; i < R_MAX; i++) {
0783         int width_threshold;
0784 
0785         pstate[i] = to_dpu_plane_state(drm_state[i]);
0786         dpu_plane[i] = to_dpu_plane(drm_state[i]->plane);
0787 
0788         if (pstate[i] == NULL) {
0789             DPU_ERROR("DPU plane state of plane id %d is NULL\n",
0790                 drm_state[i]->plane->base.id);
0791             return -EINVAL;
0792         }
0793 
0794         src[i].x1 = drm_state[i]->src_x >> 16;
0795         src[i].y1 = drm_state[i]->src_y >> 16;
0796         src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16);
0797         src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16);
0798 
0799         dst[i] = drm_plane_state_dest(drm_state[i]);
0800 
0801         if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 ||
0802             drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) {
0803             DPU_ERROR_PLANE(dpu_plane[i],
0804                 "scaling is not supported in multirect mode\n");
0805             return -EINVAL;
0806         }
0807 
0808         if (DPU_FORMAT_IS_YUV(fmt[i])) {
0809             DPU_ERROR_PLANE(dpu_plane[i],
0810                 "Unsupported format for multirect mode\n");
0811             return -EINVAL;
0812         }
0813 
0814         /**
0815          * SSPP PD_MEM is split half - one for each RECT.
0816          * Tiled formats need 5 lines of buffering while fetching
0817          * whereas linear formats need only 2 lines.
0818          * So we cannot support more than half of the supported SSPP
0819          * width for tiled formats.
0820          */
0821         width_threshold = dpu_plane[i]->catalog->caps->max_linewidth;
0822         if (has_tiled_rect)
0823             width_threshold /= 2;
0824 
0825         if (parallel_fetch_qualified &&
0826             drm_rect_width(&src[i]) > width_threshold)
0827             parallel_fetch_qualified = false;
0828 
0829     }
0830 
0831     /* Validate RECT's and set the mode */
0832 
0833     /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
0834     if (parallel_fetch_qualified) {
0835         pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
0836         pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
0837 
0838         goto done;
0839     }
0840 
0841     /* TIME_MX Mode */
0842     buffer_lines = 2 * max_tile_height;
0843 
0844     if (dst[R1].y1 >= dst[R0].y2 + buffer_lines ||
0845         dst[R0].y1 >= dst[R1].y2 + buffer_lines) {
0846         pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
0847         pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
0848     } else {
0849         DPU_ERROR(
0850             "No multirect mode possible for the planes (%d - %d)\n",
0851             drm_state[R0]->plane->base.id,
0852             drm_state[R1]->plane->base.id);
0853         return -EINVAL;
0854     }
0855 
0856 done:
0857     if (dpu_plane[R0]->is_virtual) {
0858         pstate[R0]->multirect_index = DPU_SSPP_RECT_1;
0859         pstate[R1]->multirect_index = DPU_SSPP_RECT_0;
0860     } else {
0861         pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
0862         pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
0863     }
0864 
0865     DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
0866         pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
0867     DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
0868         pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
0869     return 0;
0870 }
0871 
0872 /**
0873  * dpu_plane_get_ctl_flush - get control flush for the given plane
0874  * @plane: Pointer to drm plane structure
0875  * @ctl: Pointer to hardware control driver
0876  * @flush_sspp: Pointer to sspp flush control word
0877  */
0878 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
0879         u32 *flush_sspp)
0880 {
0881     *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
0882 }
0883 
0884 static int dpu_plane_prepare_fb(struct drm_plane *plane,
0885         struct drm_plane_state *new_state)
0886 {
0887     struct drm_framebuffer *fb = new_state->fb;
0888     struct dpu_plane *pdpu = to_dpu_plane(plane);
0889     struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
0890     struct dpu_hw_fmt_layout layout;
0891     struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
0892     int ret;
0893 
0894     if (!new_state->fb)
0895         return 0;
0896 
0897     DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
0898 
0899     /* cache aspace */
0900     pstate->aspace = kms->base.aspace;
0901 
0902     /*
0903      * TODO: Need to sort out the msm_framebuffer_prepare() call below so
0904      *       we can use msm_atomic_prepare_fb() instead of doing the
0905      *       implicit fence and fb prepare by hand here.
0906      */
0907     drm_gem_plane_helper_prepare_fb(plane, new_state);
0908 
0909     if (pstate->aspace) {
0910         ret = msm_framebuffer_prepare(new_state->fb,
0911                 pstate->aspace, pstate->needs_dirtyfb);
0912         if (ret) {
0913             DPU_ERROR("failed to prepare framebuffer\n");
0914             return ret;
0915         }
0916     }
0917 
0918     /* validate framebuffer layout before commit */
0919     ret = dpu_format_populate_layout(pstate->aspace,
0920             new_state->fb, &layout);
0921     if (ret) {
0922         DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
0923         return ret;
0924     }
0925 
0926     return 0;
0927 }
0928 
0929 static void dpu_plane_cleanup_fb(struct drm_plane *plane,
0930         struct drm_plane_state *old_state)
0931 {
0932     struct dpu_plane *pdpu = to_dpu_plane(plane);
0933     struct dpu_plane_state *old_pstate;
0934 
0935     if (!old_state || !old_state->fb)
0936         return;
0937 
0938     old_pstate = to_dpu_plane_state(old_state);
0939 
0940     DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
0941 
0942     msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace,
0943                 old_pstate->needs_dirtyfb);
0944 }
0945 
0946 static bool dpu_plane_validate_src(struct drm_rect *src,
0947                    struct drm_rect *fb_rect,
0948                    uint32_t min_src_size)
0949 {
0950     /* Ensure fb size is supported */
0951     if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH ||
0952         drm_rect_height(fb_rect) > MAX_IMG_HEIGHT)
0953         return false;
0954 
0955     /* Ensure src rect is above the minimum size */
0956     if (drm_rect_width(src) < min_src_size ||
0957         drm_rect_height(src) < min_src_size)
0958         return false;
0959 
0960     /* Ensure src is fully encapsulated in fb */
0961     return drm_rect_intersect(fb_rect, src) &&
0962         drm_rect_equals(fb_rect, src);
0963 }
0964 
0965 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
0966                         const struct dpu_sspp_sub_blks *sblk,
0967                         struct drm_rect src, const struct dpu_format *fmt)
0968 {
0969     size_t num_formats;
0970     const u32 *supported_formats;
0971 
0972     if (!sblk->rotation_cfg) {
0973         DPU_ERROR("invalid rotation cfg\n");
0974         return -EINVAL;
0975     }
0976 
0977     if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) {
0978         DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n",
0979                 src.y2, sblk->rotation_cfg->rot_maxheight);
0980         return -EINVAL;
0981     }
0982 
0983     supported_formats = sblk->rotation_cfg->rot_format_list;
0984     num_formats = sblk->rotation_cfg->rot_num_formats;
0985 
0986     if (!DPU_FORMAT_IS_UBWC(fmt) ||
0987         !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats))
0988         return -EINVAL;
0989 
0990     return 0;
0991 }
0992 
0993 static int dpu_plane_atomic_check(struct drm_plane *plane,
0994                   struct drm_atomic_state *state)
0995 {
0996     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0997                                          plane);
0998     int ret = 0, min_scale;
0999     struct dpu_plane *pdpu = to_dpu_plane(plane);
1000     struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
1001     const struct drm_crtc_state *crtc_state = NULL;
1002     const struct dpu_format *fmt;
1003     struct drm_rect src, dst, fb_rect = { 0 };
1004     uint32_t min_src_size, max_linewidth;
1005     unsigned int rotation;
1006     uint32_t supported_rotations;
1007     const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap;
1008     const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk;
1009 
1010     if (new_plane_state->crtc)
1011         crtc_state = drm_atomic_get_new_crtc_state(state,
1012                                new_plane_state->crtc);
1013 
1014     min_scale = FRAC_16_16(1, sblk->maxupscale);
1015     ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
1016                           min_scale,
1017                           sblk->maxdwnscale << 16,
1018                           true, true);
1019     if (ret) {
1020         DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
1021         return ret;
1022     }
1023     if (!new_plane_state->visible)
1024         return 0;
1025 
1026     src.x1 = new_plane_state->src_x >> 16;
1027     src.y1 = new_plane_state->src_y >> 16;
1028     src.x2 = src.x1 + (new_plane_state->src_w >> 16);
1029     src.y2 = src.y1 + (new_plane_state->src_h >> 16);
1030 
1031     dst = drm_plane_state_dest(new_plane_state);
1032 
1033     fb_rect.x2 = new_plane_state->fb->width;
1034     fb_rect.y2 = new_plane_state->fb->height;
1035 
1036     max_linewidth = pdpu->catalog->caps->max_linewidth;
1037 
1038     fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
1039 
1040     min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
1041 
1042     if (DPU_FORMAT_IS_YUV(fmt) &&
1043         (!(pipe_hw_caps->features & DPU_SSPP_SCALER) ||
1044          !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) {
1045         DPU_DEBUG_PLANE(pdpu,
1046                 "plane doesn't have scaler/csc for yuv\n");
1047         return -EINVAL;
1048 
1049     /* check src bounds */
1050     } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
1051         DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
1052                 DRM_RECT_ARG(&src));
1053         return -E2BIG;
1054 
1055     /* valid yuv image */
1056     } else if (DPU_FORMAT_IS_YUV(fmt) &&
1057            (src.x1 & 0x1 || src.y1 & 0x1 ||
1058             drm_rect_width(&src) & 0x1 ||
1059             drm_rect_height(&src) & 0x1)) {
1060         DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
1061                 DRM_RECT_ARG(&src));
1062         return -EINVAL;
1063 
1064     /* min dst support */
1065     } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
1066         DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
1067                 DRM_RECT_ARG(&dst));
1068         return -EINVAL;
1069 
1070     /* check decimated source width */
1071     } else if (drm_rect_width(&src) > max_linewidth) {
1072         DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
1073                 DRM_RECT_ARG(&src), max_linewidth);
1074         return -E2BIG;
1075     }
1076 
1077     supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
1078 
1079     if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION))
1080         supported_rotations |= DRM_MODE_ROTATE_90;
1081 
1082     rotation = drm_rotation_simplify(new_plane_state->rotation,
1083                     supported_rotations);
1084 
1085     if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) &&
1086         (rotation & DRM_MODE_ROTATE_90)) {
1087         ret = dpu_plane_check_inline_rotation(pdpu, sblk, src, fmt);
1088         if (ret)
1089             return ret;
1090     }
1091 
1092     pstate->rotation = rotation;
1093     pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);
1094 
1095     return 0;
1096 }
1097 
1098 void dpu_plane_flush(struct drm_plane *plane)
1099 {
1100     struct dpu_plane *pdpu;
1101     struct dpu_plane_state *pstate;
1102 
1103     if (!plane || !plane->state) {
1104         DPU_ERROR("invalid plane\n");
1105         return;
1106     }
1107 
1108     pdpu = to_dpu_plane(plane);
1109     pstate = to_dpu_plane_state(plane->state);
1110 
1111     /*
1112      * These updates have to be done immediately before the plane flush
1113      * timing, and may not be moved to the atomic_update/mode_set functions.
1114      */
1115     if (pdpu->is_error)
1116         /* force white frame with 100% alpha pipe output on error */
1117         _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
1118     else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
1119         /* force 100% alpha */
1120         _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
1121     else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) {
1122         const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
1123         const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
1124 
1125         if (csc_ptr)
1126             pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr);
1127     }
1128 
1129     /* flag h/w flush complete */
1130     if (plane->state)
1131         pstate->pending = false;
1132 }
1133 
1134 /**
1135  * dpu_plane_set_error: enable/disable error condition
1136  * @plane: pointer to drm_plane structure
1137  * @error: error value to set
1138  */
1139 void dpu_plane_set_error(struct drm_plane *plane, bool error)
1140 {
1141     struct dpu_plane *pdpu;
1142 
1143     if (!plane)
1144         return;
1145 
1146     pdpu = to_dpu_plane(plane);
1147     pdpu->is_error = error;
1148 }
1149 
1150 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
1151 {
1152     uint32_t src_flags;
1153     struct dpu_plane *pdpu = to_dpu_plane(plane);
1154     struct drm_plane_state *state = plane->state;
1155     struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1156     struct drm_crtc *crtc = state->crtc;
1157     struct drm_framebuffer *fb = state->fb;
1158     bool is_rt_pipe, update_qos_remap;
1159     const struct dpu_format *fmt =
1160         to_dpu_format(msm_framebuffer_format(fb));
1161     struct dpu_hw_pipe_cfg pipe_cfg;
1162 
1163     memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
1164 
1165     _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
1166 
1167     pstate->pending = true;
1168 
1169     is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
1170     _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1171 
1172     DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1173             ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1174             crtc->base.id, DRM_RECT_ARG(&state->dst),
1175             (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
1176 
1177     pipe_cfg.src_rect = state->src;
1178 
1179     /* state->src is 16.16, src_rect is not */
1180     pipe_cfg.src_rect.x1 >>= 16;
1181     pipe_cfg.src_rect.x2 >>= 16;
1182     pipe_cfg.src_rect.y1 >>= 16;
1183     pipe_cfg.src_rect.y2 >>= 16;
1184 
1185     pipe_cfg.dst_rect = state->dst;
1186 
1187     /* override for color fill */
1188     if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1189         /* skip remaining processing on color fill */
1190         return;
1191     }
1192 
1193     if (pdpu->pipe_hw->ops.setup_rects) {
1194         pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
1195                 &pipe_cfg,
1196                 pstate->multirect_index);
1197     }
1198 
1199     _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
1200 
1201     if (pdpu->pipe_hw->ops.setup_multirect)
1202         pdpu->pipe_hw->ops.setup_multirect(
1203                 pdpu->pipe_hw,
1204                 pstate->multirect_index,
1205                 pstate->multirect_mode);
1206 
1207     if (pdpu->pipe_hw->ops.setup_format) {
1208         unsigned int rotation = pstate->rotation;
1209 
1210         src_flags = 0x0;
1211 
1212         if (rotation & DRM_MODE_REFLECT_X)
1213             src_flags |= DPU_SSPP_FLIP_LR;
1214 
1215         if (rotation & DRM_MODE_REFLECT_Y)
1216             src_flags |= DPU_SSPP_FLIP_UD;
1217 
1218         if (rotation & DRM_MODE_ROTATE_90)
1219             src_flags |= DPU_SSPP_ROT_90;
1220 
1221         /* update format */
1222         pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
1223                 pstate->multirect_index);
1224 
1225         if (pdpu->pipe_hw->ops.setup_cdp) {
1226             struct dpu_hw_cdp_cfg cdp_cfg;
1227 
1228             memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
1229 
1230             cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg
1231                     [DPU_PERF_CDP_USAGE_RT].rd_enable;
1232             cdp_cfg.ubwc_meta_enable =
1233                     DPU_FORMAT_IS_UBWC(fmt);
1234             cdp_cfg.tile_amortize_enable =
1235                     DPU_FORMAT_IS_UBWC(fmt) ||
1236                     DPU_FORMAT_IS_TILE(fmt);
1237             cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
1238 
1239             pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index);
1240         }
1241     }
1242 
1243     _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg);
1244     _dpu_plane_set_danger_lut(plane, fb);
1245 
1246     if (plane->type != DRM_PLANE_TYPE_CURSOR) {
1247         _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
1248         _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
1249     }
1250 
1251     update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) ||
1252             pstate->needs_qos_remap;
1253 
1254     if (update_qos_remap) {
1255         if (is_rt_pipe != pdpu->is_rt_pipe)
1256             pdpu->is_rt_pipe = is_rt_pipe;
1257         else if (pstate->needs_qos_remap)
1258             pstate->needs_qos_remap = false;
1259         _dpu_plane_set_qos_remap(plane);
1260     }
1261 
1262     _dpu_plane_calc_bw(plane, fb, &pipe_cfg);
1263 
1264     _dpu_plane_calc_clk(plane, &pipe_cfg);
1265 }
1266 
1267 static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1268 {
1269     struct dpu_plane *pdpu = to_dpu_plane(plane);
1270     struct drm_plane_state *state = plane->state;
1271     struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1272 
1273     trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
1274                 pstate->multirect_mode);
1275 
1276     pstate->pending = true;
1277 
1278     if (is_dpu_plane_virtual(plane) &&
1279             pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect)
1280         pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw,
1281                 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE);
1282 }
1283 
1284 static void dpu_plane_atomic_update(struct drm_plane *plane,
1285                 struct drm_atomic_state *state)
1286 {
1287     struct dpu_plane *pdpu = to_dpu_plane(plane);
1288     struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1289                                        plane);
1290 
1291     pdpu->is_error = false;
1292 
1293     DPU_DEBUG_PLANE(pdpu, "\n");
1294 
1295     if (!new_state->visible) {
1296         _dpu_plane_atomic_disable(plane);
1297     } else {
1298         dpu_plane_sspp_atomic_update(plane);
1299     }
1300 }
1301 
1302 static void dpu_plane_destroy(struct drm_plane *plane)
1303 {
1304     struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
1305 
1306     DPU_DEBUG_PLANE(pdpu, "\n");
1307 
1308     if (pdpu) {
1309         _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1310 
1311         mutex_destroy(&pdpu->lock);
1312 
1313         /* this will destroy the states as well */
1314         drm_plane_cleanup(plane);
1315 
1316         dpu_hw_sspp_destroy(pdpu->pipe_hw);
1317 
1318         kfree(pdpu);
1319     }
1320 }
1321 
1322 static void dpu_plane_destroy_state(struct drm_plane *plane,
1323         struct drm_plane_state *state)
1324 {
1325     __drm_atomic_helper_plane_destroy_state(state);
1326     kfree(to_dpu_plane_state(state));
1327 }
1328 
1329 static struct drm_plane_state *
1330 dpu_plane_duplicate_state(struct drm_plane *plane)
1331 {
1332     struct dpu_plane *pdpu;
1333     struct dpu_plane_state *pstate;
1334     struct dpu_plane_state *old_state;
1335 
1336     if (!plane) {
1337         DPU_ERROR("invalid plane\n");
1338         return NULL;
1339     } else if (!plane->state) {
1340         DPU_ERROR("invalid plane state\n");
1341         return NULL;
1342     }
1343 
1344     old_state = to_dpu_plane_state(plane->state);
1345     pdpu = to_dpu_plane(plane);
1346     pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1347     if (!pstate) {
1348         DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1349         return NULL;
1350     }
1351 
1352     DPU_DEBUG_PLANE(pdpu, "\n");
1353 
1354     pstate->pending = false;
1355 
1356     __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1357 
1358     return &pstate->base;
1359 }
1360 
1361 static const char * const multirect_mode_name[] = {
1362     [DPU_SSPP_MULTIRECT_NONE] = "none",
1363     [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel",
1364     [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx",
1365 };
1366 
1367 static const char * const multirect_index_name[] = {
1368     [DPU_SSPP_RECT_SOLO] = "solo",
1369     [DPU_SSPP_RECT_0] = "rect_0",
1370     [DPU_SSPP_RECT_1] = "rect_1",
1371 };
1372 
1373 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode)
1374 {
1375     if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name)))
1376         return "unknown";
1377 
1378     return multirect_mode_name[mode];
1379 }
1380 
1381 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index)
1382 {
1383     if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name)))
1384         return "unknown";
1385 
1386     return multirect_index_name[index];
1387 }
1388 
1389 static void dpu_plane_atomic_print_state(struct drm_printer *p,
1390         const struct drm_plane_state *state)
1391 {
1392     const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1393     const struct dpu_plane *pdpu = to_dpu_plane(state->plane);
1394 
1395     drm_printf(p, "\tstage=%d\n", pstate->stage);
1396     drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name);
1397     drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode));
1398     drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index));
1399 }
1400 
1401 static void dpu_plane_reset(struct drm_plane *plane)
1402 {
1403     struct dpu_plane *pdpu;
1404     struct dpu_plane_state *pstate;
1405 
1406     if (!plane) {
1407         DPU_ERROR("invalid plane\n");
1408         return;
1409     }
1410 
1411     pdpu = to_dpu_plane(plane);
1412     DPU_DEBUG_PLANE(pdpu, "\n");
1413 
1414     /* remove previous state, if present */
1415     if (plane->state) {
1416         dpu_plane_destroy_state(plane, plane->state);
1417         plane->state = NULL;
1418     }
1419 
1420     pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1421     if (!pstate) {
1422         DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1423         return;
1424     }
1425 
1426     __drm_atomic_helper_plane_reset(plane, &pstate->base);
1427 }
1428 
1429 #ifdef CONFIG_DEBUG_FS
1430 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1431 {
1432     struct dpu_plane *pdpu = to_dpu_plane(plane);
1433     struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1434 
1435     if (!pdpu->is_rt_pipe)
1436         return;
1437 
1438     pm_runtime_get_sync(&dpu_kms->pdev->dev);
1439     _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
1440     pm_runtime_put_sync(&dpu_kms->pdev->dev);
1441 }
1442 
1443 /* SSPP live inside dpu_plane private data only. Enumerate them here. */
1444 void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
1445 {
1446     struct drm_plane *plane;
1447     struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
1448 
1449     if (IS_ERR(entry))
1450         return;
1451 
1452     drm_for_each_plane(plane, dpu_kms->dev) {
1453         struct dpu_plane *pdpu = to_dpu_plane(plane);
1454 
1455         _dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry);
1456     }
1457 }
1458 #endif
1459 
1460 static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
1461         uint32_t format, uint64_t modifier)
1462 {
1463     if (modifier == DRM_FORMAT_MOD_LINEAR)
1464         return true;
1465 
1466     if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED)
1467         return dpu_find_format(format, qcom_compressed_supported_formats,
1468                 ARRAY_SIZE(qcom_compressed_supported_formats));
1469 
1470     return false;
1471 }
1472 
1473 static const struct drm_plane_funcs dpu_plane_funcs = {
1474         .update_plane = drm_atomic_helper_update_plane,
1475         .disable_plane = drm_atomic_helper_disable_plane,
1476         .destroy = dpu_plane_destroy,
1477         .reset = dpu_plane_reset,
1478         .atomic_duplicate_state = dpu_plane_duplicate_state,
1479         .atomic_destroy_state = dpu_plane_destroy_state,
1480         .atomic_print_state = dpu_plane_atomic_print_state,
1481         .format_mod_supported = dpu_plane_format_mod_supported,
1482 };
1483 
1484 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
1485         .prepare_fb = dpu_plane_prepare_fb,
1486         .cleanup_fb = dpu_plane_cleanup_fb,
1487         .atomic_check = dpu_plane_atomic_check,
1488         .atomic_update = dpu_plane_atomic_update,
1489 };
1490 
1491 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
1492 {
1493     return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
1494 }
1495 
1496 bool is_dpu_plane_virtual(struct drm_plane *plane)
1497 {
1498     return plane ? to_dpu_plane(plane)->is_virtual : false;
1499 }
1500 
1501 /* initialize plane */
1502 struct drm_plane *dpu_plane_init(struct drm_device *dev,
1503         uint32_t pipe, enum drm_plane_type type,
1504         unsigned long possible_crtcs, u32 master_plane_id)
1505 {
1506     struct drm_plane *plane = NULL, *master_plane = NULL;
1507     const uint32_t *format_list;
1508     struct dpu_plane *pdpu;
1509     struct msm_drm_private *priv = dev->dev_private;
1510     struct dpu_kms *kms = to_dpu_kms(priv->kms);
1511     int zpos_max = DPU_ZPOS_MAX;
1512     uint32_t num_formats;
1513     uint32_t supported_rotations;
1514     int ret = -EINVAL;
1515 
1516     /* create and zero local structure */
1517     pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);
1518     if (!pdpu) {
1519         DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe);
1520         ret = -ENOMEM;
1521         return ERR_PTR(ret);
1522     }
1523 
1524     /* cache local stuff for later */
1525     plane = &pdpu->base;
1526     pdpu->pipe = pipe;
1527     pdpu->is_virtual = (master_plane_id != 0);
1528     INIT_LIST_HEAD(&pdpu->mplane_list);
1529     master_plane = drm_plane_find(dev, NULL, master_plane_id);
1530     if (master_plane) {
1531         struct dpu_plane *mpdpu = to_dpu_plane(master_plane);
1532 
1533         list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list);
1534     }
1535 
1536     /* initialize underlying h/w driver */
1537     pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog,
1538                             master_plane_id != 0);
1539     if (IS_ERR(pdpu->pipe_hw)) {
1540         DPU_ERROR("[%u]SSPP init failed\n", pipe);
1541         ret = PTR_ERR(pdpu->pipe_hw);
1542         goto clean_plane;
1543     } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
1544         DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
1545         goto clean_sspp;
1546     }
1547 
1548     if (pdpu->is_virtual) {
1549         format_list = pdpu->pipe_hw->cap->sblk->virt_format_list;
1550         num_formats = pdpu->pipe_hw->cap->sblk->virt_num_formats;
1551     }
1552     else {
1553         format_list = pdpu->pipe_hw->cap->sblk->format_list;
1554         num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
1555     }
1556 
1557     ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
1558                 format_list, num_formats,
1559                 supported_format_modifiers, type, NULL);
1560     if (ret)
1561         goto clean_sspp;
1562 
1563     pdpu->catalog = kms->catalog;
1564 
1565     if (kms->catalog->mixer_count &&
1566         kms->catalog->mixer[0].sblk->maxblendstages) {
1567         zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
1568         if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
1569             zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
1570     }
1571 
1572     ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
1573     if (ret)
1574         DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1575 
1576     drm_plane_create_alpha_property(plane);
1577     drm_plane_create_blend_mode_property(plane,
1578             BIT(DRM_MODE_BLEND_PIXEL_NONE) |
1579             BIT(DRM_MODE_BLEND_PREMULTI) |
1580             BIT(DRM_MODE_BLEND_COVERAGE));
1581 
1582     supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1583 
1584     if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
1585         supported_rotations |= DRM_MODE_ROTATE_MASK;
1586 
1587     drm_plane_create_rotation_property(plane,
1588             DRM_MODE_ROTATE_0, supported_rotations);
1589 
1590     drm_plane_enable_fb_damage_clips(plane);
1591 
1592     /* success! finalize initialization */
1593     drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
1594 
1595     mutex_init(&pdpu->lock);
1596 
1597     DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", plane->name,
1598                     pipe, plane->base.id, master_plane_id);
1599     return plane;
1600 
1601 clean_sspp:
1602     if (pdpu && pdpu->pipe_hw)
1603         dpu_hw_sspp_destroy(pdpu->pipe_hw);
1604 clean_plane:
1605     list_del(&pdpu->mplane_list);
1606     kfree(pdpu);
1607     return ERR_PTR(ret);
1608 }
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