disp/dpu1/dpu_hwio.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0003  */
0004
0005 #ifndef _DPU_HWIO_H
0006 #define _DPU_HWIO_H
0007
0008 #include "dpu_hw_util.h"
0009
0010 /**
0011  * MDP TOP block Register and bit fields and defines
0012  */
0013 #define DISP_INTF_SEL                   0x004
0014 #define INTR_EN                         0x010
0015 #define INTR_STATUS                     0x014
0016 #define INTR_CLEAR                      0x018
0017 #define INTR2_EN                        0x008
0018 #define INTR2_STATUS                    0x00c
0019 #define INTR2_CLEAR                     0x02c
0020 #define HIST_INTR_EN                    0x01c
0021 #define HIST_INTR_STATUS                0x020
0022 #define HIST_INTR_CLEAR                 0x024
0023 #define INTF_INTR_EN                    0x1C0
0024 #define INTF_INTR_STATUS                0x1C4
0025 #define INTF_INTR_CLEAR                 0x1C8
0026 #define SPLIT_DISPLAY_EN                0x2F4
0027 #define SPLIT_DISPLAY_UPPER_PIPE_CTRL   0x2F8
0028 #define DSPP_IGC_COLOR0_RAM_LUTN        0x300
0029 #define DSPP_IGC_COLOR1_RAM_LUTN        0x304
0030 #define DSPP_IGC_COLOR2_RAM_LUTN        0x308
0031 #define HW_EVENTS_CTL                   0x37C
0032 #define CLK_CTRL3                       0x3A8
0033 #define CLK_STATUS3                     0x3AC
0034 #define CLK_CTRL4                       0x3B0
0035 #define CLK_STATUS4                     0x3B4
0036 #define CLK_CTRL5                       0x3B8
0037 #define CLK_STATUS5                     0x3BC
0038 #define CLK_CTRL7                       0x3D0
0039 #define CLK_STATUS7                     0x3D4
0040 #define SPLIT_DISPLAY_LOWER_PIPE_CTRL   0x3F0
0041 #define SPLIT_DISPLAY_TE_LINE_INTERVAL  0x3F4
0042 #define INTF_SW_RESET_MASK              0x3FC
0043 #define HDMI_DP_CORE_SELECT             0x408
0044 #define MDP_OUT_CTL_0                   0x410
0045 #define MDP_VSYNC_SEL                   0x414
0046 #define DCE_SEL                         0x450
0047
0048 #endif /*_DPU_HWIO_H */