disp/dpu1/dpu_hw_wb.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved
0004  */
0005
0006 #ifndef _DPU_HW_WB_H
0007 #define _DPU_HW_WB_H
0008
0009 #include "dpu_hw_catalog.h"
0010 #include "dpu_hw_mdss.h"
0011 #include "dpu_hw_top.h"
0012 #include "dpu_hw_util.h"
0013 #include "dpu_hw_pingpong.h"
0014
0015 struct dpu_hw_wb;
0016
0017 struct dpu_hw_wb_cfg {
0018     struct dpu_hw_fmt_layout dest;
0019     enum dpu_intf_mode intf_mode;
0020     struct drm_rect roi;
0021     struct drm_rect crop;
0022 };
0023
0024 /**
0025  * enum CDP preload ahead address size
0026  */
0027 enum {
0028     DPU_WB_CDP_PRELOAD_AHEAD_32,
0029     DPU_WB_CDP_PRELOAD_AHEAD_64
0030 };
0031
0032 /**
0033  * struct dpu_hw_wb_qos_cfg : Writeback pipe QoS configuration
0034  * @danger_lut: LUT for generate danger level based on fill level
0035  * @safe_lut: LUT for generate safe level based on fill level
0036  * @creq_lut: LUT for generate creq level based on fill level
0037  * @danger_safe_en: enable danger safe generation
0038  */
0039 struct dpu_hw_wb_qos_cfg {
0040     u32 danger_lut;
0041     u32 safe_lut;
0042     u64 creq_lut;
0043     bool danger_safe_en;
0044 };
0045
0046 /**
0047  *
0048  * struct dpu_hw_wb_ops : Interface to the wb hw driver functions
0049  *  Assumption is these functions will be called after clocks are enabled
0050  *  @setup_outaddress: setup output address from the writeback job
0051  *  @setup_outformat: setup output format of writeback block from writeback job
0052  *  @setup_qos_lut:   setup qos LUT for writeback block based on input
0053  *  @setup_cdp:       setup chroma down prefetch block for writeback block
0054  *  @bind_pingpong_blk: enable/disable the connection with ping-pong block
0055  */
0056 struct dpu_hw_wb_ops {
0057     void (*setup_outaddress)(struct dpu_hw_wb *ctx,
0058             struct dpu_hw_wb_cfg *wb);
0059
0060     void (*setup_outformat)(struct dpu_hw_wb *ctx,
0061             struct dpu_hw_wb_cfg *wb);
0062
0063     void (*setup_roi)(struct dpu_hw_wb *ctx,
0064             struct dpu_hw_wb_cfg *wb);
0065
0066     void (*setup_qos_lut)(struct dpu_hw_wb *ctx,
0067             struct dpu_hw_wb_qos_cfg *cfg);
0068
0069     void (*setup_cdp)(struct dpu_hw_wb *ctx,
0070             struct dpu_hw_cdp_cfg *cfg);
0071
0072     void (*bind_pingpong_blk)(struct dpu_hw_wb *ctx,
0073             bool enable, const enum dpu_pingpong pp);
0074 };
0075
0076 /**
0077  * struct dpu_hw_wb : WB driver object
0078  * @hw: block hardware details
0079  * @mdp: pointer to associated mdp portion of the catalog
0080  * @idx: hardware index number within type
0081  * @wb_hw_caps: hardware capabilities
0082  * @ops: function pointers
0083  * @hw_mdp: MDP top level hardware block
0084  */
0085 struct dpu_hw_wb {
0086     struct dpu_hw_blk_reg_map hw;
0087     const struct dpu_mdp_cfg *mdp;
0088
0089     /* wb path */
0090     int idx;
0091     const struct dpu_wb_cfg *caps;
0092
0093     /* ops */
0094     struct dpu_hw_wb_ops ops;
0095
0096     struct dpu_hw_mdp *hw_mdp;
0097 };
0098
0099 /**
0100  * dpu_hw_wb_init(): Initializes and return writeback hw driver object.
0101  * @idx:  wb_path index for which driver object is required
0102  * @addr: mapped register io address of MDP
0103  * @m :   pointer to mdss catalog data
0104  */
0105 struct dpu_hw_wb *dpu_hw_wb_init(enum dpu_wb idx,
0106         void __iomem *addr,
0107         const struct dpu_mdss_cfg *m);
0108
0109 /**
0110  * dpu_hw_wb_destroy(): Destroy writeback hw driver object.
0111  * @hw_wb:  Pointer to writeback hw driver object
0112  */
0113 void dpu_hw_wb_destroy(struct dpu_hw_wb *hw_wb);
0114
0115 #endif /*_DPU_HW_WB_H */