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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
0004  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
0005  */
0006 
0007 #ifndef _DPU_HW_UTIL_H
0008 #define _DPU_HW_UTIL_H
0009 
0010 #include <linux/io.h>
0011 #include <linux/slab.h>
0012 #include "dpu_hw_mdss.h"
0013 #include "dpu_hw_catalog.h"
0014 
0015 #define REG_MASK(n)                     ((BIT(n)) - 1)
0016 #define MISR_FRAME_COUNT_MASK           0xFF
0017 #define MISR_CTRL_ENABLE                BIT(8)
0018 #define MISR_CTRL_STATUS                BIT(9)
0019 #define MISR_CTRL_STATUS_CLEAR          BIT(10)
0020 #define MISR_CTRL_FREE_RUN_MASK         BIT(31)
0021 
0022 /*
0023  * This is the common struct maintained by each sub block
0024  * for mapping the register offsets in this block to the
0025  * absoulute IO address
0026  * @blk_addr:     hw block register mapped address
0027  * @log_mask:     log mask for this block
0028  */
0029 struct dpu_hw_blk_reg_map {
0030     void __iomem *blk_addr;
0031     u32 log_mask;
0032 };
0033 
0034 /**
0035  * struct dpu_hw_blk - opaque hardware block object
0036  */
0037 struct dpu_hw_blk {
0038     /* opaque */
0039 };
0040 
0041 /**
0042  * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
0043  * @enable:         detail enhancer enable/disable
0044  * @sharpen_level1: sharpening strength for noise
0045  * @sharpen_level2: sharpening strength for signal
0046  * @ clip:          clip shift
0047  * @ limit:         limit value
0048  * @ thr_quiet:     quiet threshold
0049  * @ thr_dieout:    dieout threshold
0050  * @ thr_high:      low threshold
0051  * @ thr_high:      high threshold
0052  * @ prec_shift:    precision shift
0053  * @ adjust_a:      A-coefficients for mapping curve
0054  * @ adjust_b:      B-coefficients for mapping curve
0055  * @ adjust_c:      C-coefficients for mapping curve
0056  */
0057 struct dpu_hw_scaler3_de_cfg {
0058     u32 enable;
0059     int16_t sharpen_level1;
0060     int16_t sharpen_level2;
0061     uint16_t clip;
0062     uint16_t limit;
0063     uint16_t thr_quiet;
0064     uint16_t thr_dieout;
0065     uint16_t thr_low;
0066     uint16_t thr_high;
0067     uint16_t prec_shift;
0068     int16_t adjust_a[DPU_MAX_DE_CURVES];
0069     int16_t adjust_b[DPU_MAX_DE_CURVES];
0070     int16_t adjust_c[DPU_MAX_DE_CURVES];
0071 };
0072 
0073 
0074 /**
0075  * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration
0076  * @enable:        scaler enable
0077  * @dir_en:        direction detection block enable
0078  * @ init_phase_x: horizontal initial phase
0079  * @ phase_step_x: horizontal phase step
0080  * @ init_phase_y: vertical initial phase
0081  * @ phase_step_y: vertical phase step
0082  * @ preload_x:    horizontal preload value
0083  * @ preload_y:    vertical preload value
0084  * @ src_width:    source width
0085  * @ src_height:   source height
0086  * @ dst_width:    destination width
0087  * @ dst_height:   destination height
0088  * @ y_rgb_filter_cfg: y/rgb plane filter configuration
0089  * @ uv_filter_cfg: uv plane filter configuration
0090  * @ alpha_filter_cfg: alpha filter configuration
0091  * @ blend_cfg:    blend coefficients configuration
0092  * @ lut_flag:     scaler LUT update flags
0093  *                 0x1 swap LUT bank
0094  *                 0x2 update 2D filter LUT
0095  *                 0x4 update y circular filter LUT
0096  *                 0x8 update uv circular filter LUT
0097  *                 0x10 update y separable filter LUT
0098  *                 0x20 update uv separable filter LUT
0099  * @ dir_lut_idx:  2D filter LUT index
0100  * @ y_rgb_cir_lut_idx: y circular filter LUT index
0101  * @ uv_cir_lut_idx: uv circular filter LUT index
0102  * @ y_rgb_sep_lut_idx: y circular filter LUT index
0103  * @ uv_sep_lut_idx: uv separable filter LUT index
0104  * @ dir_lut:      pointer to 2D LUT
0105  * @ cir_lut:      pointer to circular filter LUT
0106  * @ sep_lut:      pointer to separable filter LUT
0107  * @ de: detail enhancer configuration
0108  * @ dir_weight:   Directional weight
0109  */
0110 struct dpu_hw_scaler3_cfg {
0111     u32 enable;
0112     u32 dir_en;
0113     int32_t init_phase_x[DPU_MAX_PLANES];
0114     int32_t phase_step_x[DPU_MAX_PLANES];
0115     int32_t init_phase_y[DPU_MAX_PLANES];
0116     int32_t phase_step_y[DPU_MAX_PLANES];
0117 
0118     u32 preload_x[DPU_MAX_PLANES];
0119     u32 preload_y[DPU_MAX_PLANES];
0120     u32 src_width[DPU_MAX_PLANES];
0121     u32 src_height[DPU_MAX_PLANES];
0122 
0123     u32 dst_width;
0124     u32 dst_height;
0125 
0126     u32 y_rgb_filter_cfg;
0127     u32 uv_filter_cfg;
0128     u32 alpha_filter_cfg;
0129     u32 blend_cfg;
0130 
0131     u32 lut_flag;
0132     u32 dir_lut_idx;
0133 
0134     u32 y_rgb_cir_lut_idx;
0135     u32 uv_cir_lut_idx;
0136     u32 y_rgb_sep_lut_idx;
0137     u32 uv_sep_lut_idx;
0138     u32 *dir_lut;
0139     size_t dir_len;
0140     u32 *cir_lut;
0141     size_t cir_len;
0142     u32 *sep_lut;
0143     size_t sep_len;
0144 
0145     /*
0146      * Detail enhancer settings
0147      */
0148     struct dpu_hw_scaler3_de_cfg de;
0149 
0150     u32 dir_weight;
0151 };
0152 
0153 /**
0154  * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
0155  * @num_ext_pxls_lr: Number of total horizontal pixels
0156  * @num_ext_pxls_tb: Number of total vertical lines
0157  * @left_ftch:       Number of extra pixels to overfetch from left
0158  * @right_ftch:      Number of extra pixels to overfetch from right
0159  * @top_ftch:        Number of extra lines to overfetch from top
0160  * @btm_ftch:        Number of extra lines to overfetch from bottom
0161  * @left_rpt:        Number of extra pixels to repeat from left
0162  * @right_rpt:       Number of extra pixels to repeat from right
0163  * @top_rpt:         Number of extra lines to repeat from top
0164  * @btm_rpt:         Number of extra lines to repeat from bottom
0165  */
0166 struct dpu_drm_pix_ext_v1 {
0167     /*
0168      * Number of pixels ext in left, right, top and bottom direction
0169      * for all color components.
0170      */
0171     int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
0172     int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
0173 
0174     /*
0175      * Number of pixels needs to be overfetched in left, right, top
0176      * and bottom directions from source image for scaling.
0177      */
0178     int32_t left_ftch[DPU_MAX_PLANES];
0179     int32_t right_ftch[DPU_MAX_PLANES];
0180     int32_t top_ftch[DPU_MAX_PLANES];
0181     int32_t btm_ftch[DPU_MAX_PLANES];
0182     /*
0183      * Number of pixels needs to be repeated in left, right, top and
0184      * bottom directions for scaling.
0185      */
0186     int32_t left_rpt[DPU_MAX_PLANES];
0187     int32_t right_rpt[DPU_MAX_PLANES];
0188     int32_t top_rpt[DPU_MAX_PLANES];
0189     int32_t btm_rpt[DPU_MAX_PLANES];
0190 
0191 };
0192 
0193 /**
0194  * struct dpu_drm_de_v1 - version 1 of detail enhancer structure
0195  * @enable:         Enables/disables detail enhancer
0196  * @sharpen_level1: Sharpening strength for noise
0197  * @sharpen_level2: Sharpening strength for context
0198  * @clip:           Clip coefficient
0199  * @limit:          Detail enhancer limit factor
0200  * @thr_quiet:      Quite zone threshold
0201  * @thr_dieout:     Die-out zone threshold
0202  * @thr_low:        Linear zone left threshold
0203  * @thr_high:       Linear zone right threshold
0204  * @prec_shift:     Detail enhancer precision
0205  * @adjust_a:       Mapping curves A coefficients
0206  * @adjust_b:       Mapping curves B coefficients
0207  * @adjust_c:       Mapping curves C coefficients
0208  */
0209 struct dpu_drm_de_v1 {
0210     uint32_t enable;
0211     int16_t sharpen_level1;
0212     int16_t sharpen_level2;
0213     uint16_t clip;
0214     uint16_t limit;
0215     uint16_t thr_quiet;
0216     uint16_t thr_dieout;
0217     uint16_t thr_low;
0218     uint16_t thr_high;
0219     uint16_t prec_shift;
0220     int16_t adjust_a[DPU_MAX_DE_CURVES];
0221     int16_t adjust_b[DPU_MAX_DE_CURVES];
0222     int16_t adjust_c[DPU_MAX_DE_CURVES];
0223 };
0224 
0225 /**
0226  * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
0227  * @enable:            Scaler enable
0228  * @dir_en:            Detail enhancer enable
0229  * @pe:                Pixel extension settings
0230  * @horz_decimate:     Horizontal decimation factor
0231  * @vert_decimate:     Vertical decimation factor
0232  * @init_phase_x:      Initial scaler phase values for x
0233  * @phase_step_x:      Phase step values for x
0234  * @init_phase_y:      Initial scaler phase values for y
0235  * @phase_step_y:      Phase step values for y
0236  * @preload_x:         Horizontal preload value
0237  * @preload_y:         Vertical preload value
0238  * @src_width:         Source width
0239  * @src_height:        Source height
0240  * @dst_width:         Destination width
0241  * @dst_height:        Destination height
0242  * @y_rgb_filter_cfg:  Y/RGB plane filter configuration
0243  * @uv_filter_cfg:     UV plane filter configuration
0244  * @alpha_filter_cfg:  Alpha filter configuration
0245  * @blend_cfg:         Selection of blend coefficients
0246  * @lut_flag:          LUT configuration flags
0247  * @dir_lut_idx:       2d 4x4 LUT index
0248  * @y_rgb_cir_lut_idx: Y/RGB circular LUT index
0249  * @uv_cir_lut_idx:    UV circular LUT index
0250  * @y_rgb_sep_lut_idx: Y/RGB separable LUT index
0251  * @uv_sep_lut_idx:    UV separable LUT index
0252  * @de:                Detail enhancer settings
0253  */
0254 struct dpu_drm_scaler_v2 {
0255     /*
0256      * General definitions
0257      */
0258     uint32_t enable;
0259     uint32_t dir_en;
0260 
0261     /*
0262      * Pix ext settings
0263      */
0264     struct dpu_drm_pix_ext_v1 pe;
0265 
0266     /*
0267      * Decimation settings
0268      */
0269     uint32_t horz_decimate;
0270     uint32_t vert_decimate;
0271 
0272     /*
0273      * Phase settings
0274      */
0275     int32_t init_phase_x[DPU_MAX_PLANES];
0276     int32_t phase_step_x[DPU_MAX_PLANES];
0277     int32_t init_phase_y[DPU_MAX_PLANES];
0278     int32_t phase_step_y[DPU_MAX_PLANES];
0279 
0280     uint32_t preload_x[DPU_MAX_PLANES];
0281     uint32_t preload_y[DPU_MAX_PLANES];
0282     uint32_t src_width[DPU_MAX_PLANES];
0283     uint32_t src_height[DPU_MAX_PLANES];
0284 
0285     uint32_t dst_width;
0286     uint32_t dst_height;
0287 
0288     uint32_t y_rgb_filter_cfg;
0289     uint32_t uv_filter_cfg;
0290     uint32_t alpha_filter_cfg;
0291     uint32_t blend_cfg;
0292 
0293     uint32_t lut_flag;
0294     uint32_t dir_lut_idx;
0295 
0296     /* for Y(RGB) and UV planes*/
0297     uint32_t y_rgb_cir_lut_idx;
0298     uint32_t uv_cir_lut_idx;
0299     uint32_t y_rgb_sep_lut_idx;
0300     uint32_t uv_sep_lut_idx;
0301 
0302     /*
0303      * Detail enhancer settings
0304      */
0305     struct dpu_drm_de_v1 de;
0306 };
0307 
0308 /**
0309  * struct dpu_hw_cdp_cfg : CDP configuration
0310  * @enable: true to enable CDP
0311  * @ubwc_meta_enable: true to enable ubwc metadata preload
0312  * @tile_amortize_enable: true to enable amortization control for tile format
0313  * @preload_ahead: number of request to preload ahead
0314  *  DPU_*_CDP_PRELOAD_AHEAD_32,
0315  *  DPU_*_CDP_PRELOAD_AHEAD_64
0316  */
0317 struct dpu_hw_cdp_cfg {
0318     bool enable;
0319     bool ubwc_meta_enable;
0320     bool tile_amortize_enable;
0321     u32 preload_ahead;
0322 };
0323 
0324 u32 *dpu_hw_util_get_log_mask_ptr(void);
0325 
0326 void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
0327         u32 reg_off,
0328         u32 val,
0329         const char *name);
0330 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
0331 
0332 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
0333 #define DPU_REG_READ(c, off) dpu_reg_read(c, off)
0334 
0335 void *dpu_hw_util_get_dir(void);
0336 
0337 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
0338         struct dpu_hw_scaler3_cfg *scaler3_cfg,
0339         u32 scaler_offset, u32 scaler_version,
0340         const struct dpu_format *format);
0341 
0342 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
0343         u32 scaler_offset);
0344 
0345 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
0346         u32 csc_reg_off,
0347         const struct dpu_csc_cfg *data, bool csc10);
0348 
0349 u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
0350         u32 total_fl);
0351 
0352 void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
0353         u32 misr_ctrl_offset,
0354         bool enable,
0355         u32 frame_count);
0356 
0357 int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
0358         u32 misr_ctrl_offset,
0359         u32 misr_signature_offset,
0360         u32 *misr_value);
0361 
0362 #endif /* _DPU_HW_UTIL_H */
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