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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
0004  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0005  */
0006 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
0007 
0008 #include "msm_drv.h"
0009 #include "dpu_kms.h"
0010 #include "dpu_hw_mdss.h"
0011 #include "dpu_hw_util.h"
0012 
0013 /* using a file static variables for debugfs access */
0014 static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE;
0015 
0016 /* DPU_SCALER_QSEED3 */
0017 #define QSEED3_HW_VERSION                  0x00
0018 #define QSEED3_OP_MODE                     0x04
0019 #define QSEED3_RGB2Y_COEFF                 0x08
0020 #define QSEED3_PHASE_INIT                  0x0C
0021 #define QSEED3_PHASE_STEP_Y_H              0x10
0022 #define QSEED3_PHASE_STEP_Y_V              0x14
0023 #define QSEED3_PHASE_STEP_UV_H             0x18
0024 #define QSEED3_PHASE_STEP_UV_V             0x1C
0025 #define QSEED3_PRELOAD                     0x20
0026 #define QSEED3_DE_SHARPEN                  0x24
0027 #define QSEED3_DE_SHARPEN_CTL              0x28
0028 #define QSEED3_DE_SHAPE_CTL                0x2C
0029 #define QSEED3_DE_THRESHOLD                0x30
0030 #define QSEED3_DE_ADJUST_DATA_0            0x34
0031 #define QSEED3_DE_ADJUST_DATA_1            0x38
0032 #define QSEED3_DE_ADJUST_DATA_2            0x3C
0033 #define QSEED3_SRC_SIZE_Y_RGB_A            0x40
0034 #define QSEED3_SRC_SIZE_UV                 0x44
0035 #define QSEED3_DST_SIZE                    0x48
0036 #define QSEED3_COEF_LUT_CTRL               0x4C
0037 #define QSEED3_COEF_LUT_SWAP_BIT           0
0038 #define QSEED3_COEF_LUT_DIR_BIT            1
0039 #define QSEED3_COEF_LUT_Y_CIR_BIT          2
0040 #define QSEED3_COEF_LUT_UV_CIR_BIT         3
0041 #define QSEED3_COEF_LUT_Y_SEP_BIT          4
0042 #define QSEED3_COEF_LUT_UV_SEP_BIT         5
0043 #define QSEED3_BUFFER_CTRL                 0x50
0044 #define QSEED3_CLK_CTRL0                   0x54
0045 #define QSEED3_CLK_CTRL1                   0x58
0046 #define QSEED3_CLK_STATUS                  0x5C
0047 #define QSEED3_PHASE_INIT_Y_H              0x90
0048 #define QSEED3_PHASE_INIT_Y_V              0x94
0049 #define QSEED3_PHASE_INIT_UV_H             0x98
0050 #define QSEED3_PHASE_INIT_UV_V             0x9C
0051 #define QSEED3_COEF_LUT                    0x100
0052 #define QSEED3_FILTERS                     5
0053 #define QSEED3_LUT_REGIONS                 4
0054 #define QSEED3_CIRCULAR_LUTS               9
0055 #define QSEED3_SEPARABLE_LUTS              10
0056 #define QSEED3_LUT_SIZE                    60
0057 #define QSEED3_ENABLE                      2
0058 #define QSEED3_DIR_LUT_SIZE                (200 * sizeof(u32))
0059 #define QSEED3_CIR_LUT_SIZE \
0060     (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32))
0061 #define QSEED3_SEP_LUT_SIZE \
0062     (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32))
0063 
0064 /* DPU_SCALER_QSEED3LITE */
0065 #define QSEED3LITE_COEF_LUT_Y_SEP_BIT         4
0066 #define QSEED3LITE_COEF_LUT_UV_SEP_BIT        5
0067 #define QSEED3LITE_COEF_LUT_CTRL              0x4C
0068 #define QSEED3LITE_COEF_LUT_SWAP_BIT          0
0069 #define QSEED3LITE_DIR_FILTER_WEIGHT          0x60
0070 #define QSEED3LITE_FILTERS                 2
0071 #define QSEED3LITE_SEPARABLE_LUTS             10
0072 #define QSEED3LITE_LUT_SIZE                   33
0073 #define QSEED3LITE_SEP_LUT_SIZE \
0074             (QSEED3LITE_LUT_SIZE * QSEED3LITE_SEPARABLE_LUTS * sizeof(u32))
0075 
0076 
0077 void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
0078         u32 reg_off,
0079         u32 val,
0080         const char *name)
0081 {
0082     /* don't need to mutex protect this */
0083     if (c->log_mask & dpu_hw_util_log_mask)
0084         DPU_DEBUG_DRIVER("[%s:0x%X] <= 0x%X\n",
0085                 name, reg_off, val);
0086     writel_relaxed(val, c->blk_addr + reg_off);
0087 }
0088 
0089 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off)
0090 {
0091     return readl_relaxed(c->blk_addr + reg_off);
0092 }
0093 
0094 u32 *dpu_hw_util_get_log_mask_ptr(void)
0095 {
0096     return &dpu_hw_util_log_mask;
0097 }
0098 
0099 static void _dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map *c,
0100         struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset)
0101 {
0102     int i, j, filter;
0103     int config_lut = 0x0;
0104     unsigned long lut_flags;
0105     u32 lut_addr, lut_offset, lut_len;
0106     u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL};
0107     static const uint32_t off_tbl[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = {
0108         {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} },
0109         {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} },
0110         {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} },
0111         {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} },
0112         {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} },
0113     };
0114 
0115     lut_flags = (unsigned long) scaler3_cfg->lut_flag;
0116     if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) &&
0117         (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
0118         lut[0] = scaler3_cfg->dir_lut;
0119         config_lut = 1;
0120     }
0121     if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) &&
0122         (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
0123         (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
0124         lut[1] = scaler3_cfg->cir_lut +
0125             scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
0126         config_lut = 1;
0127     }
0128     if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) &&
0129         (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
0130         (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
0131         lut[2] = scaler3_cfg->cir_lut +
0132             scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
0133         config_lut = 1;
0134     }
0135     if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
0136         (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
0137         (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
0138         lut[3] = scaler3_cfg->sep_lut +
0139             scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
0140         config_lut = 1;
0141     }
0142     if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
0143         (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
0144         (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
0145         lut[4] = scaler3_cfg->sep_lut +
0146             scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
0147         config_lut = 1;
0148     }
0149 
0150     if (config_lut) {
0151         for (filter = 0; filter < QSEED3_FILTERS; filter++) {
0152             if (!lut[filter])
0153                 continue;
0154             lut_offset = 0;
0155             for (i = 0; i < QSEED3_LUT_REGIONS; i++) {
0156                 lut_addr = QSEED3_COEF_LUT + offset
0157                     + off_tbl[filter][i][1];
0158                 lut_len = off_tbl[filter][i][0] << 2;
0159                 for (j = 0; j < lut_len; j++) {
0160                     DPU_REG_WRITE(c,
0161                         lut_addr,
0162                         (lut[filter])[lut_offset++]);
0163                     lut_addr += 4;
0164                 }
0165             }
0166         }
0167     }
0168 
0169     if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
0170         DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));
0171 
0172 }
0173 
0174 static void _dpu_hw_setup_scaler3lite_lut(struct dpu_hw_blk_reg_map *c,
0175         struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset)
0176 {
0177     int j, filter;
0178     int config_lut = 0x0;
0179     unsigned long lut_flags;
0180     u32 lut_addr, lut_offset;
0181     u32 *lut[QSEED3LITE_FILTERS] = {NULL, NULL};
0182     static const uint32_t off_tbl[QSEED3_FILTERS] = { 0x000, 0x200 };
0183 
0184     DPU_REG_WRITE(c, QSEED3LITE_DIR_FILTER_WEIGHT + offset, scaler3_cfg->dir_weight);
0185 
0186     if (!scaler3_cfg->sep_lut)
0187         return;
0188 
0189     lut_flags = (unsigned long) scaler3_cfg->lut_flag;
0190     if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
0191         (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3LITE_SEPARABLE_LUTS) &&
0192         (scaler3_cfg->sep_len == QSEED3LITE_SEP_LUT_SIZE)) {
0193         lut[0] = scaler3_cfg->sep_lut +
0194             scaler3_cfg->y_rgb_sep_lut_idx * QSEED3LITE_LUT_SIZE;
0195         config_lut = 1;
0196     }
0197     if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
0198         (scaler3_cfg->uv_sep_lut_idx < QSEED3LITE_SEPARABLE_LUTS) &&
0199         (scaler3_cfg->sep_len == QSEED3LITE_SEP_LUT_SIZE)) {
0200         lut[1] = scaler3_cfg->sep_lut +
0201             scaler3_cfg->uv_sep_lut_idx * QSEED3LITE_LUT_SIZE;
0202         config_lut = 1;
0203     }
0204 
0205     if (config_lut) {
0206         for (filter = 0; filter < QSEED3LITE_FILTERS; filter++) {
0207             if (!lut[filter])
0208                 continue;
0209             lut_offset = 0;
0210             lut_addr = QSEED3_COEF_LUT + offset + off_tbl[filter];
0211             for (j = 0; j < QSEED3LITE_LUT_SIZE; j++) {
0212                 DPU_REG_WRITE(c,
0213                     lut_addr,
0214                     (lut[filter])[lut_offset++]);
0215                 lut_addr += 4;
0216             }
0217         }
0218     }
0219 
0220     if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
0221         DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));
0222 
0223 }
0224 
0225 static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c,
0226         struct dpu_hw_scaler3_de_cfg *de_cfg, u32 offset)
0227 {
0228     u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr;
0229     u32 adjust_a, adjust_b, adjust_c;
0230 
0231     if (!de_cfg->enable)
0232         return;
0233 
0234     sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) |
0235         ((de_cfg->sharpen_level2 & 0x1FF) << 16);
0236 
0237     sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
0238         ((de_cfg->prec_shift & 0x7) << 13) |
0239         ((de_cfg->clip & 0x7) << 16);
0240 
0241     shape_ctl = (de_cfg->thr_quiet & 0xFF) |
0242         ((de_cfg->thr_dieout & 0x3FF) << 16);
0243 
0244     de_thr = (de_cfg->thr_low & 0x3FF) |
0245         ((de_cfg->thr_high & 0x3FF) << 16);
0246 
0247     adjust_a = (de_cfg->adjust_a[0] & 0x3FF) |
0248         ((de_cfg->adjust_a[1] & 0x3FF) << 10) |
0249         ((de_cfg->adjust_a[2] & 0x3FF) << 20);
0250 
0251     adjust_b = (de_cfg->adjust_b[0] & 0x3FF) |
0252         ((de_cfg->adjust_b[1] & 0x3FF) << 10) |
0253         ((de_cfg->adjust_b[2] & 0x3FF) << 20);
0254 
0255     adjust_c = (de_cfg->adjust_c[0] & 0x3FF) |
0256         ((de_cfg->adjust_c[1] & 0x3FF) << 10) |
0257         ((de_cfg->adjust_c[2] & 0x3FF) << 20);
0258 
0259     DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl);
0260     DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl);
0261     DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl);
0262     DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr);
0263     DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a);
0264     DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b);
0265     DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c);
0266 
0267 }
0268 
0269 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
0270         struct dpu_hw_scaler3_cfg *scaler3_cfg,
0271         u32 scaler_offset, u32 scaler_version,
0272         const struct dpu_format *format)
0273 {
0274     u32 op_mode = 0;
0275     u32 phase_init, preload, src_y_rgb, src_uv, dst;
0276 
0277     if (!scaler3_cfg->enable)
0278         goto end;
0279 
0280     op_mode |= BIT(0);
0281     op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
0282 
0283     if (format && DPU_FORMAT_IS_YUV(format)) {
0284         op_mode |= BIT(12);
0285         op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
0286     }
0287 
0288     op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
0289     op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
0290 
0291     preload =
0292         ((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
0293         ((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
0294         ((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
0295         ((scaler3_cfg->preload_y[1] & 0x7F) << 24);
0296 
0297     src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
0298         ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
0299 
0300     src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
0301         ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
0302 
0303     dst = (scaler3_cfg->dst_width & 0x1FFFF) |
0304         ((scaler3_cfg->dst_height & 0x1FFFF) << 16);
0305 
0306     if (scaler3_cfg->de.enable) {
0307         _dpu_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset);
0308         op_mode |= BIT(8);
0309     }
0310 
0311     if (scaler3_cfg->lut_flag) {
0312         if (scaler_version < 0x2004)
0313             _dpu_hw_setup_scaler3_lut(c, scaler3_cfg, scaler_offset);
0314         else
0315             _dpu_hw_setup_scaler3lite_lut(c, scaler3_cfg, scaler_offset);
0316     }
0317 
0318     if (scaler_version == 0x1002) {
0319         phase_init =
0320             ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
0321             ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
0322             ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
0323             ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
0324         DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init);
0325     } else {
0326         DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset,
0327             scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
0328         DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset,
0329             scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
0330         DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset,
0331             scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
0332         DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset,
0333             scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
0334     }
0335 
0336     DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset,
0337         scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
0338 
0339     DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset,
0340         scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
0341 
0342     DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset,
0343         scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
0344 
0345     DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset,
0346         scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
0347 
0348     DPU_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload);
0349 
0350     DPU_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb);
0351 
0352     DPU_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv);
0353 
0354     DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
0355 
0356 end:
0357     if (format && !DPU_FORMAT_IS_DX(format))
0358         op_mode |= BIT(14);
0359 
0360     if (format && format->alpha_enable) {
0361         op_mode |= BIT(10);
0362         if (scaler_version == 0x1002)
0363             op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
0364         else
0365             op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
0366     }
0367 
0368     DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);
0369 }
0370 
0371 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
0372             u32 scaler_offset)
0373 {
0374     return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset);
0375 }
0376 
0377 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
0378         u32 csc_reg_off,
0379         const struct dpu_csc_cfg *data, bool csc10)
0380 {
0381     static const u32 matrix_shift = 7;
0382     u32 clamp_shift = csc10 ? 16 : 8;
0383     u32 val;
0384 
0385     /* matrix coeff - convert S15.16 to S4.9 */
0386     val = ((data->csc_mv[0] >> matrix_shift) & 0x1FFF) |
0387         (((data->csc_mv[1] >> matrix_shift) & 0x1FFF) << 16);
0388     DPU_REG_WRITE(c, csc_reg_off, val);
0389     val = ((data->csc_mv[2] >> matrix_shift) & 0x1FFF) |
0390         (((data->csc_mv[3] >> matrix_shift) & 0x1FFF) << 16);
0391     DPU_REG_WRITE(c, csc_reg_off + 0x4, val);
0392     val = ((data->csc_mv[4] >> matrix_shift) & 0x1FFF) |
0393         (((data->csc_mv[5] >> matrix_shift) & 0x1FFF) << 16);
0394     DPU_REG_WRITE(c, csc_reg_off + 0x8, val);
0395     val = ((data->csc_mv[6] >> matrix_shift) & 0x1FFF) |
0396         (((data->csc_mv[7] >> matrix_shift) & 0x1FFF) << 16);
0397     DPU_REG_WRITE(c, csc_reg_off + 0xc, val);
0398     val = (data->csc_mv[8] >> matrix_shift) & 0x1FFF;
0399     DPU_REG_WRITE(c, csc_reg_off + 0x10, val);
0400 
0401     /* Pre clamp */
0402     val = (data->csc_pre_lv[0] << clamp_shift) | data->csc_pre_lv[1];
0403     DPU_REG_WRITE(c, csc_reg_off + 0x14, val);
0404     val = (data->csc_pre_lv[2] << clamp_shift) | data->csc_pre_lv[3];
0405     DPU_REG_WRITE(c, csc_reg_off + 0x18, val);
0406     val = (data->csc_pre_lv[4] << clamp_shift) | data->csc_pre_lv[5];
0407     DPU_REG_WRITE(c, csc_reg_off + 0x1c, val);
0408 
0409     /* Post clamp */
0410     val = (data->csc_post_lv[0] << clamp_shift) | data->csc_post_lv[1];
0411     DPU_REG_WRITE(c, csc_reg_off + 0x20, val);
0412     val = (data->csc_post_lv[2] << clamp_shift) | data->csc_post_lv[3];
0413     DPU_REG_WRITE(c, csc_reg_off + 0x24, val);
0414     val = (data->csc_post_lv[4] << clamp_shift) | data->csc_post_lv[5];
0415     DPU_REG_WRITE(c, csc_reg_off + 0x28, val);
0416 
0417     /* Pre-Bias */
0418     DPU_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]);
0419     DPU_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]);
0420     DPU_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]);
0421 
0422     /* Post-Bias */
0423     DPU_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]);
0424     DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
0425     DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
0426 }
0427 
0428 /**
0429  * _dpu_hw_get_qos_lut - get LUT mapping based on fill level
0430  * @tbl:        Pointer to LUT table
0431  * @total_fl:       fill level
0432  * Return: LUT setting corresponding to the fill level
0433  */
0434 u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
0435         u32 total_fl)
0436 {
0437     int i;
0438 
0439     if (!tbl || !tbl->nentry || !tbl->entries)
0440         return 0;
0441 
0442     for (i = 0; i < tbl->nentry; i++)
0443         if (total_fl <= tbl->entries[i].fl)
0444             return tbl->entries[i].lut;
0445 
0446     /* if last fl is zero, use as default */
0447     if (!tbl->entries[i-1].fl)
0448         return tbl->entries[i-1].lut;
0449 
0450     return 0;
0451 }
0452 
0453 void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
0454         u32 misr_ctrl_offset,
0455         bool enable, u32 frame_count)
0456 {
0457     u32 config = 0;
0458 
0459     DPU_REG_WRITE(c, misr_ctrl_offset, MISR_CTRL_STATUS_CLEAR);
0460 
0461     /* Clear old MISR value (in case it's read before a new value is calculated)*/
0462     wmb();
0463 
0464     if (enable) {
0465         config = (frame_count & MISR_FRAME_COUNT_MASK) |
0466             MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK;
0467 
0468         DPU_REG_WRITE(c, misr_ctrl_offset, config);
0469     } else {
0470         DPU_REG_WRITE(c, misr_ctrl_offset, 0);
0471     }
0472 
0473 }
0474 
0475 int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
0476         u32 misr_ctrl_offset,
0477         u32 misr_signature_offset,
0478         u32 *misr_value)
0479 {
0480     u32 ctrl = 0;
0481 
0482     if (!misr_value)
0483         return -EINVAL;
0484 
0485     ctrl = DPU_REG_READ(c, misr_ctrl_offset);
0486 
0487     if (!(ctrl & MISR_CTRL_ENABLE))
0488         return -ENODATA;
0489 
0490     if (!(ctrl & MISR_CTRL_STATUS))
0491         return -EINVAL;
0492 
0493     *misr_value = DPU_REG_READ(c, misr_signature_offset);
0494 
0495     return 0;
0496 }
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