disp/dpu1/dpu_hw_top.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0003  */
0004
0005 #include "dpu_hwio.h"
0006 #include "dpu_hw_catalog.h"
0007 #include "dpu_hw_top.h"
0008 #include "dpu_kms.h"
0009
0010 #define SSPP_SPARE                        0x28
0011
0012 #define FLD_SPLIT_DISPLAY_CMD             BIT(1)
0013 #define FLD_SMART_PANEL_FREE_RUN          BIT(2)
0014 #define FLD_INTF_1_SW_TRG_MUX             BIT(4)
0015 #define FLD_INTF_2_SW_TRG_MUX             BIT(8)
0016 #define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0xFFFF
0017
0018 #define DANGER_STATUS                     0x360
0019 #define SAFE_STATUS                       0x364
0020
0021 #define TE_LINE_INTERVAL                  0x3F4
0022
0023 #define TRAFFIC_SHAPER_EN                 BIT(31)
0024 #define TRAFFIC_SHAPER_RD_CLIENT(num)     (0x030 + (num * 4))
0025 #define TRAFFIC_SHAPER_WR_CLIENT(num)     (0x060 + (num * 4))
0026 #define TRAFFIC_SHAPER_FIXPOINT_FACTOR    4
0027
0028 #define MDP_WD_TIMER_0_CTL                0x380
0029 #define MDP_WD_TIMER_0_CTL2               0x384
0030 #define MDP_WD_TIMER_0_LOAD_VALUE         0x388
0031 #define MDP_WD_TIMER_1_CTL                0x390
0032 #define MDP_WD_TIMER_1_CTL2               0x394
0033 #define MDP_WD_TIMER_1_LOAD_VALUE         0x398
0034 #define MDP_WD_TIMER_2_CTL                0x420
0035 #define MDP_WD_TIMER_2_CTL2               0x424
0036 #define MDP_WD_TIMER_2_LOAD_VALUE         0x428
0037 #define MDP_WD_TIMER_3_CTL                0x430
0038 #define MDP_WD_TIMER_3_CTL2               0x434
0039 #define MDP_WD_TIMER_3_LOAD_VALUE         0x438
0040 #define MDP_WD_TIMER_4_CTL                0x440
0041 #define MDP_WD_TIMER_4_CTL2               0x444
0042 #define MDP_WD_TIMER_4_LOAD_VALUE         0x448
0043
0044 #define MDP_TICK_COUNT                    16
0045 #define XO_CLK_RATE                       19200
0046 #define MS_TICKS_IN_SEC                   1000
0047
0048 #define CALCULATE_WD_LOAD_VALUE(fps) \
0049     ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
0050
0051 #define DCE_SEL                           0x450
0052
0053 static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
0054         struct split_pipe_cfg *cfg)
0055 {
0056     struct dpu_hw_blk_reg_map *c;
0057     u32 upper_pipe = 0;
0058     u32 lower_pipe = 0;
0059
0060     if (!mdp || !cfg)
0061         return;
0062
0063     c = &mdp->hw;
0064
0065     if (cfg->en) {
0066         if (cfg->mode == INTF_MODE_CMD) {
0067             lower_pipe = FLD_SPLIT_DISPLAY_CMD;
0068             /* interface controlling sw trigger */
0069             if (cfg->intf == INTF_2)
0070                 lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
0071             else
0072                 lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
0073             upper_pipe = lower_pipe;
0074         } else {
0075             if (cfg->intf == INTF_2) {
0076                 lower_pipe = FLD_INTF_1_SW_TRG_MUX;
0077                 upper_pipe = FLD_INTF_2_SW_TRG_MUX;
0078             } else {
0079                 lower_pipe = FLD_INTF_2_SW_TRG_MUX;
0080                 upper_pipe = FLD_INTF_1_SW_TRG_MUX;
0081             }
0082         }
0083     }
0084
0085     DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);
0086     DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);
0087     DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);
0088     DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
0089 }
0090
0091 static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
0092         enum dpu_clk_ctrl_type clk_ctrl, bool enable)
0093 {
0094     struct dpu_hw_blk_reg_map *c;
0095     u32 reg_off, bit_off;
0096     u32 reg_val, new_val;
0097     bool clk_forced_on;
0098
0099     if (!mdp)
0100         return false;
0101
0102     c = &mdp->hw;
0103
0104     if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX)
0105         return false;
0106
0107     reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
0108     bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
0109
0110     reg_val = DPU_REG_READ(c, reg_off);
0111
0112     if (enable)
0113         new_val = reg_val | BIT(bit_off);
0114     else
0115         new_val = reg_val & ~BIT(bit_off);
0116
0117     DPU_REG_WRITE(c, reg_off, new_val);
0118
0119     clk_forced_on = !(reg_val & BIT(bit_off));
0120
0121     return clk_forced_on;
0122 }
0123
0124
0125 static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp,
0126         struct dpu_danger_safe_status *status)
0127 {
0128     struct dpu_hw_blk_reg_map *c;
0129     u32 value;
0130
0131     if (!mdp || !status)
0132         return;
0133
0134     c = &mdp->hw;
0135
0136     value = DPU_REG_READ(c, DANGER_STATUS);
0137     status->mdp = (value >> 0) & 0x3;
0138     status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
0139     status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;
0140     status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;
0141     status->sspp[SSPP_VIG3] = (value >> 10) & 0x3;
0142     status->sspp[SSPP_RGB0] = (value >> 12) & 0x3;
0143     status->sspp[SSPP_RGB1] = (value >> 14) & 0x3;
0144     status->sspp[SSPP_RGB2] = (value >> 16) & 0x3;
0145     status->sspp[SSPP_RGB3] = (value >> 18) & 0x3;
0146     status->sspp[SSPP_DMA0] = (value >> 20) & 0x3;
0147     status->sspp[SSPP_DMA1] = (value >> 22) & 0x3;
0148     status->sspp[SSPP_DMA2] = (value >> 28) & 0x3;
0149     status->sspp[SSPP_DMA3] = (value >> 30) & 0x3;
0150     status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3;
0151     status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3;
0152 }
0153
0154 static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
0155         struct dpu_vsync_source_cfg *cfg)
0156 {
0157     struct dpu_hw_blk_reg_map *c;
0158     u32 reg, wd_load_value, wd_ctl, wd_ctl2, i;
0159     static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18};
0160
0161     if (!mdp || !cfg || (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber)))
0162         return;
0163
0164     c = &mdp->hw;
0165     reg = DPU_REG_READ(c, MDP_VSYNC_SEL);
0166     for (i = 0; i < cfg->pp_count; i++) {
0167         int pp_idx = cfg->ppnumber[i] - PINGPONG_0;
0168
0169         if (pp_idx >= ARRAY_SIZE(pp_offset))
0170             continue;
0171
0172         reg &= ~(0xf << pp_offset[pp_idx]);
0173         reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx];
0174     }
0175     DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg);
0176
0177     if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 &&
0178             cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) {
0179         switch (cfg->vsync_source) {
0180         case DPU_VSYNC_SOURCE_WD_TIMER_4:
0181             wd_load_value = MDP_WD_TIMER_4_LOAD_VALUE;
0182             wd_ctl = MDP_WD_TIMER_4_CTL;
0183             wd_ctl2 = MDP_WD_TIMER_4_CTL2;
0184             break;
0185         case DPU_VSYNC_SOURCE_WD_TIMER_3:
0186             wd_load_value = MDP_WD_TIMER_3_LOAD_VALUE;
0187             wd_ctl = MDP_WD_TIMER_3_CTL;
0188             wd_ctl2 = MDP_WD_TIMER_3_CTL2;
0189             break;
0190         case DPU_VSYNC_SOURCE_WD_TIMER_2:
0191             wd_load_value = MDP_WD_TIMER_2_LOAD_VALUE;
0192             wd_ctl = MDP_WD_TIMER_2_CTL;
0193             wd_ctl2 = MDP_WD_TIMER_2_CTL2;
0194             break;
0195         case DPU_VSYNC_SOURCE_WD_TIMER_1:
0196             wd_load_value = MDP_WD_TIMER_1_LOAD_VALUE;
0197             wd_ctl = MDP_WD_TIMER_1_CTL;
0198             wd_ctl2 = MDP_WD_TIMER_1_CTL2;
0199             break;
0200         case DPU_VSYNC_SOURCE_WD_TIMER_0:
0201         default:
0202             wd_load_value = MDP_WD_TIMER_0_LOAD_VALUE;
0203             wd_ctl = MDP_WD_TIMER_0_CTL;
0204             wd_ctl2 = MDP_WD_TIMER_0_CTL2;
0205             break;
0206         }
0207
0208         DPU_REG_WRITE(c, wd_load_value,
0209             CALCULATE_WD_LOAD_VALUE(cfg->frame_rate));
0210
0211         DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */
0212         reg = DPU_REG_READ(c, wd_ctl2);
0213         reg |= BIT(8);      /* enable heartbeat timer */
0214         reg |= BIT(0);      /* enable WD timer */
0215         DPU_REG_WRITE(c, wd_ctl2, reg);
0216
0217         /* make sure that timers are enabled/disabled for vsync state */
0218         wmb();
0219     }
0220 }
0221
0222 static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
0223         struct dpu_danger_safe_status *status)
0224 {
0225     struct dpu_hw_blk_reg_map *c;
0226     u32 value;
0227
0228     if (!mdp || !status)
0229         return;
0230
0231     c = &mdp->hw;
0232
0233     value = DPU_REG_READ(c, SAFE_STATUS);
0234     status->mdp = (value >> 0) & 0x1;
0235     status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
0236     status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;
0237     status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;
0238     status->sspp[SSPP_VIG3] = (value >> 10) & 0x1;
0239     status->sspp[SSPP_RGB0] = (value >> 12) & 0x1;
0240     status->sspp[SSPP_RGB1] = (value >> 14) & 0x1;
0241     status->sspp[SSPP_RGB2] = (value >> 16) & 0x1;
0242     status->sspp[SSPP_RGB3] = (value >> 18) & 0x1;
0243     status->sspp[SSPP_DMA0] = (value >> 20) & 0x1;
0244     status->sspp[SSPP_DMA1] = (value >> 22) & 0x1;
0245     status->sspp[SSPP_DMA2] = (value >> 28) & 0x1;
0246     status->sspp[SSPP_DMA3] = (value >> 30) & 0x1;
0247     status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1;
0248     status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
0249 }
0250
0251 static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp)
0252 {
0253     struct dpu_hw_blk_reg_map *c;
0254
0255     if (!mdp)
0256         return;
0257
0258     c = &mdp->hw;
0259
0260     DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);
0261 }
0262
0263 static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
0264         unsigned long cap)
0265 {
0266     ops->setup_split_pipe = dpu_hw_setup_split_pipe;
0267     ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
0268     ops->get_danger_status = dpu_hw_get_danger_status;
0269     ops->setup_vsync_source = dpu_hw_setup_vsync_source;
0270     ops->get_safe_status = dpu_hw_get_safe_status;
0271
0272     if (cap & BIT(DPU_MDP_AUDIO_SELECT))
0273         ops->intf_audio_select = dpu_hw_intf_audio_select;
0274 }
0275
0276 static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp,
0277         const struct dpu_mdss_cfg *m,
0278         void __iomem *addr,
0279         struct dpu_hw_blk_reg_map *b)
0280 {
0281     int i;
0282
0283     if (!m || !addr || !b)
0284         return ERR_PTR(-EINVAL);
0285
0286     for (i = 0; i < m->mdp_count; i++) {
0287         if (mdp == m->mdp[i].id) {
0288             b->blk_addr = addr + m->mdp[i].base;
0289             b->log_mask = DPU_DBG_MASK_TOP;
0290             return &m->mdp[i];
0291         }
0292     }
0293
0294     return ERR_PTR(-EINVAL);
0295 }
0296
0297 struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
0298         void __iomem *addr,
0299         const struct dpu_mdss_cfg *m)
0300 {
0301     struct dpu_hw_mdp *mdp;
0302     const struct dpu_mdp_cfg *cfg;
0303
0304     if (!addr || !m)
0305         return ERR_PTR(-EINVAL);
0306
0307     mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
0308     if (!mdp)
0309         return ERR_PTR(-ENOMEM);
0310
0311     cfg = _top_offset(idx, m, addr, &mdp->hw);
0312     if (IS_ERR_OR_NULL(cfg)) {
0313         kfree(mdp);
0314         return ERR_PTR(-EINVAL);
0315     }
0316
0317     /*
0318      * Assign ops
0319      */
0320     mdp->idx = idx;
0321     mdp->caps = cfg;
0322     _setup_mdp_ops(&mdp->ops, mdp->caps->features);
0323
0324     return mdp;
0325 }
0326
0327 void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)
0328 {
0329     kfree(mdp);
0330 }
0331