disp/dpu1/dpu_hw_sspp.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0003  */
0004
0005 #ifndef _DPU_HW_SSPP_H
0006 #define _DPU_HW_SSPP_H
0007
0008 #include "dpu_hw_catalog.h"
0009 #include "dpu_hw_mdss.h"
0010 #include "dpu_hw_util.h"
0011 #include "dpu_formats.h"
0012
0013 struct dpu_hw_pipe;
0014
0015 /**
0016  * Flags
0017  */
0018 #define DPU_SSPP_FLIP_LR        BIT(0)
0019 #define DPU_SSPP_FLIP_UD        BIT(1)
0020 #define DPU_SSPP_SOURCE_ROTATED_90  BIT(2)
0021 #define DPU_SSPP_ROT_90         BIT(3)
0022 #define DPU_SSPP_SOLID_FILL     BIT(4)
0023
0024 /**
0025  * Define all scaler feature bits in catalog
0026  */
0027 #define DPU_SSPP_SCALER (BIT(DPU_SSPP_SCALER_RGB) | \
0028              BIT(DPU_SSPP_SCALER_QSEED2) | \
0029              BIT(DPU_SSPP_SCALER_QSEED3) | \
0030              BIT(DPU_SSPP_SCALER_QSEED3LITE) | \
0031              BIT(DPU_SSPP_SCALER_QSEED4))
0032
0033 /*
0034  * Define all CSC feature bits in catalog
0035  */
0036 #define DPU_SSPP_CSC_ANY (BIT(DPU_SSPP_CSC) | \
0037               BIT(DPU_SSPP_CSC_10BIT))
0038
0039 /**
0040  * Component indices
0041  */
0042 enum {
0043     DPU_SSPP_COMP_0,
0044     DPU_SSPP_COMP_1_2,
0045     DPU_SSPP_COMP_2,
0046     DPU_SSPP_COMP_3,
0047
0048     DPU_SSPP_COMP_MAX
0049 };
0050
0051 /**
0052  * DPU_SSPP_RECT_SOLO - multirect disabled
0053  * DPU_SSPP_RECT_0 - rect0 of a multirect pipe
0054  * DPU_SSPP_RECT_1 - rect1 of a multirect pipe
0055  *
0056  * Note: HW supports multirect with either RECT0 or
0057  * RECT1. Considering no benefit of such configs over
0058  * SOLO mode and to keep the plane management simple,
0059  * we dont support single rect multirect configs.
0060  */
0061 enum dpu_sspp_multirect_index {
0062     DPU_SSPP_RECT_SOLO = 0,
0063     DPU_SSPP_RECT_0,
0064     DPU_SSPP_RECT_1,
0065 };
0066
0067 enum dpu_sspp_multirect_mode {
0068     DPU_SSPP_MULTIRECT_NONE = 0,
0069     DPU_SSPP_MULTIRECT_PARALLEL,
0070     DPU_SSPP_MULTIRECT_TIME_MX,
0071 };
0072
0073 enum {
0074     DPU_FRAME_LINEAR,
0075     DPU_FRAME_TILE_A4X,
0076     DPU_FRAME_TILE_A5X,
0077 };
0078
0079 enum dpu_hw_filter {
0080     DPU_SCALE_FILTER_NEAREST = 0,
0081     DPU_SCALE_FILTER_BIL,
0082     DPU_SCALE_FILTER_PCMN,
0083     DPU_SCALE_FILTER_CA,
0084     DPU_SCALE_FILTER_MAX
0085 };
0086
0087 enum dpu_hw_filter_alpa {
0088     DPU_SCALE_ALPHA_PIXEL_REP,
0089     DPU_SCALE_ALPHA_BIL
0090 };
0091
0092 enum dpu_hw_filter_yuv {
0093     DPU_SCALE_2D_4X4,
0094     DPU_SCALE_2D_CIR,
0095     DPU_SCALE_1D_SEP,
0096     DPU_SCALE_BIL
0097 };
0098
0099 struct dpu_hw_sharp_cfg {
0100     u32 strength;
0101     u32 edge_thr;
0102     u32 smooth_thr;
0103     u32 noise_thr;
0104 };
0105
0106 struct dpu_hw_pixel_ext {
0107     /* scaling factors are enabled for this input layer */
0108     uint8_t enable_pxl_ext;
0109
0110     int init_phase_x[DPU_MAX_PLANES];
0111     int phase_step_x[DPU_MAX_PLANES];
0112     int init_phase_y[DPU_MAX_PLANES];
0113     int phase_step_y[DPU_MAX_PLANES];
0114
0115     /*
0116      * Number of pixels extension in left, right, top and bottom direction
0117      * for all color components. This pixel value for each color component
0118      * should be sum of fetch + repeat pixels.
0119      */
0120     int num_ext_pxls_left[DPU_MAX_PLANES];
0121     int num_ext_pxls_right[DPU_MAX_PLANES];
0122     int num_ext_pxls_top[DPU_MAX_PLANES];
0123     int num_ext_pxls_btm[DPU_MAX_PLANES];
0124
0125     /*
0126      * Number of pixels needs to be overfetched in left, right, top and
0127      * bottom directions from source image for scaling.
0128      */
0129     int left_ftch[DPU_MAX_PLANES];
0130     int right_ftch[DPU_MAX_PLANES];
0131     int top_ftch[DPU_MAX_PLANES];
0132     int btm_ftch[DPU_MAX_PLANES];
0133
0134     /*
0135      * Number of pixels needs to be repeated in left, right, top and
0136      * bottom directions for scaling.
0137      */
0138     int left_rpt[DPU_MAX_PLANES];
0139     int right_rpt[DPU_MAX_PLANES];
0140     int top_rpt[DPU_MAX_PLANES];
0141     int btm_rpt[DPU_MAX_PLANES];
0142
0143     uint32_t roi_w[DPU_MAX_PLANES];
0144     uint32_t roi_h[DPU_MAX_PLANES];
0145
0146     /*
0147      * Filter type to be used for scaling in horizontal and vertical
0148      * directions
0149      */
0150     enum dpu_hw_filter horz_filter[DPU_MAX_PLANES];
0151     enum dpu_hw_filter vert_filter[DPU_MAX_PLANES];
0152
0153 };
0154
0155 /**
0156  * struct dpu_hw_pipe_cfg : Pipe description
0157  * @layout:    format layout information for programming buffer to hardware
0158  * @src_rect:  src ROI, caller takes into account the different operations
0159  *             such as decimation, flip etc to program this field
0160  * @dest_rect: destination ROI.
0161  * @index:     index of the rectangle of SSPP
0162  * @mode:      parallel or time multiplex multirect mode
0163  */
0164 struct dpu_hw_pipe_cfg {
0165     struct dpu_hw_fmt_layout layout;
0166     struct drm_rect src_rect;
0167     struct drm_rect dst_rect;
0168     enum dpu_sspp_multirect_index index;
0169     enum dpu_sspp_multirect_mode mode;
0170 };
0171
0172 /**
0173  * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
0174  * @creq_vblank: creq value generated to vbif during vertical blanking
0175  * @danger_vblank: danger value generated during vertical blanking
0176  * @vblank_en: enable creq_vblank and danger_vblank during vblank
0177  * @danger_safe_en: enable danger safe generation
0178  */
0179 struct dpu_hw_pipe_qos_cfg {
0180     u32 creq_vblank;
0181     u32 danger_vblank;
0182     bool vblank_en;
0183     bool danger_safe_en;
0184 };
0185
0186 /**
0187  * enum CDP preload ahead address size
0188  */
0189 enum {
0190     DPU_SSPP_CDP_PRELOAD_AHEAD_32,
0191     DPU_SSPP_CDP_PRELOAD_AHEAD_64
0192 };
0193
0194 /**
0195  * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
0196  * @size: size to prefill in bytes, or zero to disable
0197  * @time: time to prefill in usec, or zero to disable
0198  */
0199 struct dpu_hw_pipe_ts_cfg {
0200     u64 size;
0201     u64 time;
0202 };
0203
0204 /**
0205  * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
0206  * Caller must call the init function to get the pipe context for each pipe
0207  * Assumption is these functions will be called after clocks are enabled
0208  */
0209 struct dpu_hw_sspp_ops {
0210     /**
0211      * setup_format - setup pixel format cropping rectangle, flip
0212      * @ctx: Pointer to pipe context
0213      * @cfg: Pointer to pipe config structure
0214      * @flags: Extra flags for format config
0215      * @index: rectangle index in multirect
0216      */
0217     void (*setup_format)(struct dpu_hw_pipe *ctx,
0218             const struct dpu_format *fmt, u32 flags,
0219             enum dpu_sspp_multirect_index index);
0220
0221     /**
0222      * setup_rects - setup pipe ROI rectangles
0223      * @ctx: Pointer to pipe context
0224      * @cfg: Pointer to pipe config structure
0225      * @index: rectangle index in multirect
0226      */
0227     void (*setup_rects)(struct dpu_hw_pipe *ctx,
0228             struct dpu_hw_pipe_cfg *cfg,
0229             enum dpu_sspp_multirect_index index);
0230
0231     /**
0232      * setup_pe - setup pipe pixel extension
0233      * @ctx: Pointer to pipe context
0234      * @pe_ext: Pointer to pixel ext settings
0235      */
0236     void (*setup_pe)(struct dpu_hw_pipe *ctx,
0237             struct dpu_hw_pixel_ext *pe_ext);
0238
0239     /**
0240      * setup_sourceaddress - setup pipe source addresses
0241      * @ctx: Pointer to pipe context
0242      * @cfg: Pointer to pipe config structure
0243      * @index: rectangle index in multirect
0244      */
0245     void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
0246             struct dpu_hw_pipe_cfg *cfg,
0247             enum dpu_sspp_multirect_index index);
0248
0249     /**
0250      * setup_csc - setup color space coversion
0251      * @ctx: Pointer to pipe context
0252      * @data: Pointer to config structure
0253      */
0254     void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data);
0255
0256     /**
0257      * setup_solidfill - enable/disable colorfill
0258      * @ctx: Pointer to pipe context
0259      * @const_color: Fill color value
0260      * @flags: Pipe flags
0261      * @index: rectangle index in multirect
0262      */
0263     void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
0264             enum dpu_sspp_multirect_index index);
0265
0266     /**
0267      * setup_multirect - setup multirect configuration
0268      * @ctx: Pointer to pipe context
0269      * @index: rectangle index in multirect
0270      * @mode: parallel fetch / time multiplex multirect mode
0271      */
0272
0273     void (*setup_multirect)(struct dpu_hw_pipe *ctx,
0274             enum dpu_sspp_multirect_index index,
0275             enum dpu_sspp_multirect_mode mode);
0276
0277     /**
0278      * setup_sharpening - setup sharpening
0279      * @ctx: Pointer to pipe context
0280      * @cfg: Pointer to config structure
0281      */
0282     void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
0283             struct dpu_hw_sharp_cfg *cfg);
0284
0285     /**
0286      * setup_danger_safe_lut - setup danger safe LUTs
0287      * @ctx: Pointer to pipe context
0288      * @danger_lut: LUT for generate danger level based on fill level
0289      * @safe_lut: LUT for generate safe level based on fill level
0290      *
0291      */
0292     void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
0293             u32 danger_lut,
0294             u32 safe_lut);
0295
0296     /**
0297      * setup_creq_lut - setup CREQ LUT
0298      * @ctx: Pointer to pipe context
0299      * @creq_lut: LUT for generate creq level based on fill level
0300      *
0301      */
0302     void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
0303             u64 creq_lut);
0304
0305     /**
0306      * setup_qos_ctrl - setup QoS control
0307      * @ctx: Pointer to pipe context
0308      * @cfg: Pointer to pipe QoS configuration
0309      *
0310      */
0311     void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
0312             struct dpu_hw_pipe_qos_cfg *cfg);
0313
0314     /**
0315      * setup_histogram - setup histograms
0316      * @ctx: Pointer to pipe context
0317      * @cfg: Pointer to histogram configuration
0318      */
0319     void (*setup_histogram)(struct dpu_hw_pipe *ctx,
0320             void *cfg);
0321
0322     /**
0323      * setup_scaler - setup scaler
0324      * @ctx: Pointer to pipe context
0325      * @pipe_cfg: Pointer to pipe configuration
0326      * @scaler_cfg: Pointer to scaler configuration
0327      */
0328     void (*setup_scaler)(struct dpu_hw_pipe *ctx,
0329         struct dpu_hw_pipe_cfg *pipe_cfg,
0330         void *scaler_cfg);
0331
0332     /**
0333      * get_scaler_ver - get scaler h/w version
0334      * @ctx: Pointer to pipe context
0335      */
0336     u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
0337
0338     /**
0339      * setup_cdp - setup client driven prefetch
0340      * @ctx: Pointer to pipe context
0341      * @cfg: Pointer to cdp configuration
0342      * @index: rectangle index in multirect
0343      */
0344     void (*setup_cdp)(struct dpu_hw_pipe *ctx,
0345             struct dpu_hw_cdp_cfg *cfg,
0346             enum dpu_sspp_multirect_index index);
0347 };
0348
0349 /**
0350  * struct dpu_hw_pipe - pipe description
0351  * @base: hardware block base structure
0352  * @hw: block hardware details
0353  * @catalog: back pointer to catalog
0354  * @mdp: pointer to associated mdp portion of the catalog
0355  * @idx: pipe index
0356  * @cap: pointer to layer_cfg
0357  * @ops: pointer to operations possible for this pipe
0358  */
0359 struct dpu_hw_pipe {
0360     struct dpu_hw_blk base;
0361     struct dpu_hw_blk_reg_map hw;
0362     const struct dpu_mdss_cfg *catalog;
0363     const struct dpu_mdp_cfg *mdp;
0364
0365     /* Pipe */
0366     enum dpu_sspp idx;
0367     const struct dpu_sspp_cfg *cap;
0368
0369     /* Ops */
0370     struct dpu_hw_sspp_ops ops;
0371 };
0372
0373 struct dpu_kms;
0374 /**
0375  * dpu_hw_sspp_init - initializes the sspp hw driver object.
0376  * Should be called once before accessing every pipe.
0377  * @idx:  Pipe index for which driver object is required
0378  * @addr: Mapped register io address of MDP
0379  * @catalog : Pointer to mdss catalog data
0380  * @is_virtual_pipe: is this pipe virtual pipe
0381  */
0382 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
0383         void __iomem *addr, const struct dpu_mdss_cfg *catalog,
0384         bool is_virtual_pipe);
0385
0386 /**
0387  * dpu_hw_sspp_destroy(): Destroys SSPP driver context
0388  * should be called during Hw pipe cleanup.
0389  * @ctx:  Pointer to SSPP driver context returned by dpu_hw_sspp_init
0390  */
0391 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
0392
0393 void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);
0394 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry);
0395
0396 #endif /*_DPU_HW_SSPP_H */
0397