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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0003  */
0004 
0005 #include "dpu_hwio.h"
0006 #include "dpu_hw_catalog.h"
0007 #include "dpu_hw_lm.h"
0008 #include "dpu_hw_sspp.h"
0009 #include "dpu_kms.h"
0010 
0011 #include <drm/drm_file.h>
0012 
0013 #define DPU_FETCH_CONFIG_RESET_VALUE   0x00000087
0014 
0015 /* DPU_SSPP_SRC */
0016 #define SSPP_SRC_SIZE                      0x00
0017 #define SSPP_SRC_XY                        0x08
0018 #define SSPP_OUT_SIZE                      0x0c
0019 #define SSPP_OUT_XY                        0x10
0020 #define SSPP_SRC0_ADDR                     0x14
0021 #define SSPP_SRC1_ADDR                     0x18
0022 #define SSPP_SRC2_ADDR                     0x1C
0023 #define SSPP_SRC3_ADDR                     0x20
0024 #define SSPP_SRC_YSTRIDE0                  0x24
0025 #define SSPP_SRC_YSTRIDE1                  0x28
0026 #define SSPP_SRC_FORMAT                    0x30
0027 #define SSPP_SRC_UNPACK_PATTERN            0x34
0028 #define SSPP_SRC_OP_MODE                   0x38
0029 
0030 /* SSPP_MULTIRECT*/
0031 #define SSPP_SRC_SIZE_REC1                 0x16C
0032 #define SSPP_SRC_XY_REC1                   0x168
0033 #define SSPP_OUT_SIZE_REC1                 0x160
0034 #define SSPP_OUT_XY_REC1                   0x164
0035 #define SSPP_SRC_FORMAT_REC1               0x174
0036 #define SSPP_SRC_UNPACK_PATTERN_REC1       0x178
0037 #define SSPP_SRC_OP_MODE_REC1              0x17C
0038 #define SSPP_MULTIRECT_OPMODE              0x170
0039 #define SSPP_SRC_CONSTANT_COLOR_REC1       0x180
0040 #define SSPP_EXCL_REC_SIZE_REC1            0x184
0041 #define SSPP_EXCL_REC_XY_REC1              0x188
0042 
0043 #define MDSS_MDP_OP_DEINTERLACE            BIT(22)
0044 #define MDSS_MDP_OP_DEINTERLACE_ODD        BIT(23)
0045 #define MDSS_MDP_OP_IGC_ROM_1              BIT(18)
0046 #define MDSS_MDP_OP_IGC_ROM_0              BIT(17)
0047 #define MDSS_MDP_OP_IGC_EN                 BIT(16)
0048 #define MDSS_MDP_OP_FLIP_UD                BIT(14)
0049 #define MDSS_MDP_OP_FLIP_LR                BIT(13)
0050 #define MDSS_MDP_OP_BWC_EN                 BIT(0)
0051 #define MDSS_MDP_OP_PE_OVERRIDE            BIT(31)
0052 #define MDSS_MDP_OP_BWC_LOSSLESS           (0 << 1)
0053 #define MDSS_MDP_OP_BWC_Q_HIGH             (1 << 1)
0054 #define MDSS_MDP_OP_BWC_Q_MED              (2 << 1)
0055 
0056 #define SSPP_SRC_CONSTANT_COLOR            0x3c
0057 #define SSPP_EXCL_REC_CTL                  0x40
0058 #define SSPP_UBWC_STATIC_CTRL              0x44
0059 #define SSPP_FETCH_CONFIG                  0x048
0060 #define SSPP_DANGER_LUT                    0x60
0061 #define SSPP_SAFE_LUT                      0x64
0062 #define SSPP_CREQ_LUT                      0x68
0063 #define SSPP_QOS_CTRL                      0x6C
0064 #define SSPP_DECIMATION_CONFIG             0xB4
0065 #define SSPP_SRC_ADDR_SW_STATUS            0x70
0066 #define SSPP_CREQ_LUT_0                    0x74
0067 #define SSPP_CREQ_LUT_1                    0x78
0068 #define SSPP_SW_PIX_EXT_C0_LR              0x100
0069 #define SSPP_SW_PIX_EXT_C0_TB              0x104
0070 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS      0x108
0071 #define SSPP_SW_PIX_EXT_C1C2_LR            0x110
0072 #define SSPP_SW_PIX_EXT_C1C2_TB            0x114
0073 #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS    0x118
0074 #define SSPP_SW_PIX_EXT_C3_LR              0x120
0075 #define SSPP_SW_PIX_EXT_C3_TB              0x124
0076 #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS      0x128
0077 #define SSPP_TRAFFIC_SHAPER                0x130
0078 #define SSPP_CDP_CNTL                      0x134
0079 #define SSPP_UBWC_ERROR_STATUS             0x138
0080 #define SSPP_CDP_CNTL_REC1                 0x13c
0081 #define SSPP_TRAFFIC_SHAPER_PREFILL        0x150
0082 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL   0x154
0083 #define SSPP_TRAFFIC_SHAPER_REC1           0x158
0084 #define SSPP_EXCL_REC_SIZE                 0x1B4
0085 #define SSPP_EXCL_REC_XY                   0x1B8
0086 #define SSPP_VIG_OP_MODE                   0x0
0087 #define SSPP_VIG_CSC_10_OP_MODE            0x0
0088 #define SSPP_TRAFFIC_SHAPER_BPC_MAX        0xFF
0089 
0090 /* SSPP_QOS_CTRL */
0091 #define SSPP_QOS_CTRL_VBLANK_EN            BIT(16)
0092 #define SSPP_QOS_CTRL_DANGER_SAFE_EN       BIT(0)
0093 #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK   0x3
0094 #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF    4
0095 #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK     0x3
0096 #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF      20
0097 
0098 /* DPU_SSPP_SCALER_QSEED2 */
0099 #define SCALE_CONFIG                       0x04
0100 #define COMP0_3_PHASE_STEP_X               0x10
0101 #define COMP0_3_PHASE_STEP_Y               0x14
0102 #define COMP1_2_PHASE_STEP_X               0x18
0103 #define COMP1_2_PHASE_STEP_Y               0x1c
0104 #define COMP0_3_INIT_PHASE_X               0x20
0105 #define COMP0_3_INIT_PHASE_Y               0x24
0106 #define COMP1_2_INIT_PHASE_X               0x28
0107 #define COMP1_2_INIT_PHASE_Y               0x2C
0108 #define VIG_0_QSEED2_SHARP                 0x30
0109 
0110 /*
0111  * Definitions for ViG op modes
0112  */
0113 #define VIG_OP_CSC_DST_DATAFMT BIT(19)
0114 #define VIG_OP_CSC_SRC_DATAFMT BIT(18)
0115 #define VIG_OP_CSC_EN          BIT(17)
0116 #define VIG_OP_MEM_PROT_CONT   BIT(15)
0117 #define VIG_OP_MEM_PROT_VAL    BIT(14)
0118 #define VIG_OP_MEM_PROT_SAT    BIT(13)
0119 #define VIG_OP_MEM_PROT_HUE    BIT(12)
0120 #define VIG_OP_HIST            BIT(8)
0121 #define VIG_OP_SKY_COL         BIT(7)
0122 #define VIG_OP_FOIL            BIT(6)
0123 #define VIG_OP_SKIN_COL        BIT(5)
0124 #define VIG_OP_PA_EN           BIT(4)
0125 #define VIG_OP_PA_SAT_ZERO_EXP BIT(2)
0126 #define VIG_OP_MEM_PROT_BLEND  BIT(1)
0127 
0128 /*
0129  * Definitions for CSC 10 op modes
0130  */
0131 #define VIG_CSC_10_SRC_DATAFMT BIT(1)
0132 #define VIG_CSC_10_EN          BIT(0)
0133 #define CSC_10BIT_OFFSET       4
0134 
0135 /* traffic shaper clock in Hz */
0136 #define TS_CLK          19200000
0137 
0138 
0139 static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
0140         int s_id,
0141         u32 *idx)
0142 {
0143     int rc = 0;
0144     const struct dpu_sspp_sub_blks *sblk;
0145 
0146     if (!ctx || !ctx->cap || !ctx->cap->sblk)
0147         return -EINVAL;
0148 
0149     sblk = ctx->cap->sblk;
0150 
0151     switch (s_id) {
0152     case DPU_SSPP_SRC:
0153         *idx = sblk->src_blk.base;
0154         break;
0155     case DPU_SSPP_SCALER_QSEED2:
0156     case DPU_SSPP_SCALER_QSEED3:
0157     case DPU_SSPP_SCALER_RGB:
0158         *idx = sblk->scaler_blk.base;
0159         break;
0160     case DPU_SSPP_CSC:
0161     case DPU_SSPP_CSC_10BIT:
0162         *idx = sblk->csc_blk.base;
0163         break;
0164     default:
0165         rc = -EINVAL;
0166     }
0167 
0168     return rc;
0169 }
0170 
0171 static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx,
0172         enum dpu_sspp_multirect_index index,
0173         enum dpu_sspp_multirect_mode mode)
0174 {
0175     u32 mode_mask;
0176     u32 idx;
0177 
0178     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
0179         return;
0180 
0181     if (index == DPU_SSPP_RECT_SOLO) {
0182         /**
0183          * if rect index is RECT_SOLO, we cannot expect a
0184          * virtual plane sharing the same SSPP id. So we go
0185          * and disable multirect
0186          */
0187         mode_mask = 0;
0188     } else {
0189         mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx);
0190         mode_mask |= index;
0191         if (mode == DPU_SSPP_MULTIRECT_TIME_MX)
0192             mode_mask |= BIT(2);
0193         else
0194             mode_mask &= ~BIT(2);
0195     }
0196 
0197     DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask);
0198 }
0199 
0200 static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx,
0201         u32 mask, u8 en)
0202 {
0203     u32 idx;
0204     u32 opmode;
0205 
0206     if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) ||
0207         _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) ||
0208         !test_bit(DPU_SSPP_CSC, &ctx->cap->features))
0209         return;
0210 
0211     opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx);
0212 
0213     if (en)
0214         opmode |= mask;
0215     else
0216         opmode &= ~mask;
0217 
0218     DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
0219 }
0220 
0221 static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx,
0222         u32 mask, u8 en)
0223 {
0224     u32 idx;
0225     u32 opmode;
0226 
0227     if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC_10BIT, &idx))
0228         return;
0229 
0230     opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx);
0231     if (en)
0232         opmode |= mask;
0233     else
0234         opmode &= ~mask;
0235 
0236     DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode);
0237 }
0238 
0239 /*
0240  * Setup source pixel format, flip,
0241  */
0242 static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
0243         const struct dpu_format *fmt, u32 flags,
0244         enum dpu_sspp_multirect_index rect_mode)
0245 {
0246     struct dpu_hw_blk_reg_map *c;
0247     u32 chroma_samp, unpack, src_format;
0248     u32 opmode = 0;
0249     u32 fast_clear = 0;
0250     u32 op_mode_off, unpack_pat_off, format_off;
0251     u32 idx;
0252 
0253     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt)
0254         return;
0255 
0256     if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) {
0257         op_mode_off = SSPP_SRC_OP_MODE;
0258         unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
0259         format_off = SSPP_SRC_FORMAT;
0260     } else {
0261         op_mode_off = SSPP_SRC_OP_MODE_REC1;
0262         unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
0263         format_off = SSPP_SRC_FORMAT_REC1;
0264     }
0265 
0266     c = &ctx->hw;
0267     opmode = DPU_REG_READ(c, op_mode_off + idx);
0268     opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
0269             MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
0270 
0271     if (flags & DPU_SSPP_FLIP_LR)
0272         opmode |= MDSS_MDP_OP_FLIP_LR;
0273     if (flags & DPU_SSPP_FLIP_UD)
0274         opmode |= MDSS_MDP_OP_FLIP_UD;
0275 
0276     chroma_samp = fmt->chroma_sample;
0277     if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
0278         if (chroma_samp == DPU_CHROMA_H2V1)
0279             chroma_samp = DPU_CHROMA_H1V2;
0280         else if (chroma_samp == DPU_CHROMA_H1V2)
0281             chroma_samp = DPU_CHROMA_H2V1;
0282     }
0283 
0284     src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
0285         (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
0286         (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
0287 
0288     if (flags & DPU_SSPP_ROT_90)
0289         src_format |= BIT(11); /* ROT90 */
0290 
0291     if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
0292         src_format |= BIT(8); /* SRCC3_EN */
0293 
0294     if (flags & DPU_SSPP_SOLID_FILL)
0295         src_format |= BIT(22);
0296 
0297     unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
0298         (fmt->element[1] << 8) | (fmt->element[0] << 0);
0299     src_format |= ((fmt->unpack_count - 1) << 12) |
0300         (fmt->unpack_tight << 17) |
0301         (fmt->unpack_align_msb << 18) |
0302         ((fmt->bpp - 1) << 9);
0303 
0304     if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
0305         if (DPU_FORMAT_IS_UBWC(fmt))
0306             opmode |= MDSS_MDP_OP_BWC_EN;
0307         src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
0308         DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
0309             DPU_FETCH_CONFIG_RESET_VALUE |
0310             ctx->mdp->highest_bank_bit << 18);
0311         switch (ctx->catalog->caps->ubwc_version) {
0312         case DPU_HW_UBWC_VER_10:
0313             /* TODO: UBWC v1 case */
0314             break;
0315         case DPU_HW_UBWC_VER_20:
0316             fast_clear = fmt->alpha_enable ? BIT(31) : 0;
0317             DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
0318                     fast_clear | (ctx->mdp->ubwc_swizzle) |
0319                     (ctx->mdp->highest_bank_bit << 4));
0320             break;
0321         case DPU_HW_UBWC_VER_30:
0322             DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
0323                     BIT(30) | (ctx->mdp->ubwc_swizzle) |
0324                     (ctx->mdp->highest_bank_bit << 4));
0325             break;
0326         case DPU_HW_UBWC_VER_40:
0327             DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
0328                     DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
0329             break;
0330         }
0331     }
0332 
0333     opmode |= MDSS_MDP_OP_PE_OVERRIDE;
0334 
0335     /* if this is YUV pixel format, enable CSC */
0336     if (DPU_FORMAT_IS_YUV(fmt))
0337         src_format |= BIT(15);
0338 
0339     if (DPU_FORMAT_IS_DX(fmt))
0340         src_format |= BIT(14);
0341 
0342     /* update scaler opmode, if appropriate */
0343     if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
0344         _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
0345             DPU_FORMAT_IS_YUV(fmt));
0346     else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
0347         _sspp_setup_csc10_opmode(ctx,
0348             VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
0349             DPU_FORMAT_IS_YUV(fmt));
0350 
0351     DPU_REG_WRITE(c, format_off + idx, src_format);
0352     DPU_REG_WRITE(c, unpack_pat_off + idx, unpack);
0353     DPU_REG_WRITE(c, op_mode_off + idx, opmode);
0354 
0355     /* clear previous UBWC error */
0356     DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
0357 }
0358 
0359 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
0360         struct dpu_hw_pixel_ext *pe_ext)
0361 {
0362     struct dpu_hw_blk_reg_map *c;
0363     u8 color;
0364     u32 lr_pe[4], tb_pe[4], tot_req_pixels[4];
0365     const u32 bytemask = 0xff;
0366     const u32 shortmask = 0xffff;
0367     u32 idx;
0368 
0369     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !pe_ext)
0370         return;
0371 
0372     c = &ctx->hw;
0373 
0374     /* program SW pixel extension override for all pipes*/
0375     for (color = 0; color < DPU_MAX_PLANES; color++) {
0376         /* color 2 has the same set of registers as color 1 */
0377         if (color == 2)
0378             continue;
0379 
0380         lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)|
0381             ((pe_ext->right_rpt[color] & bytemask) << 16)|
0382             ((pe_ext->left_ftch[color] & bytemask) << 8)|
0383             (pe_ext->left_rpt[color] & bytemask);
0384 
0385         tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)|
0386             ((pe_ext->btm_rpt[color] & bytemask) << 16)|
0387             ((pe_ext->top_ftch[color] & bytemask) << 8)|
0388             (pe_ext->top_rpt[color] & bytemask);
0389 
0390         tot_req_pixels[color] = (((pe_ext->roi_h[color] +
0391             pe_ext->num_ext_pxls_top[color] +
0392             pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) |
0393             ((pe_ext->roi_w[color] +
0394             pe_ext->num_ext_pxls_left[color] +
0395             pe_ext->num_ext_pxls_right[color]) & shortmask);
0396     }
0397 
0398     /* color 0 */
0399     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]);
0400     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]);
0401     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx,
0402             tot_req_pixels[0]);
0403 
0404     /* color 1 and color 2 */
0405     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]);
0406     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]);
0407     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx,
0408             tot_req_pixels[1]);
0409 
0410     /* color 3 */
0411     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]);
0412     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]);
0413     DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx,
0414             tot_req_pixels[3]);
0415 }
0416 
0417 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
0418         struct dpu_hw_pipe_cfg *sspp,
0419         void *scaler_cfg)
0420 {
0421     u32 idx;
0422     struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
0423 
0424     if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
0425         || !scaler3_cfg)
0426         return;
0427 
0428     dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
0429             ctx->cap->sblk->scaler_blk.version,
0430             sspp->layout.format);
0431 }
0432 
0433 static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx)
0434 {
0435     u32 idx;
0436 
0437     if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx))
0438         return 0;
0439 
0440     return dpu_hw_get_scaler3_ver(&ctx->hw, idx);
0441 }
0442 
0443 /*
0444  * dpu_hw_sspp_setup_rects()
0445  */
0446 static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
0447         struct dpu_hw_pipe_cfg *cfg,
0448         enum dpu_sspp_multirect_index rect_index)
0449 {
0450     struct dpu_hw_blk_reg_map *c;
0451     u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
0452     u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
0453     u32 idx;
0454 
0455     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg)
0456         return;
0457 
0458     c = &ctx->hw;
0459 
0460     if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) {
0461         src_size_off = SSPP_SRC_SIZE;
0462         src_xy_off = SSPP_SRC_XY;
0463         out_size_off = SSPP_OUT_SIZE;
0464         out_xy_off = SSPP_OUT_XY;
0465     } else {
0466         src_size_off = SSPP_SRC_SIZE_REC1;
0467         src_xy_off = SSPP_SRC_XY_REC1;
0468         out_size_off = SSPP_OUT_SIZE_REC1;
0469         out_xy_off = SSPP_OUT_XY_REC1;
0470     }
0471 
0472 
0473     /* src and dest rect programming */
0474     src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
0475     src_size = (drm_rect_height(&cfg->src_rect) << 16) |
0476            drm_rect_width(&cfg->src_rect);
0477     dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
0478     dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
0479         drm_rect_width(&cfg->dst_rect);
0480 
0481     if (rect_index == DPU_SSPP_RECT_SOLO) {
0482         ystride0 = (cfg->layout.plane_pitch[0]) |
0483             (cfg->layout.plane_pitch[1] << 16);
0484         ystride1 = (cfg->layout.plane_pitch[2]) |
0485             (cfg->layout.plane_pitch[3] << 16);
0486     } else {
0487         ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
0488         ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
0489 
0490         if (rect_index == DPU_SSPP_RECT_0) {
0491             ystride0 = (ystride0 & 0xFFFF0000) |
0492                 (cfg->layout.plane_pitch[0] & 0x0000FFFF);
0493             ystride1 = (ystride1 & 0xFFFF0000)|
0494                 (cfg->layout.plane_pitch[2] & 0x0000FFFF);
0495         } else {
0496             ystride0 = (ystride0 & 0x0000FFFF) |
0497                 ((cfg->layout.plane_pitch[0] << 16) &
0498                  0xFFFF0000);
0499             ystride1 = (ystride1 & 0x0000FFFF) |
0500                 ((cfg->layout.plane_pitch[2] << 16) &
0501                  0xFFFF0000);
0502         }
0503     }
0504 
0505     /* rectangle register programming */
0506     DPU_REG_WRITE(c, src_size_off + idx, src_size);
0507     DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
0508     DPU_REG_WRITE(c, out_size_off + idx, dst_size);
0509     DPU_REG_WRITE(c, out_xy_off + idx, dst_xy);
0510 
0511     DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
0512     DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
0513 }
0514 
0515 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
0516         struct dpu_hw_pipe_cfg *cfg,
0517         enum dpu_sspp_multirect_index rect_mode)
0518 {
0519     int i;
0520     u32 idx;
0521 
0522     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
0523         return;
0524 
0525     if (rect_mode == DPU_SSPP_RECT_SOLO) {
0526         for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
0527             DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
0528                     cfg->layout.plane_addr[i]);
0529     } else if (rect_mode == DPU_SSPP_RECT_0) {
0530         DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
0531                 cfg->layout.plane_addr[0]);
0532         DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
0533                 cfg->layout.plane_addr[2]);
0534     } else {
0535         DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
0536                 cfg->layout.plane_addr[0]);
0537         DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
0538                 cfg->layout.plane_addr[2]);
0539     }
0540 }
0541 
0542 static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
0543         const struct dpu_csc_cfg *data)
0544 {
0545     u32 idx;
0546     bool csc10 = false;
0547 
0548     if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC, &idx) || !data)
0549         return;
0550 
0551     if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) {
0552         idx += CSC_10BIT_OFFSET;
0553         csc10 = true;
0554     }
0555 
0556     dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
0557 }
0558 
0559 static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
0560         dpu_sspp_multirect_index rect_index)
0561 {
0562     u32 idx;
0563 
0564     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
0565         return;
0566 
0567     if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0)
0568         DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);
0569     else
0570         DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx,
0571                 color);
0572 }
0573 
0574 static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
0575             u32 danger_lut,
0576             u32 safe_lut)
0577 {
0578     u32 idx;
0579 
0580     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
0581         return;
0582 
0583     DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut);
0584     DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
0585 }
0586 
0587 static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
0588             u64 creq_lut)
0589 {
0590     u32 idx;
0591 
0592     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
0593         return;
0594 
0595     if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) {
0596         DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut);
0597         DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx,
0598                 creq_lut >> 32);
0599     } else {
0600         DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut);
0601     }
0602 }
0603 
0604 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
0605         struct dpu_hw_pipe_qos_cfg *cfg)
0606 {
0607     u32 idx;
0608     u32 qos_ctrl = 0;
0609 
0610     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
0611         return;
0612 
0613     if (cfg->vblank_en) {
0614         qos_ctrl |= ((cfg->creq_vblank &
0615                 SSPP_QOS_CTRL_CREQ_VBLANK_MASK) <<
0616                 SSPP_QOS_CTRL_CREQ_VBLANK_OFF);
0617         qos_ctrl |= ((cfg->danger_vblank &
0618                 SSPP_QOS_CTRL_DANGER_VBLANK_MASK) <<
0619                 SSPP_QOS_CTRL_DANGER_VBLANK_OFF);
0620         qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN;
0621     }
0622 
0623     if (cfg->danger_safe_en)
0624         qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN;
0625 
0626     DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
0627 }
0628 
0629 static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
0630         struct dpu_hw_cdp_cfg *cfg,
0631         enum dpu_sspp_multirect_index index)
0632 {
0633     u32 idx;
0634     u32 cdp_cntl = 0;
0635     u32 cdp_cntl_offset = 0;
0636 
0637     if (!ctx || !cfg)
0638         return;
0639 
0640     if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
0641         return;
0642 
0643     if (index == DPU_SSPP_RECT_SOLO || index == DPU_SSPP_RECT_0)
0644         cdp_cntl_offset = SSPP_CDP_CNTL;
0645     else
0646         cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
0647 
0648     if (cfg->enable)
0649         cdp_cntl |= BIT(0);
0650     if (cfg->ubwc_meta_enable)
0651         cdp_cntl |= BIT(1);
0652     if (cfg->tile_amortize_enable)
0653         cdp_cntl |= BIT(2);
0654     if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64)
0655         cdp_cntl |= BIT(3);
0656 
0657     DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl);
0658 }
0659 
0660 static void _setup_layer_ops(struct dpu_hw_pipe *c,
0661         unsigned long features)
0662 {
0663     if (test_bit(DPU_SSPP_SRC, &features)) {
0664         c->ops.setup_format = dpu_hw_sspp_setup_format;
0665         c->ops.setup_rects = dpu_hw_sspp_setup_rects;
0666         c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress;
0667         c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill;
0668         c->ops.setup_pe = dpu_hw_sspp_setup_pe_config;
0669     }
0670 
0671     if (test_bit(DPU_SSPP_QOS, &features)) {
0672         c->ops.setup_danger_safe_lut =
0673             dpu_hw_sspp_setup_danger_safe_lut;
0674         c->ops.setup_creq_lut = dpu_hw_sspp_setup_creq_lut;
0675         c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl;
0676     }
0677 
0678     if (test_bit(DPU_SSPP_CSC, &features) ||
0679         test_bit(DPU_SSPP_CSC_10BIT, &features))
0680         c->ops.setup_csc = dpu_hw_sspp_setup_csc;
0681 
0682     if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
0683         test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
0684         c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
0685 
0686     if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) ||
0687             test_bit(DPU_SSPP_SCALER_QSEED3LITE, &features) ||
0688             test_bit(DPU_SSPP_SCALER_QSEED4, &features)) {
0689         c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
0690         c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver;
0691     }
0692 
0693     if (test_bit(DPU_SSPP_CDP, &features))
0694         c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
0695 }
0696 
0697 #ifdef CONFIG_DEBUG_FS
0698 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry)
0699 {
0700     const struct dpu_sspp_cfg *cfg = hw_pipe->cap;
0701     const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
0702     struct dentry *debugfs_root;
0703     char sspp_name[32];
0704 
0705     snprintf(sspp_name, sizeof(sspp_name), "%d", hw_pipe->idx);
0706 
0707     /* create overall sub-directory for the pipe */
0708     debugfs_root =
0709         debugfs_create_dir(sspp_name, entry);
0710 
0711     /* don't error check these */
0712     debugfs_create_xul("features", 0600,
0713             debugfs_root, (unsigned long *)&hw_pipe->cap->features);
0714 
0715     /* add register dump support */
0716     dpu_debugfs_create_regset32("src_blk", 0400,
0717             debugfs_root,
0718             sblk->src_blk.base + cfg->base,
0719             sblk->src_blk.len,
0720             kms);
0721 
0722     if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
0723             cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) ||
0724             cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
0725             cfg->features & BIT(DPU_SSPP_SCALER_QSEED4))
0726         dpu_debugfs_create_regset32("scaler_blk", 0400,
0727                 debugfs_root,
0728                 sblk->scaler_blk.base + cfg->base,
0729                 sblk->scaler_blk.len,
0730                 kms);
0731 
0732     if (cfg->features & BIT(DPU_SSPP_CSC) ||
0733             cfg->features & BIT(DPU_SSPP_CSC_10BIT))
0734         dpu_debugfs_create_regset32("csc_blk", 0400,
0735                 debugfs_root,
0736                 sblk->csc_blk.base + cfg->base,
0737                 sblk->csc_blk.len,
0738                 kms);
0739 
0740     debugfs_create_u32("xin_id",
0741             0400,
0742             debugfs_root,
0743             (u32 *) &cfg->xin_id);
0744     debugfs_create_u32("clk_ctrl",
0745             0400,
0746             debugfs_root,
0747             (u32 *) &cfg->clk_ctrl);
0748     debugfs_create_x32("creq_vblank",
0749             0600,
0750             debugfs_root,
0751             (u32 *) &sblk->creq_vblank);
0752     debugfs_create_x32("danger_vblank",
0753             0600,
0754             debugfs_root,
0755             (u32 *) &sblk->danger_vblank);
0756 
0757     return 0;
0758 }
0759 #endif
0760 
0761 
0762 static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp,
0763         void __iomem *addr,
0764         const struct dpu_mdss_cfg *catalog,
0765         struct dpu_hw_blk_reg_map *b)
0766 {
0767     int i;
0768 
0769     if ((sspp < SSPP_MAX) && catalog && addr && b) {
0770         for (i = 0; i < catalog->sspp_count; i++) {
0771             if (sspp == catalog->sspp[i].id) {
0772                 b->blk_addr = addr + catalog->sspp[i].base;
0773                 b->log_mask = DPU_DBG_MASK_SSPP;
0774                 return &catalog->sspp[i];
0775             }
0776         }
0777     }
0778 
0779     return ERR_PTR(-ENOMEM);
0780 }
0781 
0782 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
0783         void __iomem *addr, const struct dpu_mdss_cfg *catalog,
0784         bool is_virtual_pipe)
0785 {
0786     struct dpu_hw_pipe *hw_pipe;
0787     const struct dpu_sspp_cfg *cfg;
0788 
0789     if (!addr || !catalog)
0790         return ERR_PTR(-EINVAL);
0791 
0792     hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);
0793     if (!hw_pipe)
0794         return ERR_PTR(-ENOMEM);
0795 
0796     cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw);
0797     if (IS_ERR_OR_NULL(cfg)) {
0798         kfree(hw_pipe);
0799         return ERR_PTR(-EINVAL);
0800     }
0801 
0802     /* Assign ops */
0803     hw_pipe->catalog = catalog;
0804     hw_pipe->mdp = &catalog->mdp[0];
0805     hw_pipe->idx = idx;
0806     hw_pipe->cap = cfg;
0807     _setup_layer_ops(hw_pipe, hw_pipe->cap->features);
0808 
0809     return hw_pipe;
0810 }
0811 
0812 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
0813 {
0814     kfree(ctx);
0815 }
0816
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