disp/dpu1/dpu_hw_pingpong.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0003  */
0004
0005 #ifndef _DPU_HW_PINGPONG_H
0006 #define _DPU_HW_PINGPONG_H
0007
0008 #include "dpu_hw_catalog.h"
0009 #include "dpu_hw_mdss.h"
0010 #include "dpu_hw_util.h"
0011
0012 #define DITHER_MATRIX_SZ 16
0013
0014 struct dpu_hw_pingpong;
0015
0016 struct dpu_hw_tear_check {
0017     /*
0018      * This is ratio of MDP VSYNC clk freq(Hz) to
0019      * refresh rate divided by no of lines
0020      */
0021     u32 vsync_count;
0022     u32 sync_cfg_height;
0023     u32 vsync_init_val;
0024     u32 sync_threshold_start;
0025     u32 sync_threshold_continue;
0026     u32 start_pos;
0027     u32 rd_ptr_irq;
0028     u8 hw_vsync_mode;
0029 };
0030
0031 struct dpu_hw_pp_vsync_info {
0032     u32 rd_ptr_init_val;    /* value of rd pointer at vsync edge */
0033     u32 rd_ptr_frame_count; /* num frames sent since enabling interface */
0034     u32 rd_ptr_line_count;  /* current line on panel (rd ptr) */
0035     u32 wr_ptr_line_count;  /* current line within pp fifo (wr ptr) */
0036 };
0037
0038 /**
0039  * struct dpu_hw_dither_cfg - dither feature structure
0040  * @flags: for customizing operations
0041  * @temporal_en: temperal dither enable
0042  * @c0_bitdepth: c0 component bit depth
0043  * @c1_bitdepth: c1 component bit depth
0044  * @c2_bitdepth: c2 component bit depth
0045  * @c3_bitdepth: c2 component bit depth
0046  * @matrix: dither strength matrix
0047  */
0048 struct dpu_hw_dither_cfg {
0049     u64 flags;
0050     u32 temporal_en;
0051     u32 c0_bitdepth;
0052     u32 c1_bitdepth;
0053     u32 c2_bitdepth;
0054     u32 c3_bitdepth;
0055     u32 matrix[DITHER_MATRIX_SZ];
0056 };
0057
0058 /**
0059  *
0060  * struct dpu_hw_pingpong_ops : Interface to the pingpong Hw driver functions
0061  *  Assumption is these functions will be called after clocks are enabled
0062  *  @setup_tearcheck : program tear check values
0063  *  @enable_tearcheck : enables tear check
0064  *  @get_vsync_info : retries timing info of the panel
0065  *  @setup_autorefresh : configure and enable the autorefresh config
0066  *  @get_autorefresh : retrieve autorefresh config from hardware
0067  *  @setup_dither : function to program the dither hw block
0068  *  @get_line_count: obtain current vertical line counter
0069  */
0070 struct dpu_hw_pingpong_ops {
0071     /**
0072      * enables vysnc generation and sets up init value of
0073      * read pointer and programs the tear check cofiguration
0074      */
0075     int (*setup_tearcheck)(struct dpu_hw_pingpong *pp,
0076             struct dpu_hw_tear_check *cfg);
0077
0078     /**
0079      * enables tear check block
0080      */
0081     int (*enable_tearcheck)(struct dpu_hw_pingpong *pp,
0082             bool enable);
0083
0084     /**
0085      * read, modify, write to either set or clear listening to external TE
0086      * @Return: 1 if TE was originally connected, 0 if not, or -ERROR
0087      */
0088     int (*connect_external_te)(struct dpu_hw_pingpong *pp,
0089             bool enable_external_te);
0090
0091     /**
0092      * provides the programmed and current
0093      * line_count
0094      */
0095     int (*get_vsync_info)(struct dpu_hw_pingpong *pp,
0096             struct dpu_hw_pp_vsync_info  *info);
0097
0098     /**
0099      * configure and enable the autorefresh config
0100      */
0101     void (*setup_autorefresh)(struct dpu_hw_pingpong *pp,
0102                   u32 frame_count, bool enable);
0103
0104     /**
0105      * retrieve autorefresh config from hardware
0106      */
0107     bool (*get_autorefresh)(struct dpu_hw_pingpong *pp,
0108                 u32 *frame_count);
0109
0110     /**
0111      * poll until write pointer transmission starts
0112      * @Return: 0 on success, -ETIMEDOUT on timeout
0113      */
0114     int (*poll_timeout_wr_ptr)(struct dpu_hw_pingpong *pp, u32 timeout_us);
0115
0116     /**
0117      * Obtain current vertical line counter
0118      */
0119     u32 (*get_line_count)(struct dpu_hw_pingpong *pp);
0120
0121     /**
0122      * Setup dither matix for pingpong block
0123      */
0124     void (*setup_dither)(struct dpu_hw_pingpong *pp,
0125             struct dpu_hw_dither_cfg *cfg);
0126     /**
0127      * Enable DSC
0128      */
0129     int (*enable_dsc)(struct dpu_hw_pingpong *pp);
0130
0131     /**
0132      * Disable DSC
0133      */
0134     void (*disable_dsc)(struct dpu_hw_pingpong *pp);
0135
0136     /**
0137      * Setup DSC
0138      */
0139     int (*setup_dsc)(struct dpu_hw_pingpong *pp);
0140 };
0141
0142 struct dpu_hw_merge_3d;
0143
0144 struct dpu_hw_pingpong {
0145     struct dpu_hw_blk base;
0146     struct dpu_hw_blk_reg_map hw;
0147
0148     /* pingpong */
0149     enum dpu_pingpong idx;
0150     const struct dpu_pingpong_cfg *caps;
0151     struct dpu_hw_merge_3d *merge_3d;
0152
0153     /* ops */
0154     struct dpu_hw_pingpong_ops ops;
0155 };
0156
0157 /**
0158  * to_dpu_hw_pingpong - convert base object dpu_hw_base to container
0159  * @hw: Pointer to base hardware block
0160  * return: Pointer to hardware block container
0161  */
0162 static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw)
0163 {
0164     return container_of(hw, struct dpu_hw_pingpong, base);
0165 }
0166
0167 /**
0168  * dpu_hw_pingpong_init - initializes the pingpong driver for the passed
0169  *  pingpong idx.
0170  * @idx:  Pingpong index for which driver object is required
0171  * @addr: Mapped register io address of MDP
0172  * @m:    Pointer to mdss catalog data
0173  * Returns: Error code or allocated dpu_hw_pingpong context
0174  */
0175 struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
0176         void __iomem *addr,
0177         const struct dpu_mdss_cfg *m);
0178
0179 /**
0180  * dpu_hw_pingpong_destroy - destroys pingpong driver context
0181  *  should be called to free the context
0182  * @pp:   Pointer to PP driver context returned by dpu_hw_pingpong_init
0183  */
0184 void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp);
0185
0186 #endif /*_DPU_HW_PINGPONG_H */