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0005 #include <linux/iopoll.h>
0006
0007 #include "dpu_hw_mdss.h"
0008 #include "dpu_hwio.h"
0009 #include "dpu_hw_catalog.h"
0010 #include "dpu_hw_merge3d.h"
0011 #include "dpu_kms.h"
0012 #include "dpu_trace.h"
0013
0014 #define MERGE_3D_MUX 0x000
0015 #define MERGE_3D_MODE 0x004
0016
0017 static const struct dpu_merge_3d_cfg *_merge_3d_offset(enum dpu_merge_3d idx,
0018 const struct dpu_mdss_cfg *m,
0019 void __iomem *addr,
0020 struct dpu_hw_blk_reg_map *b)
0021 {
0022 int i;
0023
0024 for (i = 0; i < m->merge_3d_count; i++) {
0025 if (idx == m->merge_3d[i].id) {
0026 b->blk_addr = addr + m->merge_3d[i].base;
0027 b->log_mask = DPU_DBG_MASK_PINGPONG;
0028 return &m->merge_3d[i];
0029 }
0030 }
0031
0032 return ERR_PTR(-EINVAL);
0033 }
0034
0035 static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d,
0036 enum dpu_3d_blend_mode mode_3d)
0037 {
0038 struct dpu_hw_blk_reg_map *c;
0039 u32 data;
0040
0041
0042 c = &merge_3d->hw;
0043 if (mode_3d == BLEND_3D_NONE) {
0044 DPU_REG_WRITE(c, MERGE_3D_MODE, 0);
0045 DPU_REG_WRITE(c, MERGE_3D_MUX, 0);
0046 } else {
0047 data = BIT(0) | ((mode_3d - 1) << 1);
0048 DPU_REG_WRITE(c, MERGE_3D_MODE, data);
0049 }
0050 }
0051
0052 static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c,
0053 unsigned long features)
0054 {
0055 c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;
0056 };
0057
0058 struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx,
0059 void __iomem *addr,
0060 const struct dpu_mdss_cfg *m)
0061 {
0062 struct dpu_hw_merge_3d *c;
0063 const struct dpu_merge_3d_cfg *cfg;
0064
0065 c = kzalloc(sizeof(*c), GFP_KERNEL);
0066 if (!c)
0067 return ERR_PTR(-ENOMEM);
0068
0069 cfg = _merge_3d_offset(idx, m, addr, &c->hw);
0070 if (IS_ERR_OR_NULL(cfg)) {
0071 kfree(c);
0072 return ERR_PTR(-EINVAL);
0073 }
0074
0075 c->idx = idx;
0076 c->caps = cfg;
0077 _setup_merge_3d_ops(c, c->caps->features);
0078
0079 return c;
0080 }
0081
0082 void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw)
0083 {
0084 kfree(hw);
0085 }