disp/dpu1/dpu_hw_mdss.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0003  */
0004
0005 #ifndef _DPU_HW_MDSS_H
0006 #define _DPU_HW_MDSS_H
0007
0008 #include <linux/kernel.h>
0009 #include <linux/err.h>
0010
0011 #include "msm_drv.h"
0012
0013 #define DPU_DBG_NAME            "dpu"
0014
0015 #define DPU_NONE                        0
0016
0017 #ifndef DPU_CSC_MATRIX_COEFF_SIZE
0018 #define DPU_CSC_MATRIX_COEFF_SIZE   9
0019 #endif
0020
0021 #ifndef DPU_CSC_CLAMP_SIZE
0022 #define DPU_CSC_CLAMP_SIZE      6
0023 #endif
0024
0025 #ifndef DPU_CSC_BIAS_SIZE
0026 #define DPU_CSC_BIAS_SIZE       3
0027 #endif
0028
0029 #ifndef DPU_MAX_PLANES
0030 #define DPU_MAX_PLANES          4
0031 #endif
0032
0033 #define PIPES_PER_STAGE         2
0034 #ifndef DPU_MAX_DE_CURVES
0035 #define DPU_MAX_DE_CURVES       3
0036 #endif
0037
0038 enum dpu_format_flags {
0039     DPU_FORMAT_FLAG_YUV_BIT,
0040     DPU_FORMAT_FLAG_DX_BIT,
0041     DPU_FORMAT_FLAG_COMPRESSED_BIT,
0042     DPU_FORMAT_FLAG_BIT_MAX,
0043 };
0044
0045 #define DPU_FORMAT_FLAG_YUV     BIT(DPU_FORMAT_FLAG_YUV_BIT)
0046 #define DPU_FORMAT_FLAG_DX      BIT(DPU_FORMAT_FLAG_DX_BIT)
0047 #define DPU_FORMAT_FLAG_COMPRESSED  BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
0048 #define DPU_FORMAT_IS_YUV(X)        \
0049     (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
0050 #define DPU_FORMAT_IS_DX(X)     \
0051     (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
0052 #define DPU_FORMAT_IS_LINEAR(X)     ((X)->fetch_mode == DPU_FETCH_LINEAR)
0053 #define DPU_FORMAT_IS_TILE(X) \
0054     (((X)->fetch_mode == DPU_FETCH_UBWC) && \
0055             !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
0056 #define DPU_FORMAT_IS_UBWC(X) \
0057     (((X)->fetch_mode == DPU_FETCH_UBWC) && \
0058             test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
0059
0060 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
0061 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
0062 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
0063 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0)
0064 #define DPU_BLEND_FG_INV_ALPHA      (1 << 2)
0065 #define DPU_BLEND_FG_MOD_ALPHA      (1 << 3)
0066 #define DPU_BLEND_FG_INV_MOD_ALPHA  (1 << 4)
0067 #define DPU_BLEND_FG_TRANSP_EN      (1 << 5)
0068 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8)
0069 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8)
0070 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8)
0071 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8)
0072 #define DPU_BLEND_BG_INV_ALPHA      (1 << 10)
0073 #define DPU_BLEND_BG_MOD_ALPHA      (1 << 11)
0074 #define DPU_BLEND_BG_INV_MOD_ALPHA  (1 << 12)
0075 #define DPU_BLEND_BG_TRANSP_EN      (1 << 13)
0076
0077 #define DPU_VSYNC0_SOURCE_GPIO      0
0078 #define DPU_VSYNC1_SOURCE_GPIO      1
0079 #define DPU_VSYNC2_SOURCE_GPIO      2
0080 #define DPU_VSYNC_SOURCE_INTF_0     3
0081 #define DPU_VSYNC_SOURCE_INTF_1     4
0082 #define DPU_VSYNC_SOURCE_INTF_2     5
0083 #define DPU_VSYNC_SOURCE_INTF_3     6
0084 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11
0085 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12
0086 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13
0087 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14
0088 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15
0089
0090 enum dpu_hw_blk_type {
0091     DPU_HW_BLK_TOP = 0,
0092     DPU_HW_BLK_SSPP,
0093     DPU_HW_BLK_LM,
0094     DPU_HW_BLK_CTL,
0095     DPU_HW_BLK_PINGPONG,
0096     DPU_HW_BLK_INTF,
0097     DPU_HW_BLK_WB,
0098     DPU_HW_BLK_DSPP,
0099     DPU_HW_BLK_MERGE_3D,
0100     DPU_HW_BLK_DSC,
0101     DPU_HW_BLK_MAX,
0102 };
0103
0104 enum dpu_mdp {
0105     MDP_TOP = 0x1,
0106     MDP_MAX,
0107 };
0108
0109 enum dpu_sspp {
0110     SSPP_NONE,
0111     SSPP_VIG0,
0112     SSPP_VIG1,
0113     SSPP_VIG2,
0114     SSPP_VIG3,
0115     SSPP_RGB0,
0116     SSPP_RGB1,
0117     SSPP_RGB2,
0118     SSPP_RGB3,
0119     SSPP_DMA0,
0120     SSPP_DMA1,
0121     SSPP_DMA2,
0122     SSPP_DMA3,
0123     SSPP_CURSOR0,
0124     SSPP_CURSOR1,
0125     SSPP_MAX
0126 };
0127
0128 enum dpu_sspp_type {
0129     SSPP_TYPE_VIG,
0130     SSPP_TYPE_RGB,
0131     SSPP_TYPE_DMA,
0132     SSPP_TYPE_CURSOR,
0133     SSPP_TYPE_MAX
0134 };
0135
0136 enum dpu_lm {
0137     LM_0 = 1,
0138     LM_1,
0139     LM_2,
0140     LM_3,
0141     LM_4,
0142     LM_5,
0143     LM_6,
0144     LM_MAX
0145 };
0146
0147 enum dpu_stage {
0148     DPU_STAGE_BASE = 0,
0149     DPU_STAGE_0,
0150     DPU_STAGE_1,
0151     DPU_STAGE_2,
0152     DPU_STAGE_3,
0153     DPU_STAGE_4,
0154     DPU_STAGE_5,
0155     DPU_STAGE_6,
0156     DPU_STAGE_7,
0157     DPU_STAGE_8,
0158     DPU_STAGE_9,
0159     DPU_STAGE_10,
0160     DPU_STAGE_MAX
0161 };
0162 enum dpu_dspp {
0163     DSPP_0 = 1,
0164     DSPP_1,
0165     DSPP_2,
0166     DSPP_3,
0167     DSPP_MAX
0168 };
0169
0170 enum dpu_ctl {
0171     CTL_0 = 1,
0172     CTL_1,
0173     CTL_2,
0174     CTL_3,
0175     CTL_4,
0176     CTL_5,
0177     CTL_MAX
0178 };
0179
0180 enum dpu_dsc {
0181     DSC_NONE = 0,
0182     DSC_0,
0183     DSC_1,
0184     DSC_2,
0185     DSC_3,
0186     DSC_4,
0187     DSC_5,
0188     DSC_MAX
0189 };
0190
0191 enum dpu_pingpong {
0192     PINGPONG_0 = 1,
0193     PINGPONG_1,
0194     PINGPONG_2,
0195     PINGPONG_3,
0196     PINGPONG_4,
0197     PINGPONG_5,
0198     PINGPONG_S0,
0199     PINGPONG_MAX
0200 };
0201
0202 enum dpu_merge_3d {
0203     MERGE_3D_0 = 1,
0204     MERGE_3D_1,
0205     MERGE_3D_2,
0206     MERGE_3D_MAX
0207 };
0208
0209 enum dpu_intf {
0210     INTF_0 = 1,
0211     INTF_1,
0212     INTF_2,
0213     INTF_3,
0214     INTF_4,
0215     INTF_5,
0216     INTF_6,
0217     INTF_MAX
0218 };
0219
0220 /*
0221  * Historically these values correspond to the values written to the
0222  * DISP_INTF_SEL register, which had to programmed manually. On newer MDP
0223  * generations this register is NOP, but we keep the values for historical
0224  * reasons.
0225  */
0226 enum dpu_intf_type {
0227     INTF_NONE = 0x0,
0228     INTF_DSI = 0x1,
0229     INTF_HDMI = 0x3,
0230     INTF_LCDC = 0x5,
0231     /* old eDP found on 8x74 and 8x84 */
0232     INTF_EDP = 0x9,
0233     /* both DP and eDP,  handled by the new DP driver */
0234     INTF_DP = 0xa,
0235
0236     /* virtual interfaces */
0237     INTF_WB = 0x100,
0238 };
0239
0240 enum dpu_intf_mode {
0241     INTF_MODE_NONE = 0,
0242     INTF_MODE_CMD,
0243     INTF_MODE_VIDEO,
0244     INTF_MODE_WB_BLOCK,
0245     INTF_MODE_WB_LINE,
0246     INTF_MODE_MAX
0247 };
0248
0249 enum dpu_wb {
0250     WB_0 = 1,
0251     WB_1,
0252     WB_2,
0253     WB_3,
0254     WB_MAX
0255 };
0256
0257 enum dpu_cwb {
0258     CWB_0 = 0x1,
0259     CWB_1,
0260     CWB_2,
0261     CWB_3,
0262     CWB_MAX
0263 };
0264
0265 enum dpu_wd_timer {
0266     WD_TIMER_0 = 0x1,
0267     WD_TIMER_1,
0268     WD_TIMER_2,
0269     WD_TIMER_3,
0270     WD_TIMER_4,
0271     WD_TIMER_5,
0272     WD_TIMER_MAX
0273 };
0274
0275 enum dpu_vbif {
0276     VBIF_0,
0277     VBIF_1,
0278     VBIF_MAX,
0279     VBIF_RT = VBIF_0,
0280     VBIF_NRT = VBIF_1
0281 };
0282
0283 /**
0284  * DPU HW,Component order color map
0285  */
0286 enum {
0287     C0_G_Y = 0,
0288     C1_B_Cb = 1,
0289     C2_R_Cr = 2,
0290     C3_ALPHA = 3
0291 };
0292
0293 /**
0294  * enum dpu_plane_type - defines how the color component pixel packing
0295  * @DPU_PLANE_INTERLEAVED   : Color components in single plane
0296  * @DPU_PLANE_PLANAR        : Color component in separate planes
0297  * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
0298  */
0299 enum dpu_plane_type {
0300     DPU_PLANE_INTERLEAVED,
0301     DPU_PLANE_PLANAR,
0302     DPU_PLANE_PSEUDO_PLANAR,
0303 };
0304
0305 /**
0306  * enum dpu_chroma_samp_type - chroma sub-samplng type
0307  * @DPU_CHROMA_RGB   : No chroma subsampling
0308  * @DPU_CHROMA_H2V1  : Chroma pixels are horizontally subsampled
0309  * @DPU_CHROMA_H1V2  : Chroma pixels are vertically subsampled
0310  * @DPU_CHROMA_420   : 420 subsampling
0311  */
0312 enum dpu_chroma_samp_type {
0313     DPU_CHROMA_RGB,
0314     DPU_CHROMA_H2V1,
0315     DPU_CHROMA_H1V2,
0316     DPU_CHROMA_420
0317 };
0318
0319 /**
0320  * dpu_fetch_type - Defines How DPU HW fetches data
0321  * @DPU_FETCH_LINEAR   : fetch is line by line
0322  * @DPU_FETCH_TILE     : fetches data in Z order from a tile
0323  * @DPU_FETCH_UBWC     : fetch and decompress data
0324  */
0325 enum dpu_fetch_type {
0326     DPU_FETCH_LINEAR,
0327     DPU_FETCH_TILE,
0328     DPU_FETCH_UBWC
0329 };
0330
0331 /**
0332  * Value of enum chosen to fit the number of bits
0333  * expected by the HW programming.
0334  */
0335 enum {
0336     COLOR_ALPHA_1BIT = 0,
0337     COLOR_ALPHA_4BIT = 1,
0338     COLOR_4BIT = 0,
0339     COLOR_5BIT = 1, /* No 5-bit Alpha */
0340     COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
0341     COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
0342 };
0343
0344 /**
0345  * enum dpu_3d_blend_mode
0346  * Desribes how the 3d data is blended
0347  * @BLEND_3D_NONE      : 3d blending not enabled
0348  * @BLEND_3D_FRAME_INT : Frame interleaving
0349  * @BLEND_3D_H_ROW_INT : Horizontal row interleaving
0350  * @BLEND_3D_V_ROW_INT : vertical row interleaving
0351  * @BLEND_3D_COL_INT   : column interleaving
0352  * @BLEND_3D_MAX       :
0353  */
0354 enum dpu_3d_blend_mode {
0355     BLEND_3D_NONE = 0,
0356     BLEND_3D_FRAME_INT,
0357     BLEND_3D_H_ROW_INT,
0358     BLEND_3D_V_ROW_INT,
0359     BLEND_3D_COL_INT,
0360     BLEND_3D_MAX
0361 };
0362
0363 /** struct dpu_format - defines the format configuration which
0364  * allows DPU HW to correctly fetch and decode the format
0365  * @base: base msm_format structure containing fourcc code
0366  * @fetch_planes: how the color components are packed in pixel format
0367  * @element: element color ordering
0368  * @bits: element bit widths
0369  * @chroma_sample: chroma sub-samplng type
0370  * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
0371  * @unpack_tight: 0 for loose, 1 for tight
0372  * @unpack_count: 0 = 1 component, 1 = 2 component
0373  * @bpp: bytes per pixel
0374  * @alpha_enable: whether the format has an alpha channel
0375  * @num_planes: number of planes (including meta data planes)
0376  * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
0377  * @flag: usage bit flags
0378  * @tile_width: format tile width
0379  * @tile_height: format tile height
0380  */
0381 struct dpu_format {
0382     struct msm_format base;
0383     enum dpu_plane_type fetch_planes;
0384     u8 element[DPU_MAX_PLANES];
0385     u8 bits[DPU_MAX_PLANES];
0386     enum dpu_chroma_samp_type chroma_sample;
0387     u8 unpack_align_msb;
0388     u8 unpack_tight;
0389     u8 unpack_count;
0390     u8 bpp;
0391     u8 alpha_enable;
0392     u8 num_planes;
0393     enum dpu_fetch_type fetch_mode;
0394     DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
0395     u16 tile_width;
0396     u16 tile_height;
0397 };
0398 #define to_dpu_format(x) container_of(x, struct dpu_format, base)
0399
0400 /**
0401  * struct dpu_hw_fmt_layout - format information of the source pixel data
0402  * @format: pixel format parameters
0403  * @num_planes: number of planes (including meta data planes)
0404  * @width: image width
0405  * @height: image height
0406  * @total_size: total size in bytes
0407  * @plane_addr: address of each plane
0408  * @plane_size: length of each plane
0409  * @plane_pitch: pitch of each plane
0410  */
0411 struct dpu_hw_fmt_layout {
0412     const struct dpu_format *format;
0413     uint32_t num_planes;
0414     uint32_t width;
0415     uint32_t height;
0416     uint32_t total_size;
0417     uint32_t plane_addr[DPU_MAX_PLANES];
0418     uint32_t plane_size[DPU_MAX_PLANES];
0419     uint32_t plane_pitch[DPU_MAX_PLANES];
0420 };
0421
0422 struct dpu_csc_cfg {
0423     /* matrix coefficients in S15.16 format */
0424     uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE];
0425     uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE];
0426     uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE];
0427     uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE];
0428     uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE];
0429 };
0430
0431 /**
0432  * struct dpu_mdss_color - mdss color description
0433  * color 0 : green
0434  * color 1 : blue
0435  * color 2 : red
0436  * color 3 : alpha
0437  */
0438 struct dpu_mdss_color {
0439     u32 color_0;
0440     u32 color_1;
0441     u32 color_2;
0442     u32 color_3;
0443 };
0444
0445 /*
0446  * Define bit masks for h/w logging.
0447  */
0448 #define DPU_DBG_MASK_NONE     (1 << 0)
0449 #define DPU_DBG_MASK_INTF     (1 << 1)
0450 #define DPU_DBG_MASK_LM       (1 << 2)
0451 #define DPU_DBG_MASK_CTL      (1 << 3)
0452 #define DPU_DBG_MASK_PINGPONG (1 << 4)
0453 #define DPU_DBG_MASK_SSPP     (1 << 5)
0454 #define DPU_DBG_MASK_WB       (1 << 6)
0455 #define DPU_DBG_MASK_TOP      (1 << 7)
0456 #define DPU_DBG_MASK_VBIF     (1 << 8)
0457 #define DPU_DBG_MASK_ROT      (1 << 9)
0458 #define DPU_DBG_MASK_DSPP     (1 << 10)
0459 #define DPU_DBG_MASK_DSC      (1 << 11)
0460
0461 #endif  /* _DPU_HW_MDSS_H */