disp/dpu1/dpu_hw_lm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef _DPU_HW_LM_H
0007 #define _DPU_HW_LM_H
0008
0009 #include "dpu_hw_mdss.h"
0010 #include "dpu_hw_util.h"
0011
0012 struct dpu_hw_mixer;
0013
0014 struct dpu_hw_mixer_cfg {
0015     u32 out_width;
0016     u32 out_height;
0017     bool right_mixer;
0018     int flags;
0019 };
0020
0021 struct dpu_hw_color3_cfg {
0022     u8 keep_fg[DPU_STAGE_MAX];
0023 };
0024
0025 /**
0026  *
0027  * struct dpu_hw_lm_ops : Interface to the mixer Hw driver functions
0028  *  Assumption is these functions will be called after clocks are enabled
0029  */
0030 struct dpu_hw_lm_ops {
0031     /*
0032      * Sets up mixer output width and height
0033      * and border color if enabled
0034      */
0035     void (*setup_mixer_out)(struct dpu_hw_mixer *ctx,
0036         struct dpu_hw_mixer_cfg *cfg);
0037
0038     /*
0039      * Alpha blending configuration
0040      * for the specified stage
0041      */
0042     void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage,
0043         uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op);
0044
0045     /*
0046      * Alpha color component selection from either fg or bg
0047      */
0048     void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op);
0049
0050     /**
0051      * setup_border_color : enable/disable border color
0052      */
0053     void (*setup_border_color)(struct dpu_hw_mixer *ctx,
0054         struct dpu_mdss_color *color,
0055         u8 border_en);
0056
0057     /**
0058      * setup_misr: Enable/disable MISR
0059      */
0060     void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count);
0061
0062     /**
0063      * collect_misr: Read MISR signature
0064      */
0065     int (*collect_misr)(struct dpu_hw_mixer *ctx, u32 *misr_value);
0066 };
0067
0068 struct dpu_hw_mixer {
0069     struct dpu_hw_blk base;
0070     struct dpu_hw_blk_reg_map hw;
0071
0072     /* lm */
0073     enum dpu_lm  idx;
0074     const struct dpu_lm_cfg   *cap;
0075     const struct dpu_mdp_cfg  *mdp;
0076     const struct dpu_ctl_cfg  *ctl;
0077
0078     /* ops */
0079     struct dpu_hw_lm_ops ops;
0080
0081     /* store mixer info specific to display */
0082     struct dpu_hw_mixer_cfg cfg;
0083 };
0084
0085 /**
0086  * to_dpu_hw_mixer - convert base object dpu_hw_base to container
0087  * @hw: Pointer to base hardware block
0088  * return: Pointer to hardware block container
0089  */
0090 static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw)
0091 {
0092     return container_of(hw, struct dpu_hw_mixer, base);
0093 }
0094
0095 /**
0096  * dpu_hw_lm_init(): Initializes the mixer hw driver object.
0097  * should be called once before accessing every mixer.
0098  * @idx:  mixer index for which driver object is required
0099  * @addr: mapped register io address of MDP
0100  * @m :   pointer to mdss catalog data
0101  */
0102 struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
0103         void __iomem *addr,
0104         const struct dpu_mdss_cfg *m);
0105
0106 /**
0107  * dpu_hw_lm_destroy(): Destroys layer mixer driver context
0108  * @lm:   Pointer to LM driver context
0109  */
0110 void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm);
0111
0112 #endif /*_DPU_HW_LM_H */