disp/dpu1/dpu_hw_intf.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
0004  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0005  */
0006
0007 #ifndef _DPU_HW_INTF_H
0008 #define _DPU_HW_INTF_H
0009
0010 #include "dpu_hw_catalog.h"
0011 #include "dpu_hw_mdss.h"
0012 #include "dpu_hw_util.h"
0013
0014 struct dpu_hw_intf;
0015
0016 /* intf timing settings */
0017 struct intf_timing_params {
0018     u32 width;      /* active width */
0019     u32 height;     /* active height */
0020     u32 xres;       /* Display panel width */
0021     u32 yres;       /* Display panel height */
0022
0023     u32 h_back_porch;
0024     u32 h_front_porch;
0025     u32 v_back_porch;
0026     u32 v_front_porch;
0027     u32 hsync_pulse_width;
0028     u32 vsync_pulse_width;
0029     u32 hsync_polarity;
0030     u32 vsync_polarity;
0031     u32 border_clr;
0032     u32 underflow_clr;
0033     u32 hsync_skew;
0034
0035     bool wide_bus_en;
0036 };
0037
0038 struct intf_prog_fetch {
0039     u8 enable;
0040     /* vsync counter for the front porch pixel line */
0041     u32 fetch_start;
0042 };
0043
0044 struct intf_status {
0045     u8 is_en;       /* interface timing engine is enabled or not */
0046     u8 is_prog_fetch_en;    /* interface prog fetch counter is enabled or not */
0047     u32 frame_count;    /* frame count since timing engine enabled */
0048     u32 line_count;     /* current line count including blanking */
0049 };
0050
0051 /**
0052  * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions
0053  *  Assumption is these functions will be called after clocks are enabled
0054  * @ setup_timing_gen : programs the timing engine
0055  * @ setup_prog_fetch : enables/disables the programmable fetch logic
0056  * @ enable_timing: enable/disable timing engine
0057  * @ get_status: returns if timing engine is enabled or not
0058  * @ get_line_count: reads current vertical line counter
0059  * @bind_pingpong_blk: enable/disable the connection with pingpong which will
0060  *                     feed pixels to this interface
0061  * @setup_misr: enable/disable MISR
0062  * @collect_misr: read MISR signature
0063  */
0064 struct dpu_hw_intf_ops {
0065     void (*setup_timing_gen)(struct dpu_hw_intf *intf,
0066             const struct intf_timing_params *p,
0067             const struct dpu_format *fmt);
0068
0069     void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
0070             const struct intf_prog_fetch *fetch);
0071
0072     void (*enable_timing)(struct dpu_hw_intf *intf,
0073             u8 enable);
0074
0075     void (*get_status)(struct dpu_hw_intf *intf,
0076             struct intf_status *status);
0077
0078     u32 (*get_line_count)(struct dpu_hw_intf *intf);
0079
0080     void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
0081             bool enable,
0082             const enum dpu_pingpong pp);
0083     void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);
0084     int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
0085 };
0086
0087 struct dpu_hw_intf {
0088     struct dpu_hw_blk_reg_map hw;
0089
0090     /* intf */
0091     enum dpu_intf idx;
0092     const struct dpu_intf_cfg *cap;
0093     const struct dpu_mdss_cfg *mdss;
0094
0095     /* ops */
0096     struct dpu_hw_intf_ops ops;
0097 };
0098
0099 /**
0100  * dpu_hw_intf_init(): Initializes the intf driver for the passed
0101  * interface idx.
0102  * @idx:  interface index for which driver object is required
0103  * @addr: mapped register io address of MDP
0104  * @m :   pointer to mdss catalog data
0105  */
0106 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
0107         void __iomem *addr,
0108         const struct dpu_mdss_cfg *m);
0109
0110 /**
0111  * dpu_hw_intf_destroy(): Destroys INTF driver context
0112  * @intf:   Pointer to INTF driver context
0113  */
0114 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf);
0115
0116 #endif /*_DPU_HW_INTF_H */