disp/dpu1/dpu_hw_dsc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2020-2022, Linaro Limited */
0003
0004 #ifndef _DPU_HW_DSC_H
0005 #define _DPU_HW_DSC_H
0006
0007 #include <drm/display/drm_dsc.h>
0008
0009 #define DSC_MODE_SPLIT_PANEL            BIT(0)
0010 #define DSC_MODE_MULTIPLEX              BIT(1)
0011 #define DSC_MODE_VIDEO                  BIT(2)
0012
0013 struct dpu_hw_dsc;
0014
0015 /**
0016  * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
0017  * Assumption is these functions will be called after clocks are enabled
0018  */
0019 struct dpu_hw_dsc_ops {
0020     /**
0021      * dsc_disable - disable dsc
0022      * @hw_dsc: Pointer to dsc context
0023      */
0024     void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
0025
0026     /**
0027      * dsc_config - configures dsc encoder
0028      * @hw_dsc: Pointer to dsc context
0029      * @dsc: panel dsc parameters
0030      * @mode: dsc topology mode to be set
0031      * @initial_lines: amount of initial lines to be used
0032      */
0033     void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
0034                struct msm_display_dsc_config *dsc,
0035                u32 mode,
0036                u32 initial_lines);
0037
0038     /**
0039      * dsc_config_thresh - programs panel thresholds
0040      * @hw_dsc: Pointer to dsc context
0041      * @dsc: panel dsc parameters
0042      */
0043     void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
0044                   struct msm_display_dsc_config *dsc);
0045 };
0046
0047 struct dpu_hw_dsc {
0048     struct dpu_hw_blk base;
0049     struct dpu_hw_blk_reg_map hw;
0050
0051     /* dsc */
0052     enum dpu_dsc idx;
0053     const struct dpu_dsc_cfg *caps;
0054
0055     /* ops */
0056     struct dpu_hw_dsc_ops ops;
0057 };
0058
0059 /**
0060  * dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
0061  * @idx:  DSC index for which driver object is required
0062  * @addr: Mapped register io address of MDP
0063  * @m:    Pointer to mdss catalog data
0064  * Returns: Error code or allocated dpu_hw_dsc context
0065  */
0066 struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
0067                    const struct dpu_mdss_cfg *m);
0068
0069 /**
0070  * dpu_hw_dsc_destroy - destroys dsc driver context
0071  * @dsc:   Pointer to dsc driver context returned by dpu_hw_dsc_init
0072  */
0073 void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
0074
0075 static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
0076 {
0077     return container_of(hw, struct dpu_hw_dsc, base);
0078 }
0079
0080 #endif /* _DPU_HW_DSC_H */