disp/dpu1/dpu_hw_dsc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2020-2022, Linaro Limited
0004  */
0005
0006 #include "dpu_kms.h"
0007 #include "dpu_hw_catalog.h"
0008 #include "dpu_hwio.h"
0009 #include "dpu_hw_mdss.h"
0010 #include "dpu_hw_dsc.h"
0011
0012 #define DSC_COMMON_MODE                 0x000
0013 #define DSC_ENC                         0x004
0014 #define DSC_PICTURE                     0x008
0015 #define DSC_SLICE                       0x00C
0016 #define DSC_CHUNK_SIZE                  0x010
0017 #define DSC_DELAY                       0x014
0018 #define DSC_SCALE_INITIAL               0x018
0019 #define DSC_SCALE_DEC_INTERVAL          0x01C
0020 #define DSC_SCALE_INC_INTERVAL          0x020
0021 #define DSC_FIRST_LINE_BPG_OFFSET       0x024
0022 #define DSC_BPG_OFFSET                  0x028
0023 #define DSC_DSC_OFFSET                  0x02C
0024 #define DSC_FLATNESS                    0x030
0025 #define DSC_RC_MODEL_SIZE               0x034
0026 #define DSC_RC                          0x038
0027 #define DSC_RC_BUF_THRESH               0x03C
0028 #define DSC_RANGE_MIN_QP                0x074
0029 #define DSC_RANGE_MAX_QP                0x0B0
0030 #define DSC_RANGE_BPG_OFFSET            0x0EC
0031
0032 static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
0033 {
0034     struct dpu_hw_blk_reg_map *c = &dsc->hw;
0035
0036     DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
0037 }
0038
0039 static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
0040                   struct msm_display_dsc_config *dsc,
0041                   u32 mode,
0042                   u32 initial_lines)
0043 {
0044     struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
0045     u32 data, lsb, bpp;
0046     u32 slice_last_group_size;
0047     u32 det_thresh_flatness;
0048     bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
0049
0050     DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
0051
0052     if (is_cmd_mode)
0053         initial_lines += 1;
0054
0055     slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
0056     data = (initial_lines << 20);
0057     data |= ((slice_last_group_size - 1) << 18);
0058     /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
0059     data |= dsc->drm->bits_per_pixel << 12;
0060     lsb = dsc->drm->bits_per_pixel % 4;
0061     bpp = dsc->drm->bits_per_pixel / 4;
0062     bpp *= 4;
0063     bpp <<= 4;
0064     bpp |= lsb;
0065
0066     data |= bpp << 8;
0067     data |= (dsc->drm->block_pred_enable << 7);
0068     data |= (dsc->drm->line_buf_depth << 3);
0069     data |= (dsc->drm->simple_422 << 2);
0070     data |= (dsc->drm->convert_rgb << 1);
0071     data |= dsc->drm->bits_per_component;
0072
0073     DPU_REG_WRITE(c, DSC_ENC, data);
0074
0075     data = dsc->drm->pic_width << 16;
0076     data |= dsc->drm->pic_height;
0077     DPU_REG_WRITE(c, DSC_PICTURE, data);
0078
0079     data = dsc->drm->slice_width << 16;
0080     data |= dsc->drm->slice_height;
0081     DPU_REG_WRITE(c, DSC_SLICE, data);
0082
0083     data = dsc->drm->slice_chunk_size << 16;
0084     DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
0085
0086     data = dsc->drm->initial_dec_delay << 16;
0087     data |= dsc->drm->initial_xmit_delay;
0088     DPU_REG_WRITE(c, DSC_DELAY, data);
0089
0090     data = dsc->drm->initial_scale_value;
0091     DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
0092
0093     data = dsc->drm->scale_decrement_interval;
0094     DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
0095
0096     data = dsc->drm->scale_increment_interval;
0097     DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
0098
0099     data = dsc->drm->first_line_bpg_offset;
0100     DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
0101
0102     data = dsc->drm->nfl_bpg_offset << 16;
0103     data |= dsc->drm->slice_bpg_offset;
0104     DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
0105
0106     data = dsc->drm->initial_offset << 16;
0107     data |= dsc->drm->final_offset;
0108     DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
0109
0110     det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
0111     data = det_thresh_flatness << 10;
0112     data |= dsc->drm->flatness_max_qp << 5;
0113     data |= dsc->drm->flatness_min_qp;
0114     DPU_REG_WRITE(c, DSC_FLATNESS, data);
0115
0116     data = dsc->drm->rc_model_size;
0117     DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
0118
0119     data = dsc->drm->rc_tgt_offset_low << 18;
0120     data |= dsc->drm->rc_tgt_offset_high << 14;
0121     data |= dsc->drm->rc_quant_incr_limit1 << 9;
0122     data |= dsc->drm->rc_quant_incr_limit0 << 4;
0123     data |= dsc->drm->rc_edge_factor;
0124     DPU_REG_WRITE(c, DSC_RC, data);
0125 }
0126
0127 static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
0128                      struct msm_display_dsc_config *dsc)
0129 {
0130     struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
0131     struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
0132     u32 off;
0133     int i;
0134
0135     off = DSC_RC_BUF_THRESH;
0136     for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
0137         DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
0138         off += 4;
0139     }
0140
0141     off = DSC_RANGE_MIN_QP;
0142     for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
0143         DPU_REG_WRITE(c, off, rc[i].range_min_qp);
0144         off += 4;
0145     }
0146
0147     off = DSC_RANGE_MAX_QP;
0148     for (i = 0; i < 15; i++) {
0149         DPU_REG_WRITE(c, off, rc[i].range_max_qp);
0150         off += 4;
0151     }
0152
0153     off = DSC_RANGE_BPG_OFFSET;
0154     for (i = 0; i < 15; i++) {
0155         DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
0156         off += 4;
0157     }
0158 }
0159
0160 static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
0161                        const struct dpu_mdss_cfg *m,
0162                        void __iomem *addr,
0163                        struct dpu_hw_blk_reg_map *b)
0164 {
0165     int i;
0166
0167     for (i = 0; i < m->dsc_count; i++) {
0168         if (dsc == m->dsc[i].id) {
0169             b->blk_addr = addr + m->dsc[i].base;
0170             b->log_mask = DPU_DBG_MASK_DSC;
0171             return &m->dsc[i];
0172         }
0173     }
0174
0175     return NULL;
0176 }
0177
0178 static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
0179                unsigned long cap)
0180 {
0181     ops->dsc_disable = dpu_hw_dsc_disable;
0182     ops->dsc_config = dpu_hw_dsc_config;
0183     ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
0184 };
0185
0186 struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
0187                    const struct dpu_mdss_cfg *m)
0188 {
0189     struct dpu_hw_dsc *c;
0190     struct dpu_dsc_cfg *cfg;
0191
0192     c = kzalloc(sizeof(*c), GFP_KERNEL);
0193     if (!c)
0194         return ERR_PTR(-ENOMEM);
0195
0196     cfg = _dsc_offset(idx, m, addr, &c->hw);
0197     if (IS_ERR_OR_NULL(cfg)) {
0198         kfree(c);
0199         return ERR_PTR(-EINVAL);
0200     }
0201
0202     c->idx = idx;
0203     c->caps = cfg;
0204     _setup_dsc_ops(&c->ops, c->caps->features);
0205
0206     return c;
0207 }
0208
0209 void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
0210 {
0211     kfree(dsc);
0212 }