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0001 /* SPDX-License-Identifier: GPL-2.0-only */ 0002 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 0003 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 0004 */ 0005 0006 #ifndef _DPU_HW_CTL_H 0007 #define _DPU_HW_CTL_H 0008 0009 #include "dpu_hw_mdss.h" 0010 #include "dpu_hw_util.h" 0011 #include "dpu_hw_catalog.h" 0012 #include "dpu_hw_sspp.h" 0013 0014 /** 0015 * dpu_ctl_mode_sel: Interface mode selection 0016 * DPU_CTL_MODE_SEL_VID: Video mode interface 0017 * DPU_CTL_MODE_SEL_CMD: Command mode interface 0018 */ 0019 enum dpu_ctl_mode_sel { 0020 DPU_CTL_MODE_SEL_VID = 0, 0021 DPU_CTL_MODE_SEL_CMD 0022 }; 0023 0024 struct dpu_hw_ctl; 0025 /** 0026 * struct dpu_hw_stage_cfg - blending stage cfg 0027 * @stage : SSPP_ID at each stage 0028 * @multirect_index: index of the rectangle of SSPP. 0029 */ 0030 struct dpu_hw_stage_cfg { 0031 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; 0032 enum dpu_sspp_multirect_index multirect_index 0033 [DPU_STAGE_MAX][PIPES_PER_STAGE]; 0034 }; 0035 0036 /** 0037 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 0038 * @intf : Interface id 0039 * @mode_3d: 3d mux configuration 0040 * @merge_3d: 3d merge block used 0041 * @intf_mode_sel: Interface mode, cmd / vid 0042 * @stream_sel: Stream selection for multi-stream interfaces 0043 * @dsc: DSC BIT masks used 0044 */ 0045 struct dpu_hw_intf_cfg { 0046 enum dpu_intf intf; 0047 enum dpu_wb wb; 0048 enum dpu_3d_blend_mode mode_3d; 0049 enum dpu_merge_3d merge_3d; 0050 enum dpu_ctl_mode_sel intf_mode_sel; 0051 int stream_sel; 0052 unsigned int dsc; 0053 }; 0054 0055 /** 0056 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions 0057 * Assumption is these functions will be called after clocks are enabled 0058 */ 0059 struct dpu_hw_ctl_ops { 0060 /** 0061 * kickoff hw operation for Sw controlled interfaces 0062 * DSI cmd mode and WB interface are SW controlled 0063 * @ctx : ctl path ctx pointer 0064 */ 0065 void (*trigger_start)(struct dpu_hw_ctl *ctx); 0066 0067 /** 0068 * check if the ctl is started 0069 * @ctx : ctl path ctx pointer 0070 * @Return: true if started, false if stopped 0071 */ 0072 bool (*is_started)(struct dpu_hw_ctl *ctx); 0073 0074 /** 0075 * kickoff prepare is in progress hw operation for sw 0076 * controlled interfaces: DSI cmd mode and WB interface 0077 * are SW controlled 0078 * @ctx : ctl path ctx pointer 0079 */ 0080 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 0081 0082 /** 0083 * Clear the value of the cached pending_flush_mask 0084 * No effect on hardware 0085 * @ctx : ctl path ctx pointer 0086 */ 0087 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 0088 0089 /** 0090 * Query the value of the cached pending_flush_mask 0091 * No effect on hardware 0092 * @ctx : ctl path ctx pointer 0093 */ 0094 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 0095 0096 /** 0097 * OR in the given flushbits to the cached pending_flush_mask 0098 * No effect on hardware 0099 * @ctx : ctl path ctx pointer 0100 * @flushbits : module flushmask 0101 */ 0102 void (*update_pending_flush)(struct dpu_hw_ctl *ctx, 0103 u32 flushbits); 0104 0105 /** 0106 * OR in the given flushbits to the cached pending_(wb_)flush_mask 0107 * No effect on hardware 0108 * @ctx : ctl path ctx pointer 0109 * @blk : writeback block index 0110 */ 0111 void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx, 0112 enum dpu_wb blk); 0113 0114 /** 0115 * OR in the given flushbits to the cached pending_(intf_)flush_mask 0116 * No effect on hardware 0117 * @ctx : ctl path ctx pointer 0118 * @blk : interface block index 0119 */ 0120 void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx, 0121 enum dpu_intf blk); 0122 0123 /** 0124 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask 0125 * No effect on hardware 0126 * @ctx : ctl path ctx pointer 0127 * @blk : interface block index 0128 */ 0129 void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx, 0130 enum dpu_merge_3d blk); 0131 0132 /** 0133 * Write the value of the pending_flush_mask to hardware 0134 * @ctx : ctl path ctx pointer 0135 */ 0136 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 0137 0138 /** 0139 * Read the value of the flush register 0140 * @ctx : ctl path ctx pointer 0141 * @Return: value of the ctl flush register. 0142 */ 0143 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 0144 0145 /** 0146 * Setup ctl_path interface config 0147 * @ctx 0148 * @cfg : interface config structure pointer 0149 */ 0150 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, 0151 struct dpu_hw_intf_cfg *cfg); 0152 0153 /** 0154 * reset ctl_path interface config 0155 * @ctx : ctl path ctx pointer 0156 * @cfg : interface config structure pointer 0157 */ 0158 void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx, 0159 struct dpu_hw_intf_cfg *cfg); 0160 0161 int (*reset)(struct dpu_hw_ctl *c); 0162 0163 /* 0164 * wait_reset_status - checks ctl reset status 0165 * @ctx : ctl path ctx pointer 0166 * 0167 * This function checks the ctl reset status bit. 0168 * If the reset bit is set, it keeps polling the status till the hw 0169 * reset is complete. 0170 * Returns: 0 on success or -error if reset incomplete within interval 0171 */ 0172 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 0173 0174 uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx, 0175 enum dpu_sspp blk); 0176 0177 uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx, 0178 enum dpu_lm blk); 0179 0180 uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx, 0181 enum dpu_dspp blk); 0182 0183 /** 0184 * Set all blend stages to disabled 0185 * @ctx : ctl path ctx pointer 0186 */ 0187 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 0188 0189 /** 0190 * Configure layer mixer to pipe configuration 0191 * @ctx : ctl path ctx pointer 0192 * @lm : layer mixer enumeration 0193 * @cfg : blend stage configuration 0194 */ 0195 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 0196 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 0197 0198 void (*set_active_pipes)(struct dpu_hw_ctl *ctx, 0199 unsigned long *fetch_active); 0200 }; 0201 0202 /** 0203 * struct dpu_hw_ctl : CTL PATH driver object 0204 * @base: hardware block base structure 0205 * @hw: block register map object 0206 * @idx: control path index 0207 * @caps: control path capabilities 0208 * @mixer_count: number of mixers 0209 * @mixer_hw_caps: mixer hardware capabilities 0210 * @pending_flush_mask: storage for pending ctl_flush managed via ops 0211 * @pending_intf_flush_mask: pending INTF flush 0212 * @pending_wb_flush_mask: pending WB flush 0213 * @ops: operation list 0214 */ 0215 struct dpu_hw_ctl { 0216 struct dpu_hw_blk base; 0217 struct dpu_hw_blk_reg_map hw; 0218 0219 /* ctl path */ 0220 int idx; 0221 const struct dpu_ctl_cfg *caps; 0222 int mixer_count; 0223 const struct dpu_lm_cfg *mixer_hw_caps; 0224 u32 pending_flush_mask; 0225 u32 pending_intf_flush_mask; 0226 u32 pending_wb_flush_mask; 0227 u32 pending_merge_3d_flush_mask; 0228 0229 /* ops */ 0230 struct dpu_hw_ctl_ops ops; 0231 }; 0232 0233 /** 0234 * dpu_hw_ctl - convert base object dpu_hw_base to container 0235 * @hw: Pointer to base hardware block 0236 * return: Pointer to hardware block container 0237 */ 0238 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) 0239 { 0240 return container_of(hw, struct dpu_hw_ctl, base); 0241 } 0242 0243 /** 0244 * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object. 0245 * should be called before accessing every ctl path registers. 0246 * @idx: ctl_path index for which driver object is required 0247 * @addr: mapped register io address of MDP 0248 * @m : pointer to mdss catalog data 0249 */ 0250 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, 0251 void __iomem *addr, 0252 const struct dpu_mdss_cfg *m); 0253 0254 /** 0255 * dpu_hw_ctl_destroy(): Destroys ctl driver context 0256 * should be called to free the context 0257 */ 0258 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx); 0259 0260 #endif /*_DPU_HW_CTL_H */
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