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0001 /* SPDX-License-Identifier: GPL-2.0-only */ 0002 /* 0003 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 0004 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 0005 */ 0006 0007 #ifndef _DPU_HW_CATALOG_H 0008 #define _DPU_HW_CATALOG_H 0009 0010 #include <linux/kernel.h> 0011 #include <linux/bug.h> 0012 #include <linux/bitmap.h> 0013 #include <linux/err.h> 0014 0015 /** 0016 * Max hardware block count: For ex: max 12 SSPP pipes or 0017 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 0018 * based on current design 0019 */ 0020 #define MAX_BLOCKS 12 0021 0022 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 0023 ((MINOR & 0xFFF) << 16) |\ 0024 (STEP & 0xFFFF)) 0025 0026 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 0027 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 0028 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 0029 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 0030 0031 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 0032 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 0033 0034 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 0035 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 0036 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 0037 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 0038 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 0039 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 0040 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 0041 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 0042 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ 0043 #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ 0044 #define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ 0045 #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ 0046 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ 0047 #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ 0048 #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ 0049 0050 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 0051 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 0052 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 0053 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 0054 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 0055 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) 0056 #define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) 0057 0058 #define DPU_HW_BLK_NAME_LEN 16 0059 0060 #define MAX_IMG_WIDTH 0x3fff 0061 #define MAX_IMG_HEIGHT 0x3fff 0062 0063 #define CRTC_DUAL_MIXERS 2 0064 0065 #define MAX_XIN_COUNT 16 0066 0067 /** 0068 * Supported UBWC feature versions 0069 */ 0070 enum { 0071 DPU_HW_UBWC_VER_10 = 0x100, 0072 DPU_HW_UBWC_VER_20 = 0x200, 0073 DPU_HW_UBWC_VER_30 = 0x300, 0074 DPU_HW_UBWC_VER_40 = 0x400, 0075 }; 0076 0077 /** 0078 * MDP TOP BLOCK features 0079 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 0080 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 0081 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 0082 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 0083 * compression initial revision 0084 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 0085 * @DPU_MDP_MAX Maximum value 0086 0087 */ 0088 enum { 0089 DPU_MDP_PANIC_PER_PIPE = 0x1, 0090 DPU_MDP_10BIT_SUPPORT, 0091 DPU_MDP_BWC, 0092 DPU_MDP_UBWC_1_0, 0093 DPU_MDP_UBWC_1_5, 0094 DPU_MDP_AUDIO_SELECT, 0095 DPU_MDP_MAX 0096 }; 0097 0098 /** 0099 * SSPP sub-blocks/features 0100 * @DPU_SSPP_SRC Src and fetch part of the pipes, 0101 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 0102 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 0103 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 0104 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 0105 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 0106 * @DPU_SSPP_CSC, Support of Color space converion 0107 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 0108 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 0109 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 0110 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 0111 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 0112 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 0113 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 0114 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 0115 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 0116 * @DPU_SSPP_CDP Supports client driven prefetch 0117 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 0118 * @DPU_SSPP_MAX maximum value 0119 */ 0120 enum { 0121 DPU_SSPP_SRC = 0x1, 0122 DPU_SSPP_SCALER_QSEED2, 0123 DPU_SSPP_SCALER_QSEED3, 0124 DPU_SSPP_SCALER_QSEED3LITE, 0125 DPU_SSPP_SCALER_QSEED4, 0126 DPU_SSPP_SCALER_RGB, 0127 DPU_SSPP_CSC, 0128 DPU_SSPP_CSC_10BIT, 0129 DPU_SSPP_CURSOR, 0130 DPU_SSPP_QOS, 0131 DPU_SSPP_QOS_8LVL, 0132 DPU_SSPP_EXCL_RECT, 0133 DPU_SSPP_SMART_DMA_V1, 0134 DPU_SSPP_SMART_DMA_V2, 0135 DPU_SSPP_TS_PREFILL, 0136 DPU_SSPP_TS_PREFILL_REC1, 0137 DPU_SSPP_CDP, 0138 DPU_SSPP_INLINE_ROTATION, 0139 DPU_SSPP_MAX 0140 }; 0141 0142 /* 0143 * MIXER sub-blocks/features 0144 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 0145 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 0146 * @DPU_MIXER_GC Gamma correction block 0147 * @DPU_DIM_LAYER Layer mixer supports dim layer 0148 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 0149 * @DPU_MIXER_MAX maximum value 0150 */ 0151 enum { 0152 DPU_MIXER_LAYER = 0x1, 0153 DPU_MIXER_SOURCESPLIT, 0154 DPU_MIXER_GC, 0155 DPU_DIM_LAYER, 0156 DPU_MIXER_COMBINED_ALPHA, 0157 DPU_MIXER_MAX 0158 }; 0159 0160 /** 0161 * DSPP sub-blocks 0162 * @DPU_DSPP_PCC Panel color correction block 0163 * @DPU_DSPP_GC Gamma correction block 0164 */ 0165 enum { 0166 DPU_DSPP_PCC = 0x1, 0167 DPU_DSPP_GC, 0168 DPU_DSPP_MAX 0169 }; 0170 0171 /** 0172 * PINGPONG sub-blocks 0173 * @DPU_PINGPONG_TE Tear check block 0174 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 0175 * @DPU_PINGPONG_SPLIT PP block supports split fifo 0176 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 0177 * @DPU_PINGPONG_DITHER, Dither blocks 0178 * @DPU_PINGPONG_MAX 0179 */ 0180 enum { 0181 DPU_PINGPONG_TE = 0x1, 0182 DPU_PINGPONG_TE2, 0183 DPU_PINGPONG_SPLIT, 0184 DPU_PINGPONG_SLAVE, 0185 DPU_PINGPONG_DITHER, 0186 DPU_PINGPONG_MAX 0187 }; 0188 0189 /** 0190 * CTL sub-blocks 0191 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 0192 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 0193 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 0194 * @DPU_CTL_MAX 0195 */ 0196 enum { 0197 DPU_CTL_SPLIT_DISPLAY = 0x1, 0198 DPU_CTL_ACTIVE_CFG, 0199 DPU_CTL_FETCH_ACTIVE, 0200 DPU_CTL_VM_CFG, 0201 DPU_CTL_MAX 0202 }; 0203 0204 /** 0205 * INTF sub-blocks 0206 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 0207 * pixel data arrives to this INTF 0208 * @DPU_INTF_TE INTF block has TE configuration support 0209 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 0210 than video timing 0211 * @DPU_INTF_MAX 0212 */ 0213 enum { 0214 DPU_INTF_INPUT_CTRL = 0x1, 0215 DPU_INTF_TE, 0216 DPU_DATA_HCTL_EN, 0217 DPU_INTF_MAX 0218 }; 0219 0220 /** 0221 * WB sub-blocks and features 0222 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 0223 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 0224 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 0225 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 0226 * @DPU_WB_DITHER, Dither block 0227 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 0228 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 0229 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 0230 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 0231 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 0232 * the destination image 0233 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 0234 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 0235 * @DPU_WB_CDP Writeback supports client driven prefetch 0236 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 0237 * data arrives. 0238 * @DPU_WB_CROP CWB supports cropping 0239 * @DPU_WB_MAX maximum value 0240 */ 0241 enum { 0242 DPU_WB_LINE_MODE = 0x1, 0243 DPU_WB_BLOCK_MODE, 0244 DPU_WB_UBWC, 0245 DPU_WB_YUV_CONFIG, 0246 DPU_WB_PIPE_ALPHA, 0247 DPU_WB_XY_ROI_OFFSET, 0248 DPU_WB_QOS, 0249 DPU_WB_QOS_8LVL, 0250 DPU_WB_CDP, 0251 DPU_WB_INPUT_CTRL, 0252 DPU_WB_CROP, 0253 DPU_WB_MAX 0254 }; 0255 0256 /** 0257 * VBIF sub-blocks and features 0258 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 0259 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 0260 * @DPU_VBIF_MAX maximum value 0261 */ 0262 enum { 0263 DPU_VBIF_QOS_OTLIM = 0x1, 0264 DPU_VBIF_QOS_REMAP, 0265 DPU_VBIF_MAX 0266 }; 0267 0268 /** 0269 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 0270 * @name: string name for debug purposes 0271 * @id: enum identifying this block 0272 * @base: register base offset to mdss 0273 * @len: length of hardware block 0274 * @features bit mask identifying sub-blocks/features 0275 */ 0276 #define DPU_HW_BLK_INFO \ 0277 char name[DPU_HW_BLK_NAME_LEN]; \ 0278 u32 id; \ 0279 u32 base; \ 0280 u32 len; \ 0281 unsigned long features 0282 0283 /** 0284 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 0285 * @name: string name for debug purposes 0286 * @id: enum identifying this sub-block 0287 * @base: offset of this sub-block relative to the block 0288 * offset 0289 * @len register block length of this sub-block 0290 */ 0291 #define DPU_HW_SUBBLK_INFO \ 0292 char name[DPU_HW_BLK_NAME_LEN]; \ 0293 u32 id; \ 0294 u32 base; \ 0295 u32 len 0296 0297 /** 0298 * struct dpu_src_blk: SSPP part of the source pipes 0299 * @info: HW register and features supported by this sub-blk 0300 */ 0301 struct dpu_src_blk { 0302 DPU_HW_SUBBLK_INFO; 0303 }; 0304 0305 /** 0306 * struct dpu_scaler_blk: Scaler information 0307 * @info: HW register and features supported by this sub-blk 0308 * @version: qseed block revision 0309 */ 0310 struct dpu_scaler_blk { 0311 DPU_HW_SUBBLK_INFO; 0312 u32 version; 0313 }; 0314 0315 struct dpu_csc_blk { 0316 DPU_HW_SUBBLK_INFO; 0317 }; 0318 0319 /** 0320 * struct dpu_pp_blk : Pixel processing sub-blk information 0321 * @info: HW register and features supported by this sub-blk 0322 * @version: HW Algorithm version 0323 */ 0324 struct dpu_pp_blk { 0325 DPU_HW_SUBBLK_INFO; 0326 u32 version; 0327 }; 0328 0329 /** 0330 * enum dpu_qos_lut_usage - define QoS LUT use cases 0331 */ 0332 enum dpu_qos_lut_usage { 0333 DPU_QOS_LUT_USAGE_LINEAR, 0334 DPU_QOS_LUT_USAGE_MACROTILE, 0335 DPU_QOS_LUT_USAGE_NRT, 0336 DPU_QOS_LUT_USAGE_MAX, 0337 }; 0338 0339 /** 0340 * struct dpu_qos_lut_entry - define QoS LUT table entry 0341 * @fl: fill level, or zero on last entry to indicate default lut 0342 * @lut: lut to use if equal to or less than fill level 0343 */ 0344 struct dpu_qos_lut_entry { 0345 u32 fl; 0346 u64 lut; 0347 }; 0348 0349 /** 0350 * struct dpu_qos_lut_tbl - define QoS LUT table 0351 * @nentry: number of entry in this table 0352 * @entries: Pointer to table entries 0353 */ 0354 struct dpu_qos_lut_tbl { 0355 u32 nentry; 0356 const struct dpu_qos_lut_entry *entries; 0357 }; 0358 0359 /** 0360 * struct dpu_rotation_cfg - define inline rotation config 0361 * @rot_maxheight: max pre rotated height allowed for rotation 0362 * @rot_num_formats: number of elements in @rot_format_list 0363 * @rot_format_list: list of supported rotator formats 0364 */ 0365 struct dpu_rotation_cfg { 0366 u32 rot_maxheight; 0367 size_t rot_num_formats; 0368 const u32 *rot_format_list; 0369 }; 0370 0371 /** 0372 * struct dpu_caps - define DPU capabilities 0373 * @max_mixer_width max layer mixer line width support. 0374 * @max_mixer_blendstages max layer mixer blend stages or 0375 * supported z order 0376 * @qseed_type qseed2 or qseed3 support. 0377 * @smart_dma_rev Supported version of SmartDMA feature. 0378 * @ubwc_version UBWC feature version (0x0 for not supported) 0379 * @has_src_split source split feature status 0380 * @has_dim_layer dim layer feature status 0381 * @has_idle_pc indicate if idle power collapse feature is supported 0382 * @has_3d_merge indicate if 3D merge is supported 0383 * @max_linewidth max linewidth for sspp 0384 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 0385 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 0386 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 0387 */ 0388 struct dpu_caps { 0389 u32 max_mixer_width; 0390 u32 max_mixer_blendstages; 0391 u32 qseed_type; 0392 u32 smart_dma_rev; 0393 u32 ubwc_version; 0394 bool has_src_split; 0395 bool has_dim_layer; 0396 bool has_idle_pc; 0397 bool has_3d_merge; 0398 /* SSPP limits */ 0399 u32 max_linewidth; 0400 u32 pixel_ram_size; 0401 u32 max_hdeci_exp; 0402 u32 max_vdeci_exp; 0403 }; 0404 0405 /** 0406 * struct dpu_sspp_sub_blks : SSPP sub-blocks 0407 * common: Pointer to common configurations shared by sub blocks 0408 * @creq_vblank: creq priority during vertical blanking 0409 * @danger_vblank: danger priority during vertical blanking 0410 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 0411 * @maxupscale: maxupscale ratio supported 0412 * @smart_dma_priority: hw priority of rect1 of multirect pipe 0413 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 0414 * @qseed_ver: qseed version 0415 * @src_blk: 0416 * @scaler_blk: 0417 * @csc_blk: 0418 * @hsic: 0419 * @memcolor: 0420 * @pcc_blk: 0421 * @igc_blk: 0422 * @format_list: Pointer to list of supported formats 0423 * @num_formats: Number of supported formats 0424 * @virt_format_list: Pointer to list of supported formats for virtual planes 0425 * @virt_num_formats: Number of supported formats for virtual planes 0426 * @dpu_rotation_cfg: inline rotation configuration 0427 */ 0428 struct dpu_sspp_sub_blks { 0429 u32 creq_vblank; 0430 u32 danger_vblank; 0431 u32 maxdwnscale; 0432 u32 maxupscale; 0433 u32 smart_dma_priority; 0434 u32 max_per_pipe_bw; 0435 u32 qseed_ver; 0436 struct dpu_src_blk src_blk; 0437 struct dpu_scaler_blk scaler_blk; 0438 struct dpu_pp_blk csc_blk; 0439 struct dpu_pp_blk hsic_blk; 0440 struct dpu_pp_blk memcolor_blk; 0441 struct dpu_pp_blk pcc_blk; 0442 struct dpu_pp_blk igc_blk; 0443 0444 const u32 *format_list; 0445 u32 num_formats; 0446 const u32 *virt_format_list; 0447 u32 virt_num_formats; 0448 const struct dpu_rotation_cfg *rotation_cfg; 0449 }; 0450 0451 /** 0452 * struct dpu_lm_sub_blks: information of mixer block 0453 * @maxwidth: Max pixel width supported by this mixer 0454 * @maxblendstages: Max number of blend-stages supported 0455 * @blendstage_base: Blend-stage register base offset 0456 * @gc: gamma correction block 0457 */ 0458 struct dpu_lm_sub_blks { 0459 u32 maxwidth; 0460 u32 maxblendstages; 0461 u32 blendstage_base[MAX_BLOCKS]; 0462 struct dpu_pp_blk gc; 0463 }; 0464 0465 /** 0466 * struct dpu_dspp_sub_blks: Information of DSPP block 0467 * @gc : gamma correction block 0468 * @pcc: pixel color correction block 0469 */ 0470 struct dpu_dspp_sub_blks { 0471 struct dpu_pp_blk gc; 0472 struct dpu_pp_blk pcc; 0473 }; 0474 0475 struct dpu_pingpong_sub_blks { 0476 struct dpu_pp_blk te; 0477 struct dpu_pp_blk te2; 0478 struct dpu_pp_blk dither; 0479 }; 0480 0481 /** 0482 * dpu_clk_ctrl_type - Defines top level clock control signals 0483 */ 0484 enum dpu_clk_ctrl_type { 0485 DPU_CLK_CTRL_NONE, 0486 DPU_CLK_CTRL_VIG0, 0487 DPU_CLK_CTRL_VIG1, 0488 DPU_CLK_CTRL_VIG2, 0489 DPU_CLK_CTRL_VIG3, 0490 DPU_CLK_CTRL_VIG4, 0491 DPU_CLK_CTRL_RGB0, 0492 DPU_CLK_CTRL_RGB1, 0493 DPU_CLK_CTRL_RGB2, 0494 DPU_CLK_CTRL_RGB3, 0495 DPU_CLK_CTRL_DMA0, 0496 DPU_CLK_CTRL_DMA1, 0497 DPU_CLK_CTRL_DMA2, 0498 DPU_CLK_CTRL_DMA3, 0499 DPU_CLK_CTRL_CURSOR0, 0500 DPU_CLK_CTRL_CURSOR1, 0501 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 0502 DPU_CLK_CTRL_REG_DMA, 0503 DPU_CLK_CTRL_WB2, 0504 DPU_CLK_CTRL_MAX, 0505 }; 0506 0507 /* struct dpu_clk_ctrl_reg : Clock control register 0508 * @reg_off: register offset 0509 * @bit_off: bit offset 0510 */ 0511 struct dpu_clk_ctrl_reg { 0512 u32 reg_off; 0513 u32 bit_off; 0514 }; 0515 0516 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 0517 * @id: index identifying this block 0518 * @base: register base offset to mdss 0519 * @features bit mask identifying sub-blocks/features 0520 * @highest_bank_bit: UBWC parameter 0521 * @ubwc_static: ubwc static configuration 0522 * @ubwc_swizzle: ubwc default swizzle setting 0523 * @clk_ctrls clock control register definition 0524 */ 0525 struct dpu_mdp_cfg { 0526 DPU_HW_BLK_INFO; 0527 u32 highest_bank_bit; 0528 u32 ubwc_swizzle; 0529 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 0530 }; 0531 0532 /* struct dpu_ctl_cfg : MDP CTL instance info 0533 * @id: index identifying this block 0534 * @base: register base offset to mdss 0535 * @features bit mask identifying sub-blocks/features 0536 * @intr_start: interrupt index for CTL_START 0537 */ 0538 struct dpu_ctl_cfg { 0539 DPU_HW_BLK_INFO; 0540 s32 intr_start; 0541 }; 0542 0543 /** 0544 * struct dpu_sspp_cfg - information of source pipes 0545 * @id: index identifying this block 0546 * @base register offset of this block 0547 * @features bit mask identifying sub-blocks/features 0548 * @sblk: SSPP sub-blocks information 0549 * @xin_id: bus client identifier 0550 * @clk_ctrl clock control identifier 0551 * @type sspp type identifier 0552 */ 0553 struct dpu_sspp_cfg { 0554 DPU_HW_BLK_INFO; 0555 const struct dpu_sspp_sub_blks *sblk; 0556 u32 xin_id; 0557 enum dpu_clk_ctrl_type clk_ctrl; 0558 u32 type; 0559 }; 0560 0561 /** 0562 * struct dpu_lm_cfg - information of layer mixer blocks 0563 * @id: index identifying this block 0564 * @base register offset of this block 0565 * @features bit mask identifying sub-blocks/features 0566 * @sblk: LM Sub-blocks information 0567 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 0568 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 0569 */ 0570 struct dpu_lm_cfg { 0571 DPU_HW_BLK_INFO; 0572 const struct dpu_lm_sub_blks *sblk; 0573 u32 pingpong; 0574 u32 dspp; 0575 unsigned long lm_pair_mask; 0576 }; 0577 0578 /** 0579 * struct dpu_dspp_cfg - information of DSPP blocks 0580 * @id enum identifying this block 0581 * @base register offset of this block 0582 * @features bit mask identifying sub-blocks/features 0583 * supported by this block 0584 * @sblk sub-blocks information 0585 */ 0586 struct dpu_dspp_cfg { 0587 DPU_HW_BLK_INFO; 0588 const struct dpu_dspp_sub_blks *sblk; 0589 }; 0590 0591 /** 0592 * struct dpu_pingpong_cfg - information of PING-PONG blocks 0593 * @id enum identifying this block 0594 * @base register offset of this block 0595 * @features bit mask identifying sub-blocks/features 0596 * @intr_done: index for PINGPONG done interrupt 0597 * @intr_rdptr: index for PINGPONG readpointer done interrupt 0598 * @sblk sub-blocks information 0599 */ 0600 struct dpu_pingpong_cfg { 0601 DPU_HW_BLK_INFO; 0602 u32 merge_3d; 0603 s32 intr_done; 0604 s32 intr_rdptr; 0605 const struct dpu_pingpong_sub_blks *sblk; 0606 }; 0607 0608 /** 0609 * struct dpu_merge_3d_cfg - information of DSPP blocks 0610 * @id enum identifying this block 0611 * @base register offset of this block 0612 * @features bit mask identifying sub-blocks/features 0613 * supported by this block 0614 * @sblk sub-blocks information 0615 */ 0616 struct dpu_merge_3d_cfg { 0617 DPU_HW_BLK_INFO; 0618 const struct dpu_merge_3d_sub_blks *sblk; 0619 }; 0620 0621 /** 0622 * struct dpu_dsc_cfg - information of DSC blocks 0623 * @id enum identifying this block 0624 * @base register offset of this block 0625 * @features bit mask identifying sub-blocks/features 0626 */ 0627 struct dpu_dsc_cfg { 0628 DPU_HW_BLK_INFO; 0629 }; 0630 0631 /** 0632 * struct dpu_intf_cfg - information of timing engine blocks 0633 * @id enum identifying this block 0634 * @base register offset of this block 0635 * @features bit mask identifying sub-blocks/features 0636 * @type: Interface type(DSI, DP, HDMI) 0637 * @controller_id: Controller Instance ID in case of multiple of intf type 0638 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 0639 * @intr_underrun: index for INTF underrun interrupt 0640 * @intr_vsync: index for INTF VSYNC interrupt 0641 */ 0642 struct dpu_intf_cfg { 0643 DPU_HW_BLK_INFO; 0644 u32 type; /* interface type*/ 0645 u32 controller_id; 0646 u32 prog_fetch_lines_worst_case; 0647 s32 intr_underrun; 0648 s32 intr_vsync; 0649 }; 0650 0651 /** 0652 * struct dpu_wb_cfg - information of writeback blocks 0653 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 0654 * @vbif_idx: vbif client index 0655 * @maxlinewidth: max line width supported by writeback block 0656 * @xin_id: bus client identifier 0657 * @intr_wb_done: interrupt index for WB_DONE 0658 * @format_list: list of formats supported by this writeback block 0659 * @num_formats: number of formats supported by this writeback block 0660 * @clk_ctrl: clock control identifier 0661 */ 0662 struct dpu_wb_cfg { 0663 DPU_HW_BLK_INFO; 0664 u8 vbif_idx; 0665 u32 maxlinewidth; 0666 u32 xin_id; 0667 s32 intr_wb_done; 0668 const u32 *format_list; 0669 u32 num_formats; 0670 enum dpu_clk_ctrl_type clk_ctrl; 0671 }; 0672 0673 /** 0674 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 0675 * @pps pixel per seconds 0676 * @ot_limit OT limit to use up to specified pixel per second 0677 */ 0678 struct dpu_vbif_dynamic_ot_cfg { 0679 u64 pps; 0680 u32 ot_limit; 0681 }; 0682 0683 /** 0684 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 0685 * @count length of cfg 0686 * @cfg pointer to array of configuration settings with 0687 * ascending requirements 0688 */ 0689 struct dpu_vbif_dynamic_ot_tbl { 0690 u32 count; 0691 const struct dpu_vbif_dynamic_ot_cfg *cfg; 0692 }; 0693 0694 /** 0695 * struct dpu_vbif_qos_tbl - QoS priority table 0696 * @npriority_lvl num of priority level 0697 * @priority_lvl pointer to array of priority level in ascending order 0698 */ 0699 struct dpu_vbif_qos_tbl { 0700 u32 npriority_lvl; 0701 const u32 *priority_lvl; 0702 }; 0703 0704 /** 0705 * struct dpu_vbif_cfg - information of VBIF blocks 0706 * @id enum identifying this block 0707 * @base register offset of this block 0708 * @features bit mask identifying sub-blocks/features 0709 * @ot_rd_limit default OT read limit 0710 * @ot_wr_limit default OT write limit 0711 * @xin_halt_timeout maximum time (in usec) for xin to halt 0712 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 0713 * @dynamic_ot_rd_tbl dynamic OT read configuration table 0714 * @dynamic_ot_wr_tbl dynamic OT write configuration table 0715 * @qos_rt_tbl real-time QoS priority table 0716 * @qos_nrt_tbl non-real-time QoS priority table 0717 * @memtype_count number of defined memtypes 0718 * @memtype array of xin memtype definitions 0719 */ 0720 struct dpu_vbif_cfg { 0721 DPU_HW_BLK_INFO; 0722 u32 default_ot_rd_limit; 0723 u32 default_ot_wr_limit; 0724 u32 xin_halt_timeout; 0725 u32 qos_rp_remap_size; 0726 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 0727 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 0728 struct dpu_vbif_qos_tbl qos_rt_tbl; 0729 struct dpu_vbif_qos_tbl qos_nrt_tbl; 0730 u32 memtype_count; 0731 u32 memtype[MAX_XIN_COUNT]; 0732 }; 0733 /** 0734 * struct dpu_reg_dma_cfg - information of lut dma blocks 0735 * @id enum identifying this block 0736 * @base register offset of this block 0737 * @features bit mask identifying sub-blocks/features 0738 * @version version of lutdma hw block 0739 * @trigger_sel_off offset to trigger select registers of lutdma 0740 */ 0741 struct dpu_reg_dma_cfg { 0742 DPU_HW_BLK_INFO; 0743 u32 version; 0744 u32 trigger_sel_off; 0745 u32 xin_id; 0746 enum dpu_clk_ctrl_type clk_ctrl; 0747 }; 0748 0749 /** 0750 * Define CDP use cases 0751 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 0752 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 0753 */ 0754 enum { 0755 DPU_PERF_CDP_USAGE_RT, 0756 DPU_PERF_CDP_USAGE_NRT, 0757 DPU_PERF_CDP_USAGE_MAX 0758 }; 0759 0760 /** 0761 * struct dpu_perf_cdp_cfg - define CDP use case configuration 0762 * @rd_enable: true if read pipe CDP is enabled 0763 * @wr_enable: true if write pipe CDP is enabled 0764 */ 0765 struct dpu_perf_cdp_cfg { 0766 bool rd_enable; 0767 bool wr_enable; 0768 }; 0769 0770 /** 0771 * struct dpu_perf_cfg - performance control settings 0772 * @max_bw_low low threshold of maximum bandwidth (kbps) 0773 * @max_bw_high high threshold of maximum bandwidth (kbps) 0774 * @min_core_ib minimum bandwidth for core (kbps) 0775 * @min_core_ib minimum mnoc ib vote in kbps 0776 * @min_llcc_ib minimum llcc ib vote in kbps 0777 * @min_dram_ib minimum dram ib vote in kbps 0778 * @undersized_prefill_lines undersized prefill in lines 0779 * @xtra_prefill_lines extra prefill latency in lines 0780 * @dest_scale_prefill_lines destination scaler latency in lines 0781 * @macrotile_perfill_lines macrotile latency in lines 0782 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 0783 * @linear_prefill_lines linear latency in lines 0784 * @downscaling_prefill_lines downscaling latency in lines 0785 * @amortizable_theshold minimum y position for traffic shaping prefill 0786 * @min_prefill_lines minimum pipeline latency in lines 0787 * @clk_inefficiency_factor DPU src clock inefficiency factor 0788 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 0789 * @safe_lut_tbl: LUT tables for safe signals 0790 * @danger_lut_tbl: LUT tables for danger signals 0791 * @qos_lut_tbl: LUT tables for QoS signals 0792 * @cdp_cfg cdp use case configurations 0793 */ 0794 struct dpu_perf_cfg { 0795 u32 max_bw_low; 0796 u32 max_bw_high; 0797 u32 min_core_ib; 0798 u32 min_llcc_ib; 0799 u32 min_dram_ib; 0800 u32 undersized_prefill_lines; 0801 u32 xtra_prefill_lines; 0802 u32 dest_scale_prefill_lines; 0803 u32 macrotile_prefill_lines; 0804 u32 yuv_nv12_prefill_lines; 0805 u32 linear_prefill_lines; 0806 u32 downscaling_prefill_lines; 0807 u32 amortizable_threshold; 0808 u32 min_prefill_lines; 0809 u32 clk_inefficiency_factor; 0810 u32 bw_inefficiency_factor; 0811 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 0812 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 0813 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 0814 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 0815 }; 0816 0817 /** 0818 * struct dpu_mdss_cfg - information of MDSS HW 0819 * This is the main catalog data structure representing 0820 * this HW version. Contains number of instances, 0821 * register offsets, capabilities of the all MDSS HW sub-blocks. 0822 * 0823 * @dma_formats Supported formats for dma pipe 0824 * @cursor_formats Supported formats for cursor pipe 0825 * @vig_formats Supported formats for vig pipe 0826 * @mdss_irqs: Bitmap with the irqs supported by the target 0827 */ 0828 struct dpu_mdss_cfg { 0829 const struct dpu_caps *caps; 0830 0831 u32 mdp_count; 0832 const struct dpu_mdp_cfg *mdp; 0833 0834 u32 ctl_count; 0835 const struct dpu_ctl_cfg *ctl; 0836 0837 u32 sspp_count; 0838 const struct dpu_sspp_cfg *sspp; 0839 0840 u32 mixer_count; 0841 const struct dpu_lm_cfg *mixer; 0842 0843 u32 pingpong_count; 0844 const struct dpu_pingpong_cfg *pingpong; 0845 0846 u32 merge_3d_count; 0847 const struct dpu_merge_3d_cfg *merge_3d; 0848 0849 u32 dsc_count; 0850 struct dpu_dsc_cfg *dsc; 0851 0852 u32 intf_count; 0853 const struct dpu_intf_cfg *intf; 0854 0855 u32 vbif_count; 0856 const struct dpu_vbif_cfg *vbif; 0857 0858 u32 wb_count; 0859 const struct dpu_wb_cfg *wb; 0860 0861 u32 reg_dma_count; 0862 const struct dpu_reg_dma_cfg *dma_cfg; 0863 0864 u32 ad_count; 0865 0866 u32 dspp_count; 0867 const struct dpu_dspp_cfg *dspp; 0868 0869 /* Add additional block data structures here */ 0870 0871 const struct dpu_perf_cfg *perf; 0872 const struct dpu_format_extended *dma_formats; 0873 const struct dpu_format_extended *cursor_formats; 0874 const struct dpu_format_extended *vig_formats; 0875 0876 unsigned long mdss_irqs; 0877 }; 0878 0879 struct dpu_mdss_hw_cfg_handler { 0880 u32 hw_rev; 0881 const struct dpu_mdss_cfg *dpu_cfg; 0882 }; 0883 0884 /** 0885 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 0886 * hardcoded target specific catalog information in config structure 0887 * @hw_rev: caller needs provide the hardware revision. 0888 * 0889 * Return: dpu config structure 0890 */ 0891 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 0892 0893 #endif /* _DPU_HW_CATALOG_H */
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