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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0003  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
0004  */
0005 
0006 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
0007 #include <linux/slab.h>
0008 #include <linux/of_address.h>
0009 #include <linux/platform_device.h>
0010 #include "dpu_hw_mdss.h"
0011 #include "dpu_hw_interrupts.h"
0012 #include "dpu_hw_catalog.h"
0013 #include "dpu_kms.h"
0014 
0015 #define VIG_MASK \
0016     (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
0017     BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
0018     BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
0019 
0020 #define VIG_MSM8998_MASK \
0021     (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
0022 
0023 #define VIG_SDM845_MASK \
0024     (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
0025 
0026 #define VIG_SC7180_MASK \
0027     (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
0028 
0029 #define VIG_SM8250_MASK \
0030     (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
0031 
0032 #define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
0033 
0034 #define DMA_MSM8998_MASK \
0035     (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
0036     BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
0037     BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
0038 
0039 #define VIG_SC7280_MASK \
0040     (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
0041 
0042 #define DMA_SDM845_MASK \
0043     (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
0044     BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
0045     BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
0046 
0047 #define DMA_CURSOR_SDM845_MASK \
0048     (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
0049 
0050 #define DMA_CURSOR_MSM8998_MASK \
0051     (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
0052 
0053 #define MIXER_MSM8998_MASK \
0054     (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
0055 
0056 #define MIXER_SDM845_MASK \
0057     (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
0058 
0059 #define MIXER_SC7180_MASK \
0060     (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
0061 
0062 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
0063 
0064 #define PINGPONG_SDM845_SPLIT_MASK \
0065     (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
0066 
0067 #define CTL_SC7280_MASK \
0068     (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG))
0069 
0070 #define MERGE_3D_SM8150_MASK (0)
0071 
0072 #define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC)
0073 
0074 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
0075 
0076 #define INTF_SDM845_MASK (0)
0077 
0078 #define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
0079 
0080 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
0081 
0082 #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
0083              BIT(MDP_SSPP_TOP0_INTR2) | \
0084              BIT(MDP_SSPP_TOP0_HIST_INTR) | \
0085              BIT(MDP_INTF0_INTR) | \
0086              BIT(MDP_INTF1_INTR) | \
0087              BIT(MDP_INTF2_INTR) | \
0088              BIT(MDP_INTF3_INTR) | \
0089              BIT(MDP_INTF4_INTR) | \
0090              BIT(MDP_AD4_0_INTR) | \
0091              BIT(MDP_AD4_1_INTR))
0092 
0093 #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
0094              BIT(MDP_SSPP_TOP0_INTR2) | \
0095              BIT(MDP_SSPP_TOP0_HIST_INTR) | \
0096              BIT(MDP_INTF0_INTR) | \
0097              BIT(MDP_INTF1_INTR))
0098 
0099 #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
0100              BIT(MDP_SSPP_TOP0_INTR2) | \
0101              BIT(MDP_SSPP_TOP0_HIST_INTR) | \
0102              BIT(MDP_INTF0_7xxx_INTR) | \
0103              BIT(MDP_INTF1_7xxx_INTR) | \
0104              BIT(MDP_INTF5_7xxx_INTR))
0105 
0106 #define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
0107              BIT(MDP_SSPP_TOP0_INTR2) | \
0108              BIT(MDP_SSPP_TOP0_HIST_INTR) | \
0109              BIT(MDP_INTF0_INTR) | \
0110              BIT(MDP_INTF1_INTR) | \
0111              BIT(MDP_INTF2_INTR) | \
0112              BIT(MDP_INTF3_INTR) | \
0113              BIT(MDP_INTF4_INTR))
0114 
0115 #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
0116               BIT(MDP_SSPP_TOP0_INTR2) | \
0117               BIT(MDP_SSPP_TOP0_HIST_INTR) | \
0118               BIT(MDP_INTF0_INTR) | \
0119               BIT(MDP_INTF1_INTR) | \
0120               BIT(MDP_INTF2_INTR) | \
0121               BIT(MDP_INTF3_INTR) | \
0122               BIT(MDP_INTF4_INTR) | \
0123               BIT(MDP_INTF5_INTR) | \
0124               BIT(MDP_AD4_0_INTR) | \
0125               BIT(MDP_AD4_1_INTR))
0126 
0127 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
0128              BIT(DPU_WB_UBWC) | \
0129              BIT(DPU_WB_YUV_CONFIG) | \
0130              BIT(DPU_WB_PIPE_ALPHA) | \
0131              BIT(DPU_WB_XY_ROI_OFFSET) | \
0132              BIT(DPU_WB_QOS) | \
0133              BIT(DPU_WB_QOS_8LVL) | \
0134              BIT(DPU_WB_CDP) | \
0135              BIT(DPU_WB_INPUT_CTRL))
0136 
0137 #define DEFAULT_PIXEL_RAM_SIZE      (50 * 1024)
0138 #define DEFAULT_DPU_LINE_WIDTH      2048
0139 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH   2560
0140 
0141 #define MAX_HORZ_DECIMATION 4
0142 #define MAX_VERT_DECIMATION 4
0143 
0144 #define MAX_UPSCALE_RATIO   20
0145 #define MAX_DOWNSCALE_RATIO 4
0146 #define SSPP_UNITY_SCALE    1
0147 
0148 #define STRCAT(X, Y) (X Y)
0149 
0150 static const uint32_t plane_formats[] = {
0151     DRM_FORMAT_ARGB8888,
0152     DRM_FORMAT_ABGR8888,
0153     DRM_FORMAT_RGBA8888,
0154     DRM_FORMAT_BGRA8888,
0155     DRM_FORMAT_XRGB8888,
0156     DRM_FORMAT_RGBX8888,
0157     DRM_FORMAT_BGRX8888,
0158     DRM_FORMAT_XBGR8888,
0159     DRM_FORMAT_RGB888,
0160     DRM_FORMAT_BGR888,
0161     DRM_FORMAT_RGB565,
0162     DRM_FORMAT_BGR565,
0163     DRM_FORMAT_ARGB1555,
0164     DRM_FORMAT_ABGR1555,
0165     DRM_FORMAT_RGBA5551,
0166     DRM_FORMAT_BGRA5551,
0167     DRM_FORMAT_XRGB1555,
0168     DRM_FORMAT_XBGR1555,
0169     DRM_FORMAT_RGBX5551,
0170     DRM_FORMAT_BGRX5551,
0171     DRM_FORMAT_ARGB4444,
0172     DRM_FORMAT_ABGR4444,
0173     DRM_FORMAT_RGBA4444,
0174     DRM_FORMAT_BGRA4444,
0175     DRM_FORMAT_XRGB4444,
0176     DRM_FORMAT_XBGR4444,
0177     DRM_FORMAT_RGBX4444,
0178     DRM_FORMAT_BGRX4444,
0179 };
0180 
0181 static const uint32_t plane_formats_yuv[] = {
0182     DRM_FORMAT_ARGB8888,
0183     DRM_FORMAT_ABGR8888,
0184     DRM_FORMAT_RGBA8888,
0185     DRM_FORMAT_BGRX8888,
0186     DRM_FORMAT_BGRA8888,
0187     DRM_FORMAT_XRGB8888,
0188     DRM_FORMAT_XBGR8888,
0189     DRM_FORMAT_RGBX8888,
0190     DRM_FORMAT_RGB888,
0191     DRM_FORMAT_BGR888,
0192     DRM_FORMAT_RGB565,
0193     DRM_FORMAT_BGR565,
0194     DRM_FORMAT_ARGB1555,
0195     DRM_FORMAT_ABGR1555,
0196     DRM_FORMAT_RGBA5551,
0197     DRM_FORMAT_BGRA5551,
0198     DRM_FORMAT_XRGB1555,
0199     DRM_FORMAT_XBGR1555,
0200     DRM_FORMAT_RGBX5551,
0201     DRM_FORMAT_BGRX5551,
0202     DRM_FORMAT_ARGB4444,
0203     DRM_FORMAT_ABGR4444,
0204     DRM_FORMAT_RGBA4444,
0205     DRM_FORMAT_BGRA4444,
0206     DRM_FORMAT_XRGB4444,
0207     DRM_FORMAT_XBGR4444,
0208     DRM_FORMAT_RGBX4444,
0209     DRM_FORMAT_BGRX4444,
0210 
0211     DRM_FORMAT_NV12,
0212     DRM_FORMAT_NV21,
0213     DRM_FORMAT_NV16,
0214     DRM_FORMAT_NV61,
0215     DRM_FORMAT_VYUY,
0216     DRM_FORMAT_UYVY,
0217     DRM_FORMAT_YUYV,
0218     DRM_FORMAT_YVYU,
0219     DRM_FORMAT_YUV420,
0220     DRM_FORMAT_YVU420,
0221 };
0222 
0223 static const u32 rotation_v2_formats[] = {
0224     DRM_FORMAT_NV12,
0225     /* TODO add formats after validation */
0226 };
0227 
0228 static const uint32_t wb2_formats[] = {
0229     DRM_FORMAT_RGB565,
0230     DRM_FORMAT_BGR565,
0231     DRM_FORMAT_RGB888,
0232     DRM_FORMAT_ARGB8888,
0233     DRM_FORMAT_RGBA8888,
0234     DRM_FORMAT_ABGR8888,
0235     DRM_FORMAT_XRGB8888,
0236     DRM_FORMAT_RGBX8888,
0237     DRM_FORMAT_XBGR8888,
0238     DRM_FORMAT_ARGB1555,
0239     DRM_FORMAT_RGBA5551,
0240     DRM_FORMAT_XRGB1555,
0241     DRM_FORMAT_RGBX5551,
0242     DRM_FORMAT_ARGB4444,
0243     DRM_FORMAT_RGBA4444,
0244     DRM_FORMAT_RGBX4444,
0245     DRM_FORMAT_XRGB4444,
0246     DRM_FORMAT_BGR565,
0247     DRM_FORMAT_BGR888,
0248     DRM_FORMAT_ABGR8888,
0249     DRM_FORMAT_BGRA8888,
0250     DRM_FORMAT_BGRX8888,
0251     DRM_FORMAT_XBGR8888,
0252     DRM_FORMAT_ABGR1555,
0253     DRM_FORMAT_BGRA5551,
0254     DRM_FORMAT_XBGR1555,
0255     DRM_FORMAT_BGRX5551,
0256     DRM_FORMAT_ABGR4444,
0257     DRM_FORMAT_BGRA4444,
0258     DRM_FORMAT_BGRX4444,
0259     DRM_FORMAT_XBGR4444,
0260 };
0261 
0262 /*************************************************************
0263  * DPU sub blocks config
0264  *************************************************************/
0265 /* DPU top level caps */
0266 static const struct dpu_caps msm8998_dpu_caps = {
0267     .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0268     .max_mixer_blendstages = 0x7,
0269     .qseed_type = DPU_SSPP_SCALER_QSEED3,
0270     .smart_dma_rev = DPU_SSPP_SMART_DMA_V1,
0271     .ubwc_version = DPU_HW_UBWC_VER_10,
0272     .has_src_split = true,
0273     .has_dim_layer = true,
0274     .has_idle_pc = true,
0275     .has_3d_merge = true,
0276     .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0277     .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
0278     .max_hdeci_exp = MAX_HORZ_DECIMATION,
0279     .max_vdeci_exp = MAX_VERT_DECIMATION,
0280 };
0281 
0282 static const struct dpu_caps qcm2290_dpu_caps = {
0283     .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0284     .max_mixer_blendstages = 0x4,
0285     .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
0286     .ubwc_version = DPU_HW_UBWC_VER_20,
0287     .has_dim_layer = true,
0288     .has_idle_pc = true,
0289     .max_linewidth = 2160,
0290     .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
0291 };
0292 
0293 static const struct dpu_caps sdm845_dpu_caps = {
0294     .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0295     .max_mixer_blendstages = 0xb,
0296     .qseed_type = DPU_SSPP_SCALER_QSEED3,
0297     .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
0298     .ubwc_version = DPU_HW_UBWC_VER_20,
0299     .has_src_split = true,
0300     .has_dim_layer = true,
0301     .has_idle_pc = true,
0302     .has_3d_merge = true,
0303     .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0304     .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
0305     .max_hdeci_exp = MAX_HORZ_DECIMATION,
0306     .max_vdeci_exp = MAX_VERT_DECIMATION,
0307 };
0308 
0309 static const struct dpu_caps sc7180_dpu_caps = {
0310     .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0311     .max_mixer_blendstages = 0x9,
0312     .qseed_type = DPU_SSPP_SCALER_QSEED4,
0313     .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
0314     .ubwc_version = DPU_HW_UBWC_VER_20,
0315     .has_dim_layer = true,
0316     .has_idle_pc = true,
0317     .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0318     .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
0319 };
0320 
0321 static const struct dpu_caps sm8150_dpu_caps = {
0322     .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0323     .max_mixer_blendstages = 0xb,
0324     .qseed_type = DPU_SSPP_SCALER_QSEED3,
0325     .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
0326     .ubwc_version = DPU_HW_UBWC_VER_30,
0327     .has_src_split = true,
0328     .has_dim_layer = true,
0329     .has_idle_pc = true,
0330     .has_3d_merge = true,
0331     .max_linewidth = 4096,
0332     .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
0333     .max_hdeci_exp = MAX_HORZ_DECIMATION,
0334     .max_vdeci_exp = MAX_VERT_DECIMATION,
0335 };
0336 
0337 static const struct dpu_caps sc8180x_dpu_caps = {
0338     .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0339     .max_mixer_blendstages = 0xb,
0340     .qseed_type = DPU_SSPP_SCALER_QSEED3,
0341     .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
0342     .ubwc_version = DPU_HW_UBWC_VER_30,
0343     .has_src_split = true,
0344     .has_dim_layer = true,
0345     .has_idle_pc = true,
0346     .has_3d_merge = true,
0347     .max_linewidth = 4096,
0348     .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
0349     .max_hdeci_exp = MAX_HORZ_DECIMATION,
0350     .max_vdeci_exp = MAX_VERT_DECIMATION,
0351 };
0352 
0353 static const struct dpu_caps sm8250_dpu_caps = {
0354     .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0355     .max_mixer_blendstages = 0xb,
0356     .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
0357     .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
0358     .ubwc_version = DPU_HW_UBWC_VER_40,
0359     .has_src_split = true,
0360     .has_dim_layer = true,
0361     .has_idle_pc = true,
0362     .has_3d_merge = true,
0363     .max_linewidth = 4096,
0364     .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
0365 };
0366 
0367 static const struct dpu_caps sc7280_dpu_caps = {
0368     .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0369     .max_mixer_blendstages = 0x7,
0370     .qseed_type = DPU_SSPP_SCALER_QSEED4,
0371     .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
0372     .ubwc_version = DPU_HW_UBWC_VER_30,
0373     .has_dim_layer = true,
0374     .has_idle_pc = true,
0375     .max_linewidth = 2400,
0376     .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
0377 };
0378 
0379 static const struct dpu_mdp_cfg msm8998_mdp[] = {
0380     {
0381     .name = "top_0", .id = MDP_TOP,
0382     .base = 0x0, .len = 0x458,
0383     .features = 0,
0384     .highest_bank_bit = 0x2,
0385     .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
0386             .reg_off = 0x2AC, .bit_off = 0},
0387     .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
0388             .reg_off = 0x2B4, .bit_off = 0},
0389     .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
0390             .reg_off = 0x2BC, .bit_off = 0},
0391     .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
0392             .reg_off = 0x2C4, .bit_off = 0},
0393     .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
0394             .reg_off = 0x2AC, .bit_off = 8},
0395     .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
0396             .reg_off = 0x2B4, .bit_off = 8},
0397     .clk_ctrls[DPU_CLK_CTRL_DMA2] = {
0398             .reg_off = 0x2C4, .bit_off = 8},
0399     .clk_ctrls[DPU_CLK_CTRL_DMA3] = {
0400             .reg_off = 0x2C4, .bit_off = 12},
0401     .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
0402             .reg_off = 0x3A8, .bit_off = 15},
0403     .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
0404             .reg_off = 0x3B0, .bit_off = 15},
0405     },
0406 };
0407 
0408 static const struct dpu_mdp_cfg sdm845_mdp[] = {
0409     {
0410     .name = "top_0", .id = MDP_TOP,
0411     .base = 0x0, .len = 0x45C,
0412     .features = BIT(DPU_MDP_AUDIO_SELECT),
0413     .highest_bank_bit = 0x2,
0414     .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
0415             .reg_off = 0x2AC, .bit_off = 0},
0416     .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
0417             .reg_off = 0x2B4, .bit_off = 0},
0418     .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
0419             .reg_off = 0x2BC, .bit_off = 0},
0420     .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
0421             .reg_off = 0x2C4, .bit_off = 0},
0422     .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
0423             .reg_off = 0x2AC, .bit_off = 8},
0424     .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
0425             .reg_off = 0x2B4, .bit_off = 8},
0426     .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
0427             .reg_off = 0x2BC, .bit_off = 8},
0428     .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
0429             .reg_off = 0x2C4, .bit_off = 8},
0430     },
0431 };
0432 
0433 static const struct dpu_mdp_cfg sc7180_mdp[] = {
0434     {
0435     .name = "top_0", .id = MDP_TOP,
0436     .base = 0x0, .len = 0x494,
0437     .features = 0,
0438     .highest_bank_bit = 0x3,
0439     .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
0440         .reg_off = 0x2AC, .bit_off = 0},
0441     .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
0442         .reg_off = 0x2AC, .bit_off = 8},
0443     .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
0444         .reg_off = 0x2B4, .bit_off = 8},
0445     .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
0446         .reg_off = 0x2C4, .bit_off = 8},
0447     },
0448 };
0449 
0450 static const struct dpu_mdp_cfg sc8180x_mdp[] = {
0451     {
0452     .name = "top_0", .id = MDP_TOP,
0453     .base = 0x0, .len = 0x45C,
0454     .features = 0,
0455     .highest_bank_bit = 0x3,
0456     .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
0457             .reg_off = 0x2AC, .bit_off = 0},
0458     .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
0459             .reg_off = 0x2B4, .bit_off = 0},
0460     .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
0461             .reg_off = 0x2BC, .bit_off = 0},
0462     .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
0463             .reg_off = 0x2C4, .bit_off = 0},
0464     .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
0465             .reg_off = 0x2AC, .bit_off = 8},
0466     .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
0467             .reg_off = 0x2B4, .bit_off = 8},
0468     .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
0469             .reg_off = 0x2BC, .bit_off = 8},
0470     .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
0471             .reg_off = 0x2C4, .bit_off = 8},
0472     },
0473 };
0474 
0475 static const struct dpu_mdp_cfg sm8250_mdp[] = {
0476     {
0477     .name = "top_0", .id = MDP_TOP,
0478     .base = 0x0, .len = 0x494,
0479     .features = 0,
0480     .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
0481     .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
0482             .reg_off = 0x2AC, .bit_off = 0},
0483     .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
0484             .reg_off = 0x2B4, .bit_off = 0},
0485     .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
0486             .reg_off = 0x2BC, .bit_off = 0},
0487     .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
0488             .reg_off = 0x2C4, .bit_off = 0},
0489     .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
0490             .reg_off = 0x2AC, .bit_off = 8},
0491     .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
0492             .reg_off = 0x2B4, .bit_off = 8},
0493     .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
0494             .reg_off = 0x2BC, .bit_off = 8},
0495     .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
0496             .reg_off = 0x2C4, .bit_off = 8},
0497     .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
0498             .reg_off = 0x2BC, .bit_off = 20},
0499     .clk_ctrls[DPU_CLK_CTRL_WB2] = {
0500             .reg_off = 0x3B8, .bit_off = 24},
0501     },
0502 };
0503 
0504 static const struct dpu_mdp_cfg sc7280_mdp[] = {
0505     {
0506     .name = "top_0", .id = MDP_TOP,
0507     .base = 0x0, .len = 0x2014,
0508     .highest_bank_bit = 0x1,
0509     .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
0510         .reg_off = 0x2AC, .bit_off = 0},
0511     .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
0512         .reg_off = 0x2AC, .bit_off = 8},
0513     .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
0514         .reg_off = 0x2B4, .bit_off = 8},
0515     .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
0516         .reg_off = 0x2C4, .bit_off = 8},
0517     },
0518 };
0519 
0520 static const struct dpu_mdp_cfg qcm2290_mdp[] = {
0521     {
0522     .name = "top_0", .id = MDP_TOP,
0523     .base = 0x0, .len = 0x494,
0524     .features = 0,
0525     .highest_bank_bit = 0x2,
0526     .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
0527         .reg_off = 0x2AC, .bit_off = 0},
0528     .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
0529         .reg_off = 0x2AC, .bit_off = 8},
0530     },
0531 };
0532 
0533 /*************************************************************
0534  * CTL sub blocks config
0535  *************************************************************/
0536 static const struct dpu_ctl_cfg msm8998_ctl[] = {
0537     {
0538     .name = "ctl_0", .id = CTL_0,
0539     .base = 0x1000, .len = 0x94,
0540     .features = BIT(DPU_CTL_SPLIT_DISPLAY),
0541     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
0542     },
0543     {
0544     .name = "ctl_1", .id = CTL_1,
0545     .base = 0x1200, .len = 0x94,
0546     .features = 0,
0547     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
0548     },
0549     {
0550     .name = "ctl_2", .id = CTL_2,
0551     .base = 0x1400, .len = 0x94,
0552     .features = BIT(DPU_CTL_SPLIT_DISPLAY),
0553     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
0554     },
0555     {
0556     .name = "ctl_3", .id = CTL_3,
0557     .base = 0x1600, .len = 0x94,
0558     .features = 0,
0559     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
0560     },
0561     {
0562     .name = "ctl_4", .id = CTL_4,
0563     .base = 0x1800, .len = 0x94,
0564     .features = 0,
0565     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
0566     },
0567 };
0568 
0569 static const struct dpu_ctl_cfg sdm845_ctl[] = {
0570     {
0571     .name = "ctl_0", .id = CTL_0,
0572     .base = 0x1000, .len = 0xE4,
0573     .features = BIT(DPU_CTL_SPLIT_DISPLAY),
0574     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
0575     },
0576     {
0577     .name = "ctl_1", .id = CTL_1,
0578     .base = 0x1200, .len = 0xE4,
0579     .features = BIT(DPU_CTL_SPLIT_DISPLAY),
0580     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
0581     },
0582     {
0583     .name = "ctl_2", .id = CTL_2,
0584     .base = 0x1400, .len = 0xE4,
0585     .features = 0,
0586     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
0587     },
0588     {
0589     .name = "ctl_3", .id = CTL_3,
0590     .base = 0x1600, .len = 0xE4,
0591     .features = 0,
0592     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
0593     },
0594     {
0595     .name = "ctl_4", .id = CTL_4,
0596     .base = 0x1800, .len = 0xE4,
0597     .features = 0,
0598     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
0599     },
0600 };
0601 
0602 static const struct dpu_ctl_cfg sc7180_ctl[] = {
0603     {
0604     .name = "ctl_0", .id = CTL_0,
0605     .base = 0x1000, .len = 0xE4,
0606     .features = BIT(DPU_CTL_ACTIVE_CFG),
0607     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
0608     },
0609     {
0610     .name = "ctl_1", .id = CTL_1,
0611     .base = 0x1200, .len = 0xE4,
0612     .features = BIT(DPU_CTL_ACTIVE_CFG),
0613     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
0614     },
0615     {
0616     .name = "ctl_2", .id = CTL_2,
0617     .base = 0x1400, .len = 0xE4,
0618     .features = BIT(DPU_CTL_ACTIVE_CFG),
0619     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
0620     },
0621 };
0622 
0623 static const struct dpu_ctl_cfg sm8150_ctl[] = {
0624     {
0625     .name = "ctl_0", .id = CTL_0,
0626     .base = 0x1000, .len = 0x1e0,
0627     .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
0628     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
0629     },
0630     {
0631     .name = "ctl_1", .id = CTL_1,
0632     .base = 0x1200, .len = 0x1e0,
0633     .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
0634     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
0635     },
0636     {
0637     .name = "ctl_2", .id = CTL_2,
0638     .base = 0x1400, .len = 0x1e0,
0639     .features = BIT(DPU_CTL_ACTIVE_CFG),
0640     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
0641     },
0642     {
0643     .name = "ctl_3", .id = CTL_3,
0644     .base = 0x1600, .len = 0x1e0,
0645     .features = BIT(DPU_CTL_ACTIVE_CFG),
0646     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
0647     },
0648     {
0649     .name = "ctl_4", .id = CTL_4,
0650     .base = 0x1800, .len = 0x1e0,
0651     .features = BIT(DPU_CTL_ACTIVE_CFG),
0652     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
0653     },
0654     {
0655     .name = "ctl_5", .id = CTL_5,
0656     .base = 0x1a00, .len = 0x1e0,
0657     .features = BIT(DPU_CTL_ACTIVE_CFG),
0658     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
0659     },
0660 };
0661 
0662 static const struct dpu_ctl_cfg sc7280_ctl[] = {
0663     {
0664     .name = "ctl_0", .id = CTL_0,
0665     .base = 0x15000, .len = 0x1E8,
0666     .features = CTL_SC7280_MASK,
0667     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
0668     },
0669     {
0670     .name = "ctl_1", .id = CTL_1,
0671     .base = 0x16000, .len = 0x1E8,
0672     .features = CTL_SC7280_MASK,
0673     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
0674     },
0675     {
0676     .name = "ctl_2", .id = CTL_2,
0677     .base = 0x17000, .len = 0x1E8,
0678     .features = CTL_SC7280_MASK,
0679     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
0680     },
0681     {
0682     .name = "ctl_3", .id = CTL_3,
0683     .base = 0x18000, .len = 0x1E8,
0684     .features = CTL_SC7280_MASK,
0685     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
0686     },
0687 };
0688 
0689 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
0690     {
0691     .name = "ctl_0", .id = CTL_0,
0692     .base = 0x1000, .len = 0x1dc,
0693     .features = BIT(DPU_CTL_ACTIVE_CFG),
0694     .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
0695     },
0696 };
0697 
0698 /*************************************************************
0699  * SSPP sub blocks config
0700  *************************************************************/
0701 
0702 /* SSPP common configuration */
0703 #define _VIG_SBLK(num, sdma_pri, qseed_ver) \
0704     { \
0705     .maxdwnscale = MAX_DOWNSCALE_RATIO, \
0706     .maxupscale = MAX_UPSCALE_RATIO, \
0707     .smart_dma_priority = sdma_pri, \
0708     .src_blk = {.name = STRCAT("sspp_src_", num), \
0709         .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
0710     .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
0711         .id = qseed_ver, \
0712         .base = 0xa00, .len = 0xa0,}, \
0713     .csc_blk = {.name = STRCAT("sspp_csc", num), \
0714         .id = DPU_SSPP_CSC_10BIT, \
0715         .base = 0x1a00, .len = 0x100,}, \
0716     .format_list = plane_formats_yuv, \
0717     .num_formats = ARRAY_SIZE(plane_formats_yuv), \
0718     .virt_format_list = plane_formats, \
0719     .virt_num_formats = ARRAY_SIZE(plane_formats), \
0720     .rotation_cfg = NULL, \
0721     }
0722 
0723 #define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \
0724     { \
0725     .maxdwnscale = MAX_DOWNSCALE_RATIO, \
0726     .maxupscale = MAX_UPSCALE_RATIO, \
0727     .smart_dma_priority = sdma_pri, \
0728     .src_blk = {.name = STRCAT("sspp_src_", num), \
0729         .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
0730     .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
0731         .id = qseed_ver, \
0732         .base = 0xa00, .len = 0xa0,}, \
0733     .csc_blk = {.name = STRCAT("sspp_csc", num), \
0734         .id = DPU_SSPP_CSC_10BIT, \
0735         .base = 0x1a00, .len = 0x100,}, \
0736     .format_list = plane_formats_yuv, \
0737     .num_formats = ARRAY_SIZE(plane_formats_yuv), \
0738     .virt_format_list = plane_formats, \
0739     .virt_num_formats = ARRAY_SIZE(plane_formats), \
0740     .rotation_cfg = rot_cfg, \
0741     }
0742 
0743 #define _DMA_SBLK(num, sdma_pri) \
0744     { \
0745     .maxdwnscale = SSPP_UNITY_SCALE, \
0746     .maxupscale = SSPP_UNITY_SCALE, \
0747     .smart_dma_priority = sdma_pri, \
0748     .src_blk = {.name = STRCAT("sspp_src_", num), \
0749         .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
0750     .format_list = plane_formats, \
0751     .num_formats = ARRAY_SIZE(plane_formats), \
0752     .virt_format_list = plane_formats, \
0753     .virt_num_formats = ARRAY_SIZE(plane_formats), \
0754     }
0755 
0756 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
0757                 _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3);
0758 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
0759                 _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3);
0760 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
0761                 _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3);
0762 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
0763                 _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3);
0764 
0765 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
0766     .rot_maxheight = 1088,
0767     .rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
0768     .rot_format_list = rotation_v2_formats,
0769 };
0770 
0771 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
0772                 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
0773 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
0774                 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
0775 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
0776                 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
0777 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
0778                 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
0779 
0780 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
0781 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
0782 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
0783 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
0784 
0785 #define SSPP_BLK(_name, _id, _base, _features, \
0786         _sblk, _xinid, _type, _clkctrl) \
0787     { \
0788     .name = _name, .id = _id, \
0789     .base = _base, .len = 0x1c8, \
0790     .features = _features, \
0791     .sblk = &_sblk, \
0792     .xin_id = _xinid, \
0793     .type = _type, \
0794     .clk_ctrl = _clkctrl \
0795     }
0796 
0797 static const struct dpu_sspp_cfg msm8998_sspp[] = {
0798     SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK,
0799         msm8998_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
0800     SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK,
0801         msm8998_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
0802     SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK,
0803         msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
0804     SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK,
0805         msm8998_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
0806     SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_MSM8998_MASK,
0807         sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
0808     SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_MSM8998_MASK,
0809         sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
0810     SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_MSM8998_MASK,
0811         sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
0812     SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_MSM8998_MASK,
0813         sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
0814 };
0815 
0816 static const struct dpu_sspp_cfg sdm845_sspp[] = {
0817     SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
0818         sdm845_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
0819     SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
0820         sdm845_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
0821     SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
0822         sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
0823     SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
0824         sdm845_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
0825     SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
0826         sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
0827     SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
0828         sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
0829     SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
0830         sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
0831     SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_SDM845_MASK,
0832         sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
0833 };
0834 
0835 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
0836                 _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
0837 
0838 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
0839             _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
0840 
0841 static const struct dpu_sspp_cfg sc7180_sspp[] = {
0842     SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
0843         sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
0844     SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
0845         sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
0846     SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
0847         sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
0848     SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
0849         sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
0850 };
0851 
0852 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
0853                 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
0854 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
0855                 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
0856 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
0857                 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
0858 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
0859                 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
0860 
0861 static const struct dpu_sspp_cfg sm8250_sspp[] = {
0862     SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
0863         sm8250_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
0864     SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
0865         sm8250_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
0866     SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
0867         sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
0868     SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
0869         sm8250_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
0870     SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
0871         sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
0872     SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
0873         sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
0874     SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
0875         sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
0876     SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_SDM845_MASK,
0877         sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
0878 };
0879 
0880 static const struct dpu_sspp_cfg sc7280_sspp[] = {
0881     SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
0882         sc7280_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
0883     SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
0884         sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
0885     SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
0886         sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
0887     SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
0888         sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
0889 };
0890 
0891 
0892 #define _VIG_SBLK_NOSCALE(num, sdma_pri) \
0893     { \
0894     .maxdwnscale = SSPP_UNITY_SCALE, \
0895     .maxupscale = SSPP_UNITY_SCALE, \
0896     .smart_dma_priority = sdma_pri, \
0897     .src_blk = {.name = STRCAT("sspp_src_", num), \
0898         .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
0899     .format_list = plane_formats_yuv, \
0900     .num_formats = ARRAY_SIZE(plane_formats_yuv), \
0901     .virt_format_list = plane_formats, \
0902     .virt_num_formats = ARRAY_SIZE(plane_formats), \
0903     }
0904 
0905 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2);
0906 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
0907 
0908 static const struct dpu_sspp_cfg qcm2290_sspp[] = {
0909     SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
0910          qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
0911     SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
0912          qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
0913 };
0914 
0915 /*************************************************************
0916  * MIXER sub blocks config
0917  *************************************************************/
0918 
0919 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
0920     { \
0921     .name = _name, .id = _id, \
0922     .base = _base, .len = 0x320, \
0923     .features = _fmask, \
0924     .sblk = _sblk, \
0925     .pingpong = _pp, \
0926     .lm_pair_mask = (1 << _lmpair), \
0927     .dspp = _dspp \
0928     }
0929 
0930 /* MSM8998 */
0931 
0932 static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
0933     .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0934     .maxblendstages = 7, /* excluding base layer */
0935     .blendstage_base = { /* offsets relative to mixer base */
0936         0x20, 0x50, 0x80, 0xb0, 0x230,
0937         0x260, 0x290
0938     },
0939 };
0940 
0941 static const struct dpu_lm_cfg msm8998_lm[] = {
0942     LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
0943         &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0),
0944     LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
0945         &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1),
0946     LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
0947         &msm8998_lm_sblk, PINGPONG_2, LM_0, 0),
0948     LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
0949         &msm8998_lm_sblk, PINGPONG_MAX, 0, 0),
0950     LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
0951         &msm8998_lm_sblk, PINGPONG_MAX, 0, 0),
0952     LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
0953         &msm8998_lm_sblk, PINGPONG_3, LM_1, 0),
0954 };
0955 
0956 /* SDM845 */
0957 
0958 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
0959     .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0960     .maxblendstages = 11, /* excluding base layer */
0961     .blendstage_base = { /* offsets relative to mixer base */
0962         0x20, 0x38, 0x50, 0x68, 0x80, 0x98,
0963         0xb0, 0xc8, 0xe0, 0xf8, 0x110
0964     },
0965 };
0966 
0967 static const struct dpu_lm_cfg sdm845_lm[] = {
0968     LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
0969         &sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
0970     LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
0971         &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
0972     LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
0973         &sdm845_lm_sblk, PINGPONG_2, LM_5, 0),
0974     LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
0975         &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
0976     LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
0977         &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
0978     LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
0979         &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
0980 };
0981 
0982 /* SC7180 */
0983 
0984 static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
0985     .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
0986     .maxblendstages = 7, /* excluding base layer */
0987     .blendstage_base = { /* offsets relative to mixer base */
0988         0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
0989     },
0990 };
0991 
0992 static const struct dpu_lm_cfg sc7180_lm[] = {
0993     LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
0994         &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
0995     LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK,
0996         &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
0997 };
0998 
0999 /* SM8150 */
1000 
1001 static const struct dpu_lm_cfg sm8150_lm[] = {
1002     LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
1003         &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
1004     LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
1005         &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
1006     LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
1007         &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
1008     LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
1009         &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
1010     LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
1011         &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
1012     LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
1013         &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
1014 };
1015 
1016 static const struct dpu_lm_cfg sc7280_lm[] = {
1017     LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
1018         &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
1019     LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
1020         &sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
1021     LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
1022         &sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
1023 };
1024 
1025 /* QCM2290 */
1026 
1027 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
1028     .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
1029     .maxblendstages = 4, /* excluding base layer */
1030     .blendstage_base = { /* offsets relative to mixer base */
1031         0x20, 0x38, 0x50, 0x68
1032     },
1033 };
1034 
1035 static const struct dpu_lm_cfg qcm2290_lm[] = {
1036     LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
1037         &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
1038 };
1039 
1040 /*************************************************************
1041  * DSPP sub blocks config
1042  *************************************************************/
1043 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {
1044     .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1045         .len = 0x90, .version = 0x10007},
1046     .gc = { .id = DPU_DSPP_GC, .base = 0x17c0,
1047         .len = 0x90, .version = 0x10007},
1048 };
1049 
1050 static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = {
1051     .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1052         .len = 0x90, .version = 0x10000},
1053 };
1054 
1055 static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
1056     .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1057         .len = 0x90, .version = 0x40000},
1058 };
1059 
1060 #define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
1061         {\
1062         .name = _name, .id = _id, \
1063         .base = _base, .len = 0x1800, \
1064         .features = _mask, \
1065         .sblk = _sblk \
1066         }
1067 
1068 static const struct dpu_dspp_cfg msm8998_dspp[] = {
1069     DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK,
1070          &msm8998_dspp_sblk),
1071     DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK,
1072          &msm8998_dspp_sblk),
1073 };
1074 
1075 static const struct dpu_dspp_cfg sc7180_dspp[] = {
1076     DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1077          &sc7180_dspp_sblk),
1078 };
1079 
1080 static const struct dpu_dspp_cfg sm8150_dspp[] = {
1081     DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1082          &sm8150_dspp_sblk),
1083     DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
1084          &sm8150_dspp_sblk),
1085     DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
1086          &sm8150_dspp_sblk),
1087     DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
1088          &sm8150_dspp_sblk),
1089 };
1090 
1091 static const struct dpu_dspp_cfg qcm2290_dspp[] = {
1092     DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1093          &sm8150_dspp_sblk),
1094 };
1095 
1096 /*************************************************************
1097  * PINGPONG sub blocks config
1098  *************************************************************/
1099 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {
1100     .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
1101         .version = 0x1},
1102     .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
1103         .len = 0x20, .version = 0x10000},
1104 };
1105 
1106 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
1107     .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
1108         .len = 0x20, .version = 0x10000},
1109 };
1110 
1111 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
1112     .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
1113     .len = 0x20, .version = 0x20000},
1114 };
1115 
1116 #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
1117     {\
1118     .name = _name, .id = _id, \
1119     .base = _base, .len = 0xd4, \
1120     .features = PINGPONG_SDM845_SPLIT_MASK, \
1121     .merge_3d = _merge_3d, \
1122     .sblk = &_sblk, \
1123     .intr_done = _done, \
1124     .intr_rdptr = _rdptr, \
1125     }
1126 #define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
1127     {\
1128     .name = _name, .id = _id, \
1129     .base = _base, .len = 0xd4, \
1130     .features = PINGPONG_SDM845_MASK, \
1131     .merge_3d = _merge_3d, \
1132     .sblk = &_sblk, \
1133     .intr_done = _done, \
1134     .intr_rdptr = _rdptr, \
1135     }
1136 
1137 static const struct dpu_pingpong_cfg sdm845_pp[] = {
1138     PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
1139             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1140             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1141     PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
1142             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1143             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
1144     PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
1145             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1146             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
1147     PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
1148             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1149             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
1150 };
1151 
1152 static struct dpu_pingpong_cfg sc7180_pp[] = {
1153     PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
1154     PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
1155 };
1156 
1157 static const struct dpu_pingpong_cfg sm8150_pp[] = {
1158     PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
1159             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1160             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1161     PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
1162             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1163             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
1164     PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
1165             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1166             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
1167     PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
1168             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1169             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
1170     PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
1171             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
1172             -1),
1173     PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
1174             DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
1175             -1),
1176 };
1177 
1178 static struct dpu_pingpong_cfg qcm2290_pp[] = {
1179     PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
1180         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1181         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1182 };
1183 
1184 /*************************************************************
1185  * MERGE_3D sub blocks config
1186  *************************************************************/
1187 #define MERGE_3D_BLK(_name, _id, _base) \
1188     {\
1189     .name = _name, .id = _id, \
1190     .base = _base, .len = 0x100, \
1191     .features = MERGE_3D_SM8150_MASK, \
1192     .sblk = NULL \
1193     }
1194 
1195 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
1196     MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
1197     MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
1198     MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
1199 };
1200 
1201 static const struct dpu_pingpong_cfg sc7280_pp[] = {
1202     PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
1203     PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
1204     PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
1205     PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
1206 };
1207 
1208 /*************************************************************
1209  * DSC sub blocks config
1210  *************************************************************/
1211 #define DSC_BLK(_name, _id, _base) \
1212     {\
1213     .name = _name, .id = _id, \
1214     .base = _base, .len = 0x140, \
1215     .features = 0, \
1216     }
1217 
1218 static struct dpu_dsc_cfg sdm845_dsc[] = {
1219     DSC_BLK("dsc_0", DSC_0, 0x80000),
1220     DSC_BLK("dsc_1", DSC_1, 0x80400),
1221     DSC_BLK("dsc_2", DSC_2, 0x80800),
1222     DSC_BLK("dsc_3", DSC_3, 0x80c00),
1223 };
1224 
1225 /*************************************************************
1226  * INTF sub blocks config
1227  *************************************************************/
1228 #define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
1229     {\
1230     .name = _name, .id = _id, \
1231     .base = _base, .len = 0x280, \
1232     .features = _features, \
1233     .type = _type, \
1234     .controller_id = _ctrl_id, \
1235     .prog_fetch_lines_worst_case = _progfetch, \
1236     .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
1237     .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
1238     }
1239 
1240 static const struct dpu_intf_cfg msm8998_intf[] = {
1241     INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1242     INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1243     INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1244     INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1245 };
1246 
1247 static const struct dpu_intf_cfg sdm845_intf[] = {
1248     INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1249     INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1250     INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1251     INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1252 };
1253 
1254 static const struct dpu_intf_cfg sc7180_intf[] = {
1255     INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1256     INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1257 };
1258 
1259 static const struct dpu_intf_cfg sm8150_intf[] = {
1260     INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1261     INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1262     INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1263     INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1264 };
1265 
1266 static const struct dpu_intf_cfg sc7280_intf[] = {
1267     INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1268     INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1269     INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
1270 };
1271 
1272 static const struct dpu_intf_cfg sc8180x_intf[] = {
1273     INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1274     INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1275     INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1276     /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
1277     INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1278     INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
1279     INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
1280 };
1281 
1282 static const struct dpu_intf_cfg qcm2290_intf[] = {
1283     INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),
1284     INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1285 };
1286 
1287 /*************************************************************
1288  * Writeback blocks config
1289  *************************************************************/
1290 #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
1291         __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
1292     { \
1293     .name = _name, .id = _id, \
1294     .base = _base, .len = 0x2c8, \
1295     .features = _features, \
1296     .format_list = wb2_formats, \
1297     .num_formats = ARRAY_SIZE(wb2_formats), \
1298     .clk_ctrl = _clk_ctrl, \
1299     .xin_id = __xin_id, \
1300     .vbif_idx = vbif_id, \
1301     .maxlinewidth = _max_linewidth, \
1302     .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
1303     }
1304 
1305 static const struct dpu_wb_cfg sm8250_wb[] = {
1306     WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
1307             VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
1308 };
1309 
1310 /*************************************************************
1311  * VBIF sub blocks config
1312  *************************************************************/
1313 /* VBIF QOS remap */
1314 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};
1315 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};
1316 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
1317 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
1318 
1319 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
1320     {
1321         .pps = 1088 * 1920 * 30,
1322         .ot_limit = 2,
1323     },
1324     {
1325         .pps = 1088 * 1920 * 60,
1326         .ot_limit = 6,
1327     },
1328     {
1329         .pps = 3840 * 2160 * 30,
1330         .ot_limit = 16,
1331     },
1332 };
1333 
1334 static const struct dpu_vbif_cfg msm8998_vbif[] = {
1335     {
1336     .name = "vbif_0", .id = VBIF_0,
1337     .base = 0, .len = 0x1040,
1338     .default_ot_rd_limit = 32,
1339     .default_ot_wr_limit = 32,
1340     .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM),
1341     .xin_halt_timeout = 0x4000,
1342     .qos_rp_remap_size = 0x20,
1343     .dynamic_ot_rd_tbl = {
1344         .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
1345         .cfg = msm8998_ot_rdwr_cfg,
1346         },
1347     .dynamic_ot_wr_tbl = {
1348         .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
1349         .cfg = msm8998_ot_rdwr_cfg,
1350         },
1351     .qos_rt_tbl = {
1352         .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl),
1353         .priority_lvl = msm8998_rt_pri_lvl,
1354         },
1355     .qos_nrt_tbl = {
1356         .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl),
1357         .priority_lvl = msm8998_nrt_pri_lvl,
1358         },
1359     .memtype_count = 14,
1360     .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
1361     },
1362 };
1363 
1364 static const struct dpu_vbif_cfg sdm845_vbif[] = {
1365     {
1366     .name = "vbif_0", .id = VBIF_0,
1367     .base = 0, .len = 0x1040,
1368     .features = BIT(DPU_VBIF_QOS_REMAP),
1369     .xin_halt_timeout = 0x4000,
1370     .qos_rp_remap_size = 0x40,
1371     .qos_rt_tbl = {
1372         .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
1373         .priority_lvl = sdm845_rt_pri_lvl,
1374         },
1375     .qos_nrt_tbl = {
1376         .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
1377         .priority_lvl = sdm845_nrt_pri_lvl,
1378         },
1379     .memtype_count = 14,
1380     .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
1381     },
1382 };
1383 
1384 static const struct dpu_reg_dma_cfg sdm845_regdma = {
1385     .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
1386 };
1387 
1388 static const struct dpu_reg_dma_cfg sm8150_regdma = {
1389     .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
1390 };
1391 
1392 static const struct dpu_reg_dma_cfg sm8250_regdma = {
1393     .base = 0x0,
1394     .version = 0x00010002,
1395     .trigger_sel_off = 0x119c,
1396     .xin_id = 7,
1397     .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
1398 };
1399 
1400 /*************************************************************
1401  * PERF data config
1402  *************************************************************/
1403 
1404 /* SSPP QOS LUTs */
1405 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = {
1406     {.fl = 4,  .lut = 0x1b},
1407     {.fl = 5,  .lut = 0x5b},
1408     {.fl = 6,  .lut = 0x15b},
1409     {.fl = 7,  .lut = 0x55b},
1410     {.fl = 8,  .lut = 0x155b},
1411     {.fl = 9,  .lut = 0x555b},
1412     {.fl = 10, .lut = 0x1555b},
1413     {.fl = 11, .lut = 0x5555b},
1414     {.fl = 12, .lut = 0x15555b},
1415     {.fl = 13, .lut = 0x55555b},
1416     {.fl = 14, .lut = 0},
1417     {.fl = 1,  .lut = 0x1b},
1418     {.fl = 0,  .lut = 0}
1419 };
1420 
1421 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
1422     {.fl = 4, .lut = 0x357},
1423     {.fl = 5, .lut = 0x3357},
1424     {.fl = 6, .lut = 0x23357},
1425     {.fl = 7, .lut = 0x223357},
1426     {.fl = 8, .lut = 0x2223357},
1427     {.fl = 9, .lut = 0x22223357},
1428     {.fl = 10, .lut = 0x222223357},
1429     {.fl = 11, .lut = 0x2222223357},
1430     {.fl = 12, .lut = 0x22222223357},
1431     {.fl = 13, .lut = 0x222222223357},
1432     {.fl = 14, .lut = 0x1222222223357},
1433     {.fl = 0, .lut = 0x11222222223357}
1434 };
1435 
1436 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = {
1437     {.fl = 10, .lut = 0x1aaff},
1438     {.fl = 11, .lut = 0x5aaff},
1439     {.fl = 12, .lut = 0x15aaff},
1440     {.fl = 13, .lut = 0x55aaff},
1441     {.fl = 1,  .lut = 0x1aaff},
1442     {.fl = 0,  .lut = 0},
1443 };
1444 
1445 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
1446     {.fl = 0, .lut = 0x0011222222335777},
1447 };
1448 
1449 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
1450     {.fl = 0, .lut = 0x0011222222223357 },
1451 };
1452 
1453 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = {
1454     {.fl = 4, .lut = 0x0000000000000357 },
1455 };
1456 
1457 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = {
1458     {.fl = 0, .lut = 0x0011222222335777},
1459 };
1460 
1461 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
1462     {.fl = 10, .lut = 0x344556677},
1463     {.fl = 11, .lut = 0x3344556677},
1464     {.fl = 12, .lut = 0x23344556677},
1465     {.fl = 13, .lut = 0x223344556677},
1466     {.fl = 14, .lut = 0x1223344556677},
1467     {.fl = 0, .lut = 0x112233344556677},
1468 };
1469 
1470 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
1471     {.fl = 0, .lut = 0x0011223344556677},
1472 };
1473 
1474 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
1475     {.fl = 10, .lut = 0x0000000344556677},
1476 };
1477 
1478 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = {
1479     {.fl = 0, .lut = 0x0},
1480 };
1481 
1482 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
1483     {.fl = 0, .lut = 0x0},
1484 };
1485 
1486 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
1487     {.fl = 0, .lut = 0x0},
1488 };
1489 
1490 static const struct dpu_perf_cfg msm8998_perf_data = {
1491     .max_bw_low = 6700000,
1492     .max_bw_high = 6700000,
1493     .min_core_ib = 2400000,
1494     .min_llcc_ib = 800000,
1495     .min_dram_ib = 800000,
1496     .undersized_prefill_lines = 2,
1497     .xtra_prefill_lines = 2,
1498     .dest_scale_prefill_lines = 3,
1499     .macrotile_prefill_lines = 4,
1500     .yuv_nv12_prefill_lines = 8,
1501     .linear_prefill_lines = 1,
1502     .downscaling_prefill_lines = 1,
1503     .amortizable_threshold = 25,
1504     .min_prefill_lines = 25,
1505     .danger_lut_tbl = {0xf, 0xffff, 0x0},
1506     .safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
1507     .qos_lut_tbl = {
1508         {.nentry = ARRAY_SIZE(msm8998_qos_linear),
1509         .entries = msm8998_qos_linear
1510         },
1511         {.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
1512         .entries = msm8998_qos_macrotile
1513         },
1514         {.nentry = ARRAY_SIZE(msm8998_qos_nrt),
1515         .entries = msm8998_qos_nrt
1516         },
1517     },
1518     .cdp_cfg = {
1519         {.rd_enable = 1, .wr_enable = 1},
1520         {.rd_enable = 1, .wr_enable = 0}
1521     },
1522     .clk_inefficiency_factor = 200,
1523     .bw_inefficiency_factor = 120,
1524 };
1525 
1526 static const struct dpu_perf_cfg sdm845_perf_data = {
1527     .max_bw_low = 6800000,
1528     .max_bw_high = 6800000,
1529     .min_core_ib = 2400000,
1530     .min_llcc_ib = 800000,
1531     .min_dram_ib = 800000,
1532     .undersized_prefill_lines = 2,
1533     .xtra_prefill_lines = 2,
1534     .dest_scale_prefill_lines = 3,
1535     .macrotile_prefill_lines = 4,
1536     .yuv_nv12_prefill_lines = 8,
1537     .linear_prefill_lines = 1,
1538     .downscaling_prefill_lines = 1,
1539     .amortizable_threshold = 25,
1540     .min_prefill_lines = 24,
1541     .danger_lut_tbl = {0xf, 0xffff, 0x0},
1542     .safe_lut_tbl = {0xfff0, 0xf000, 0xffff},
1543     .qos_lut_tbl = {
1544         {.nentry = ARRAY_SIZE(sdm845_qos_linear),
1545         .entries = sdm845_qos_linear
1546         },
1547         {.nentry = ARRAY_SIZE(sdm845_qos_macrotile),
1548         .entries = sdm845_qos_macrotile
1549         },
1550         {.nentry = ARRAY_SIZE(sdm845_qos_nrt),
1551         .entries = sdm845_qos_nrt
1552         },
1553     },
1554     .cdp_cfg = {
1555         {.rd_enable = 1, .wr_enable = 1},
1556         {.rd_enable = 1, .wr_enable = 0}
1557     },
1558     .clk_inefficiency_factor = 105,
1559     .bw_inefficiency_factor = 120,
1560 };
1561 
1562 static const struct dpu_perf_cfg sc7180_perf_data = {
1563     .max_bw_low = 6800000,
1564     .max_bw_high = 6800000,
1565     .min_core_ib = 2400000,
1566     .min_llcc_ib = 800000,
1567     .min_dram_ib = 1600000,
1568     .min_prefill_lines = 24,
1569     .danger_lut_tbl = {0xff, 0xffff, 0x0},
1570     .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
1571     .qos_lut_tbl = {
1572         {.nentry = ARRAY_SIZE(sc7180_qos_linear),
1573         .entries = sc7180_qos_linear
1574         },
1575         {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1576         .entries = sc7180_qos_macrotile
1577         },
1578         {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1579         .entries = sc7180_qos_nrt
1580         },
1581     },
1582     .cdp_cfg = {
1583         {.rd_enable = 1, .wr_enable = 1},
1584         {.rd_enable = 1, .wr_enable = 0}
1585     },
1586     .clk_inefficiency_factor = 105,
1587     .bw_inefficiency_factor = 120,
1588 };
1589 
1590 static const struct dpu_perf_cfg sm8150_perf_data = {
1591     .max_bw_low = 12800000,
1592     .max_bw_high = 12800000,
1593     .min_core_ib = 2400000,
1594     .min_llcc_ib = 800000,
1595     .min_dram_ib = 800000,
1596     .min_prefill_lines = 24,
1597     .danger_lut_tbl = {0xf, 0xffff, 0x0},
1598     .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
1599     .qos_lut_tbl = {
1600         {.nentry = ARRAY_SIZE(sm8150_qos_linear),
1601         .entries = sm8150_qos_linear
1602         },
1603         {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1604         .entries = sc7180_qos_macrotile
1605         },
1606         {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1607         .entries = sc7180_qos_nrt
1608         },
1609         /* TODO: macrotile-qseed is different from macrotile */
1610     },
1611     .cdp_cfg = {
1612         {.rd_enable = 1, .wr_enable = 1},
1613         {.rd_enable = 1, .wr_enable = 0}
1614     },
1615     .clk_inefficiency_factor = 105,
1616     .bw_inefficiency_factor = 120,
1617 };
1618 
1619 static const struct dpu_perf_cfg sc8180x_perf_data = {
1620     .max_bw_low = 9600000,
1621     .max_bw_high = 9600000,
1622     .min_core_ib = 2400000,
1623     .min_llcc_ib = 800000,
1624     .min_dram_ib = 800000,
1625     .danger_lut_tbl = {0xf, 0xffff, 0x0},
1626     .qos_lut_tbl = {
1627         {.nentry = ARRAY_SIZE(sc8180x_qos_linear),
1628         .entries = sc8180x_qos_linear
1629         },
1630         {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile),
1631         .entries = sc8180x_qos_macrotile
1632         },
1633         {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1634         .entries = sc7180_qos_nrt
1635         },
1636         /* TODO: macrotile-qseed is different from macrotile */
1637     },
1638     .cdp_cfg = {
1639         {.rd_enable = 1, .wr_enable = 1},
1640         {.rd_enable = 1, .wr_enable = 0}
1641     },
1642     .clk_inefficiency_factor = 105,
1643     .bw_inefficiency_factor = 120,
1644 };
1645 
1646 static const struct dpu_perf_cfg sm8250_perf_data = {
1647     .max_bw_low = 13700000,
1648     .max_bw_high = 16600000,
1649     .min_core_ib = 4800000,
1650     .min_llcc_ib = 0,
1651     .min_dram_ib = 800000,
1652     .min_prefill_lines = 35,
1653     .danger_lut_tbl = {0xf, 0xffff, 0x0},
1654     .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
1655     .qos_lut_tbl = {
1656         {.nentry = ARRAY_SIZE(sc7180_qos_linear),
1657         .entries = sc7180_qos_linear
1658         },
1659         {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1660         .entries = sc7180_qos_macrotile
1661         },
1662         {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1663         .entries = sc7180_qos_nrt
1664         },
1665         /* TODO: macrotile-qseed is different from macrotile */
1666     },
1667     .cdp_cfg = {
1668         {.rd_enable = 1, .wr_enable = 1},
1669         {.rd_enable = 1, .wr_enable = 0}
1670     },
1671     .clk_inefficiency_factor = 105,
1672     .bw_inefficiency_factor = 120,
1673 };
1674 
1675 static const struct dpu_perf_cfg sc7280_perf_data = {
1676     .max_bw_low = 4700000,
1677     .max_bw_high = 8800000,
1678     .min_core_ib = 2500000,
1679     .min_llcc_ib = 0,
1680     .min_dram_ib = 1600000,
1681     .min_prefill_lines = 24,
1682     .danger_lut_tbl = {0xffff, 0xffff, 0x0},
1683     .safe_lut_tbl = {0xff00, 0xff00, 0xffff},
1684     .qos_lut_tbl = {
1685         {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1686         .entries = sc7180_qos_macrotile
1687         },
1688         {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1689         .entries = sc7180_qos_macrotile
1690         },
1691         {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1692         .entries = sc7180_qos_nrt
1693         },
1694     },
1695     .cdp_cfg = {
1696         {.rd_enable = 1, .wr_enable = 1},
1697         {.rd_enable = 1, .wr_enable = 0}
1698     },
1699     .clk_inefficiency_factor = 105,
1700     .bw_inefficiency_factor = 120,
1701 };
1702 
1703 static const struct dpu_perf_cfg qcm2290_perf_data = {
1704     .max_bw_low = 2700000,
1705     .max_bw_high = 2700000,
1706     .min_core_ib = 1300000,
1707     .min_llcc_ib = 0,
1708     .min_dram_ib = 1600000,
1709     .min_prefill_lines = 24,
1710     .danger_lut_tbl = {0xff, 0x0, 0x0},
1711     .safe_lut_tbl = {0xfff0, 0x0, 0x0},
1712     .qos_lut_tbl = {
1713         {.nentry = ARRAY_SIZE(qcm2290_qos_linear),
1714         .entries = qcm2290_qos_linear
1715         },
1716     },
1717     .cdp_cfg = {
1718         {.rd_enable = 1, .wr_enable = 1},
1719         {.rd_enable = 1, .wr_enable = 0}
1720     },
1721     .clk_inefficiency_factor = 105,
1722     .bw_inefficiency_factor = 120,
1723 };
1724 /*************************************************************
1725  * Hardware catalog
1726  *************************************************************/
1727 
1728 static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
1729     .caps = &msm8998_dpu_caps,
1730     .mdp_count = ARRAY_SIZE(msm8998_mdp),
1731     .mdp = msm8998_mdp,
1732     .ctl_count = ARRAY_SIZE(msm8998_ctl),
1733     .ctl = msm8998_ctl,
1734     .sspp_count = ARRAY_SIZE(msm8998_sspp),
1735     .sspp = msm8998_sspp,
1736     .mixer_count = ARRAY_SIZE(msm8998_lm),
1737     .mixer = msm8998_lm,
1738     .dspp_count = ARRAY_SIZE(msm8998_dspp),
1739     .dspp = msm8998_dspp,
1740     .pingpong_count = ARRAY_SIZE(sdm845_pp),
1741     .pingpong = sdm845_pp,
1742     .intf_count = ARRAY_SIZE(msm8998_intf),
1743     .intf = msm8998_intf,
1744     .vbif_count = ARRAY_SIZE(msm8998_vbif),
1745     .vbif = msm8998_vbif,
1746     .reg_dma_count = 0,
1747     .perf = &msm8998_perf_data,
1748     .mdss_irqs = IRQ_SM8250_MASK,
1749 };
1750 
1751 static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
1752     .caps = &sdm845_dpu_caps,
1753     .mdp_count = ARRAY_SIZE(sdm845_mdp),
1754     .mdp = sdm845_mdp,
1755     .ctl_count = ARRAY_SIZE(sdm845_ctl),
1756     .ctl = sdm845_ctl,
1757     .sspp_count = ARRAY_SIZE(sdm845_sspp),
1758     .sspp = sdm845_sspp,
1759     .mixer_count = ARRAY_SIZE(sdm845_lm),
1760     .mixer = sdm845_lm,
1761     .pingpong_count = ARRAY_SIZE(sdm845_pp),
1762     .pingpong = sdm845_pp,
1763     .dsc_count = ARRAY_SIZE(sdm845_dsc),
1764     .dsc = sdm845_dsc,
1765     .intf_count = ARRAY_SIZE(sdm845_intf),
1766     .intf = sdm845_intf,
1767     .vbif_count = ARRAY_SIZE(sdm845_vbif),
1768     .vbif = sdm845_vbif,
1769     .reg_dma_count = 1,
1770     .dma_cfg = &sdm845_regdma,
1771     .perf = &sdm845_perf_data,
1772     .mdss_irqs = IRQ_SDM845_MASK,
1773 };
1774 
1775 static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
1776     .caps = &sc7180_dpu_caps,
1777     .mdp_count = ARRAY_SIZE(sc7180_mdp),
1778     .mdp = sc7180_mdp,
1779     .ctl_count = ARRAY_SIZE(sc7180_ctl),
1780     .ctl = sc7180_ctl,
1781     .sspp_count = ARRAY_SIZE(sc7180_sspp),
1782     .sspp = sc7180_sspp,
1783     .mixer_count = ARRAY_SIZE(sc7180_lm),
1784     .mixer = sc7180_lm,
1785     .dspp_count = ARRAY_SIZE(sc7180_dspp),
1786     .dspp = sc7180_dspp,
1787     .pingpong_count = ARRAY_SIZE(sc7180_pp),
1788     .pingpong = sc7180_pp,
1789     .intf_count = ARRAY_SIZE(sc7180_intf),
1790     .intf = sc7180_intf,
1791     .wb_count = ARRAY_SIZE(sm8250_wb),
1792     .wb = sm8250_wb,
1793     .vbif_count = ARRAY_SIZE(sdm845_vbif),
1794     .vbif = sdm845_vbif,
1795     .reg_dma_count = 1,
1796     .dma_cfg = &sdm845_regdma,
1797     .perf = &sc7180_perf_data,
1798     .mdss_irqs = IRQ_SC7180_MASK,
1799 };
1800 
1801 static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
1802     .caps = &sm8150_dpu_caps,
1803     .mdp_count = ARRAY_SIZE(sdm845_mdp),
1804     .mdp = sdm845_mdp,
1805     .ctl_count = ARRAY_SIZE(sm8150_ctl),
1806     .ctl = sm8150_ctl,
1807     .sspp_count = ARRAY_SIZE(sdm845_sspp),
1808     .sspp = sdm845_sspp,
1809     .mixer_count = ARRAY_SIZE(sm8150_lm),
1810     .mixer = sm8150_lm,
1811     .dspp_count = ARRAY_SIZE(sm8150_dspp),
1812     .dspp = sm8150_dspp,
1813     .pingpong_count = ARRAY_SIZE(sm8150_pp),
1814     .pingpong = sm8150_pp,
1815     .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1816     .merge_3d = sm8150_merge_3d,
1817     .intf_count = ARRAY_SIZE(sm8150_intf),
1818     .intf = sm8150_intf,
1819     .vbif_count = ARRAY_SIZE(sdm845_vbif),
1820     .vbif = sdm845_vbif,
1821     .reg_dma_count = 1,
1822     .dma_cfg = &sm8150_regdma,
1823     .perf = &sm8150_perf_data,
1824     .mdss_irqs = IRQ_SDM845_MASK,
1825 };
1826 
1827 static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
1828     .caps = &sc8180x_dpu_caps,
1829     .mdp_count = ARRAY_SIZE(sc8180x_mdp),
1830     .mdp = sc8180x_mdp,
1831     .ctl_count = ARRAY_SIZE(sm8150_ctl),
1832     .ctl = sm8150_ctl,
1833     .sspp_count = ARRAY_SIZE(sdm845_sspp),
1834     .sspp = sdm845_sspp,
1835     .mixer_count = ARRAY_SIZE(sm8150_lm),
1836     .mixer = sm8150_lm,
1837     .pingpong_count = ARRAY_SIZE(sm8150_pp),
1838     .pingpong = sm8150_pp,
1839     .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1840     .merge_3d = sm8150_merge_3d,
1841     .intf_count = ARRAY_SIZE(sc8180x_intf),
1842     .intf = sc8180x_intf,
1843     .vbif_count = ARRAY_SIZE(sdm845_vbif),
1844     .vbif = sdm845_vbif,
1845     .reg_dma_count = 1,
1846     .dma_cfg = &sm8150_regdma,
1847     .perf = &sc8180x_perf_data,
1848     .mdss_irqs = IRQ_SC8180X_MASK,
1849 };
1850 
1851 static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
1852     .caps = &sm8250_dpu_caps,
1853     .mdp_count = ARRAY_SIZE(sm8250_mdp),
1854     .mdp = sm8250_mdp,
1855     .ctl_count = ARRAY_SIZE(sm8150_ctl),
1856     .ctl = sm8150_ctl,
1857     .sspp_count = ARRAY_SIZE(sm8250_sspp),
1858     .sspp = sm8250_sspp,
1859     .mixer_count = ARRAY_SIZE(sm8150_lm),
1860     .mixer = sm8150_lm,
1861     .dspp_count = ARRAY_SIZE(sm8150_dspp),
1862     .dspp = sm8150_dspp,
1863     .pingpong_count = ARRAY_SIZE(sm8150_pp),
1864     .pingpong = sm8150_pp,
1865     .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1866     .merge_3d = sm8150_merge_3d,
1867     .intf_count = ARRAY_SIZE(sm8150_intf),
1868     .intf = sm8150_intf,
1869     .vbif_count = ARRAY_SIZE(sdm845_vbif),
1870     .vbif = sdm845_vbif,
1871     .wb_count = ARRAY_SIZE(sm8250_wb),
1872     .wb = sm8250_wb,
1873     .reg_dma_count = 1,
1874     .dma_cfg = &sm8250_regdma,
1875     .perf = &sm8250_perf_data,
1876     .mdss_irqs = IRQ_SM8250_MASK,
1877 };
1878 
1879 static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
1880     .caps = &sc7280_dpu_caps,
1881     .mdp_count = ARRAY_SIZE(sc7280_mdp),
1882     .mdp = sc7280_mdp,
1883     .ctl_count = ARRAY_SIZE(sc7280_ctl),
1884     .ctl = sc7280_ctl,
1885     .sspp_count = ARRAY_SIZE(sc7280_sspp),
1886     .sspp = sc7280_sspp,
1887     .dspp_count = ARRAY_SIZE(sc7180_dspp),
1888     .dspp = sc7180_dspp,
1889     .mixer_count = ARRAY_SIZE(sc7280_lm),
1890     .mixer = sc7280_lm,
1891     .pingpong_count = ARRAY_SIZE(sc7280_pp),
1892     .pingpong = sc7280_pp,
1893     .intf_count = ARRAY_SIZE(sc7280_intf),
1894     .intf = sc7280_intf,
1895     .vbif_count = ARRAY_SIZE(sdm845_vbif),
1896     .vbif = sdm845_vbif,
1897     .perf = &sc7280_perf_data,
1898     .mdss_irqs = IRQ_SC7280_MASK,
1899 };
1900 
1901 static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
1902     .caps = &qcm2290_dpu_caps,
1903     .mdp_count = ARRAY_SIZE(qcm2290_mdp),
1904     .mdp = qcm2290_mdp,
1905     .ctl_count = ARRAY_SIZE(qcm2290_ctl),
1906     .ctl = qcm2290_ctl,
1907     .sspp_count = ARRAY_SIZE(qcm2290_sspp),
1908     .sspp = qcm2290_sspp,
1909     .mixer_count = ARRAY_SIZE(qcm2290_lm),
1910     .mixer = qcm2290_lm,
1911     .dspp_count = ARRAY_SIZE(qcm2290_dspp),
1912     .dspp = qcm2290_dspp,
1913     .pingpong_count = ARRAY_SIZE(qcm2290_pp),
1914     .pingpong = qcm2290_pp,
1915     .intf_count = ARRAY_SIZE(qcm2290_intf),
1916     .intf = qcm2290_intf,
1917     .vbif_count = ARRAY_SIZE(sdm845_vbif),
1918     .vbif = sdm845_vbif,
1919     .reg_dma_count = 1,
1920     .dma_cfg = &sdm845_regdma,
1921     .perf = &qcm2290_perf_data,
1922     .mdss_irqs = IRQ_SC7180_MASK,
1923 };
1924 
1925 static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
1926     { .hw_rev = DPU_HW_VER_300, .dpu_cfg = &msm8998_dpu_cfg},
1927     { .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg},
1928     { .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg},
1929     { .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg},
1930     { .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg},
1931     { .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg},
1932     { .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg},
1933     { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
1934     { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
1935     { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
1936     { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
1937 };
1938 
1939 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
1940 {
1941     int i;
1942     struct dpu_mdss_cfg *dpu_cfg;
1943 
1944     dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL);
1945     if (!dpu_cfg)
1946         return ERR_PTR(-ENOMEM);
1947 
1948     for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
1949         if (cfg_handler[i].hw_rev == hw_rev)
1950             return cfg_handler[i].dpu_cfg;
1951     }
1952 
1953     DPU_ERROR("unsupported chipset id:%X\n", hw_rev);
1954 
1955     return ERR_PTR(-ENODEV);
1956 }
1957
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