disp/dpu1/dpu_encoder_phys_vid.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
0003  */
0004
0005 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
0006 #include "dpu_encoder_phys.h"
0007 #include "dpu_hw_interrupts.h"
0008 #include "dpu_hw_merge3d.h"
0009 #include "dpu_core_irq.h"
0010 #include "dpu_formats.h"
0011 #include "dpu_trace.h"
0012 #include "disp/msm_disp_snapshot.h"
0013
0014 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
0015         (e) && (e)->parent ? \
0016         (e)->parent->base.id : -1, \
0017         (e) && (e)->hw_intf ? \
0018         (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
0019
0020 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
0021         (e) && (e)->parent ? \
0022         (e)->parent->base.id : -1, \
0023         (e) && (e)->hw_intf ? \
0024         (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
0025
0026 #define to_dpu_encoder_phys_vid(x) \
0027     container_of(x, struct dpu_encoder_phys_vid, base)
0028
0029 static bool dpu_encoder_phys_vid_is_master(
0030         struct dpu_encoder_phys *phys_enc)
0031 {
0032     bool ret = false;
0033
0034     if (phys_enc->split_role != ENC_ROLE_SLAVE)
0035         ret = true;
0036
0037     return ret;
0038 }
0039
0040 static void drm_mode_to_intf_timing_params(
0041         const struct dpu_encoder_phys *phys_enc,
0042         const struct drm_display_mode *mode,
0043         struct intf_timing_params *timing)
0044 {
0045     memset(timing, 0, sizeof(*timing));
0046
0047     if ((mode->htotal < mode->hsync_end)
0048             || (mode->hsync_start < mode->hdisplay)
0049             || (mode->vtotal < mode->vsync_end)
0050             || (mode->vsync_start < mode->vdisplay)
0051             || (mode->hsync_end < mode->hsync_start)
0052             || (mode->vsync_end < mode->vsync_start)) {
0053         DPU_ERROR(
0054             "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
0055                 mode->hsync_start, mode->hsync_end,
0056                 mode->htotal, mode->hdisplay);
0057         DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
0058                 mode->vsync_start, mode->vsync_end,
0059                 mode->vtotal, mode->vdisplay);
0060         return;
0061     }
0062
0063     /*
0064      * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
0065      *  Active Region      Front Porch   Sync   Back Porch
0066      * <-----------------><------------><-----><----------->
0067      * <- [hv]display --->
0068      * <--------- [hv]sync_start ------>
0069      * <----------------- [hv]sync_end ------->
0070      * <---------------------------- [hv]total ------------->
0071      */
0072     timing->width = mode->hdisplay; /* active width */
0073     timing->height = mode->vdisplay;    /* active height */
0074     timing->xres = timing->width;
0075     timing->yres = timing->height;
0076     timing->h_back_porch = mode->htotal - mode->hsync_end;
0077     timing->h_front_porch = mode->hsync_start - mode->hdisplay;
0078     timing->v_back_porch = mode->vtotal - mode->vsync_end;
0079     timing->v_front_porch = mode->vsync_start - mode->vdisplay;
0080     timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
0081     timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
0082     timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
0083     timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
0084     timing->border_clr = 0;
0085     timing->underflow_clr = 0xff;
0086     timing->hsync_skew = mode->hskew;
0087
0088     /* DSI controller cannot handle active-low sync signals. */
0089     if (phys_enc->hw_intf->cap->type == INTF_DSI) {
0090         timing->hsync_polarity = 0;
0091         timing->vsync_polarity = 0;
0092     }
0093
0094     /* for DP/EDP, Shift timings to align it to bottom right */
0095     if (phys_enc->hw_intf->cap->type == INTF_DP) {
0096         timing->h_back_porch += timing->h_front_porch;
0097         timing->h_front_porch = 0;
0098         timing->v_back_porch += timing->v_front_porch;
0099         timing->v_front_porch = 0;
0100     }
0101
0102     timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
0103
0104     /*
0105      * for DP, divide the horizonal parameters by 2 when
0106      * widebus is enabled
0107      */
0108     if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
0109         timing->width = timing->width >> 1;
0110         timing->xres = timing->xres >> 1;
0111         timing->h_back_porch = timing->h_back_porch >> 1;
0112         timing->h_front_porch = timing->h_front_porch >> 1;
0113         timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
0114     }
0115 }
0116
0117 static u32 get_horizontal_total(const struct intf_timing_params *timing)
0118 {
0119     u32 active = timing->xres;
0120     u32 inactive =
0121         timing->h_back_porch + timing->h_front_porch +
0122         timing->hsync_pulse_width;
0123     return active + inactive;
0124 }
0125
0126 static u32 get_vertical_total(const struct intf_timing_params *timing)
0127 {
0128     u32 active = timing->yres;
0129     u32 inactive =
0130         timing->v_back_porch + timing->v_front_porch +
0131         timing->vsync_pulse_width;
0132     return active + inactive;
0133 }
0134
0135 /*
0136  * programmable_fetch_get_num_lines:
0137  *  Number of fetch lines in vertical front porch
0138  * @timing: Pointer to the intf timing information for the requested mode
0139  *
0140  * Returns the number of fetch lines in vertical front porch at which mdp
0141  * can start fetching the next frame.
0142  *
0143  * Number of needed prefetch lines is anything that cannot be absorbed in the
0144  * start of frame time (back porch + vsync pulse width).
0145  *
0146  * Some panels have very large VFP, however we only need a total number of
0147  * lines based on the chip worst case latencies.
0148  */
0149 static u32 programmable_fetch_get_num_lines(
0150         struct dpu_encoder_phys *phys_enc,
0151         const struct intf_timing_params *timing)
0152 {
0153     u32 worst_case_needed_lines =
0154         phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
0155     u32 start_of_frame_lines =
0156         timing->v_back_porch + timing->vsync_pulse_width;
0157     u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
0158     u32 actual_vfp_lines = 0;
0159
0160     /* Fetch must be outside active lines, otherwise undefined. */
0161     if (start_of_frame_lines >= worst_case_needed_lines) {
0162         DPU_DEBUG_VIDENC(phys_enc,
0163                 "prog fetch is not needed, large vbp+vsw\n");
0164         actual_vfp_lines = 0;
0165     } else if (timing->v_front_porch < needed_vfp_lines) {
0166         /* Warn fetch needed, but not enough porch in panel config */
0167         pr_warn_once
0168             ("low vbp+vfp may lead to perf issues in some cases\n");
0169         DPU_DEBUG_VIDENC(phys_enc,
0170                 "less vfp than fetch req, using entire vfp\n");
0171         actual_vfp_lines = timing->v_front_porch;
0172     } else {
0173         DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
0174         actual_vfp_lines = needed_vfp_lines;
0175     }
0176
0177     DPU_DEBUG_VIDENC(phys_enc,
0178         "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
0179         timing->v_front_porch, timing->v_back_porch,
0180         timing->vsync_pulse_width);
0181     DPU_DEBUG_VIDENC(phys_enc,
0182         "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
0183         worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
0184
0185     return actual_vfp_lines;
0186 }
0187
0188 /*
0189  * programmable_fetch_config: Programs HW to prefetch lines by offsetting
0190  *  the start of fetch into the vertical front porch for cases where the
0191  *  vsync pulse width and vertical back porch time is insufficient
0192  *
0193  *  Gets # of lines to pre-fetch, then calculate VSYNC counter value.
0194  *  HW layer requires VSYNC counter of first pixel of tgt VFP line.
0195  *
0196  * @timing: Pointer to the intf timing information for the requested mode
0197  */
0198 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
0199                       const struct intf_timing_params *timing)
0200 {
0201     struct intf_prog_fetch f = { 0 };
0202     u32 vfp_fetch_lines = 0;
0203     u32 horiz_total = 0;
0204     u32 vert_total = 0;
0205     u32 vfp_fetch_start_vsync_counter = 0;
0206     unsigned long lock_flags;
0207
0208     if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
0209         return;
0210
0211     vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
0212     if (vfp_fetch_lines) {
0213         vert_total = get_vertical_total(timing);
0214         horiz_total = get_horizontal_total(timing);
0215         vfp_fetch_start_vsync_counter =
0216             (vert_total - vfp_fetch_lines) * horiz_total + 1;
0217         f.enable = 1;
0218         f.fetch_start = vfp_fetch_start_vsync_counter;
0219     }
0220
0221     DPU_DEBUG_VIDENC(phys_enc,
0222         "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
0223         vfp_fetch_lines, vfp_fetch_start_vsync_counter);
0224
0225     spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
0226     phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
0227     spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
0228 }
0229
0230 static void dpu_encoder_phys_vid_setup_timing_engine(
0231         struct dpu_encoder_phys *phys_enc)
0232 {
0233     struct drm_display_mode mode;
0234     struct intf_timing_params timing_params = { 0 };
0235     const struct dpu_format *fmt = NULL;
0236     u32 fmt_fourcc = DRM_FORMAT_RGB888;
0237     unsigned long lock_flags;
0238     struct dpu_hw_intf_cfg intf_cfg = { 0 };
0239
0240     if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {
0241         DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);
0242         return;
0243     }
0244
0245     mode = phys_enc->cached_mode;
0246     if (!phys_enc->hw_intf->ops.setup_timing_gen) {
0247         DPU_ERROR("timing engine setup is not supported\n");
0248         return;
0249     }
0250
0251     DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
0252     drm_mode_debug_printmodeline(&mode);
0253
0254     if (phys_enc->split_role != ENC_ROLE_SOLO) {
0255         mode.hdisplay >>= 1;
0256         mode.htotal >>= 1;
0257         mode.hsync_start >>= 1;
0258         mode.hsync_end >>= 1;
0259
0260         DPU_DEBUG_VIDENC(phys_enc,
0261             "split_role %d, halve horizontal %d %d %d %d\n",
0262             phys_enc->split_role,
0263             mode.hdisplay, mode.htotal,
0264             mode.hsync_start, mode.hsync_end);
0265     }
0266
0267     drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
0268
0269     fmt = dpu_get_dpu_format(fmt_fourcc);
0270     DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
0271
0272     intf_cfg.intf = phys_enc->hw_intf->idx;
0273     intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
0274     intf_cfg.stream_sel = 0; /* Don't care value for video mode */
0275     intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
0276     if (phys_enc->hw_pp->merge_3d)
0277         intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
0278
0279     spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
0280     phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
0281             &timing_params, fmt);
0282     phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
0283
0284     /* setup which pp blk will connect to this intf */
0285     if (phys_enc->hw_intf->ops.bind_pingpong_blk)
0286         phys_enc->hw_intf->ops.bind_pingpong_blk(
0287                 phys_enc->hw_intf,
0288                 true,
0289                 phys_enc->hw_pp->idx);
0290
0291     if (phys_enc->hw_pp->merge_3d)
0292         phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
0293
0294     spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
0295
0296     programmable_fetch_config(phys_enc, &timing_params);
0297 }
0298
0299 static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
0300 {
0301     struct dpu_encoder_phys *phys_enc = arg;
0302     struct dpu_hw_ctl *hw_ctl;
0303     unsigned long lock_flags;
0304     u32 flush_register = 0;
0305
0306     hw_ctl = phys_enc->hw_ctl;
0307
0308     DPU_ATRACE_BEGIN("vblank_irq");
0309
0310     if (phys_enc->parent_ops->handle_vblank_virt)
0311         phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
0312                 phys_enc);
0313
0314     atomic_read(&phys_enc->pending_kickoff_cnt);
0315
0316     /*
0317      * only decrement the pending flush count if we've actually flushed
0318      * hardware. due to sw irq latency, vblank may have already happened
0319      * so we need to double-check with hw that it accepted the flush bits
0320      */
0321     spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
0322     if (hw_ctl->ops.get_flush_register)
0323         flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
0324
0325     if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
0326         atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
0327     spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
0328
0329     /* Signal any waiting atomic commit thread */
0330     wake_up_all(&phys_enc->pending_kickoff_wq);
0331
0332     phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc,
0333             DPU_ENCODER_FRAME_EVENT_DONE);
0334
0335     DPU_ATRACE_END("vblank_irq");
0336 }
0337
0338 static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
0339 {
0340     struct dpu_encoder_phys *phys_enc = arg;
0341
0342     if (phys_enc->parent_ops->handle_underrun_virt)
0343         phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
0344             phys_enc);
0345 }
0346
0347 static bool dpu_encoder_phys_vid_needs_single_flush(
0348         struct dpu_encoder_phys *phys_enc)
0349 {
0350     return phys_enc->split_role != ENC_ROLE_SOLO;
0351 }
0352
0353 static void dpu_encoder_phys_vid_atomic_mode_set(
0354         struct dpu_encoder_phys *phys_enc,
0355         struct drm_crtc_state *crtc_state,
0356         struct drm_connector_state *conn_state)
0357 {
0358     phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
0359
0360     phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
0361 }
0362
0363 static int dpu_encoder_phys_vid_control_vblank_irq(
0364         struct dpu_encoder_phys *phys_enc,
0365         bool enable)
0366 {
0367     int ret = 0;
0368     int refcount;
0369
0370     refcount = atomic_read(&phys_enc->vblank_refcount);
0371
0372     /* Slave encoders don't report vblank */
0373     if (!dpu_encoder_phys_vid_is_master(phys_enc))
0374         goto end;
0375
0376     /* protect against negative */
0377     if (!enable && refcount == 0) {
0378         ret = -EINVAL;
0379         goto end;
0380     }
0381
0382     DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
0383               atomic_read(&phys_enc->vblank_refcount));
0384
0385     if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
0386         ret = dpu_core_irq_register_callback(phys_enc->dpu_kms,
0387                 phys_enc->irq[INTR_IDX_VSYNC],
0388                 dpu_encoder_phys_vid_vblank_irq,
0389                 phys_enc);
0390     else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
0391         ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
0392                 phys_enc->irq[INTR_IDX_VSYNC]);
0393
0394 end:
0395     if (ret) {
0396         DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
0397               DRMID(phys_enc->parent),
0398               phys_enc->hw_intf->idx - INTF_0, ret, enable,
0399               refcount);
0400     }
0401     return ret;
0402 }
0403
0404 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
0405 {
0406     struct dpu_hw_ctl *ctl;
0407
0408     ctl = phys_enc->hw_ctl;
0409
0410     DPU_DEBUG_VIDENC(phys_enc, "\n");
0411
0412     if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
0413         return;
0414
0415     dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
0416
0417     dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
0418
0419     /*
0420      * For single flush cases (dual-ctl or pp-split), skip setting the
0421      * flush bit for the slave intf, since both intfs use same ctl
0422      * and HW will only flush the master.
0423      */
0424     if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
0425         !dpu_encoder_phys_vid_is_master(phys_enc))
0426         goto skip_flush;
0427
0428     ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
0429     if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
0430         ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
0431
0432 skip_flush:
0433     DPU_DEBUG_VIDENC(phys_enc,
0434         "update pending flush ctl %d intf %d\n",
0435         ctl->idx - CTL_0, phys_enc->hw_intf->idx);
0436
0437     atomic_set(&phys_enc->underrun_cnt, 0);
0438
0439     /* ctl_flush & timing engine enable will be triggered by framework */
0440     if (phys_enc->enable_state == DPU_ENC_DISABLED)
0441         phys_enc->enable_state = DPU_ENC_ENABLING;
0442 }
0443
0444 static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)
0445 {
0446     DPU_DEBUG_VIDENC(phys_enc, "\n");
0447     kfree(phys_enc);
0448 }
0449
0450 static int dpu_encoder_phys_vid_wait_for_vblank(
0451         struct dpu_encoder_phys *phys_enc)
0452 {
0453     struct dpu_encoder_wait_info wait_info;
0454     int ret;
0455
0456     wait_info.wq = &phys_enc->pending_kickoff_wq;
0457     wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
0458     wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
0459
0460     if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
0461         return 0;
0462     }
0463
0464     /* Wait for kickoff to complete */
0465     ret = dpu_encoder_helper_wait_for_irq(phys_enc,
0466             phys_enc->irq[INTR_IDX_VSYNC],
0467             dpu_encoder_phys_vid_vblank_irq,
0468             &wait_info);
0469
0470     if (ret == -ETIMEDOUT) {
0471         dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
0472     }
0473
0474     return ret;
0475 }
0476
0477 static int dpu_encoder_phys_vid_wait_for_commit_done(
0478         struct dpu_encoder_phys *phys_enc)
0479 {
0480     struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
0481     int ret;
0482
0483     if (!hw_ctl)
0484         return 0;
0485
0486     ret = wait_event_timeout(phys_enc->pending_kickoff_wq,
0487         (hw_ctl->ops.get_flush_register(hw_ctl) == 0),
0488         msecs_to_jiffies(50));
0489     if (ret <= 0) {
0490         DPU_ERROR("vblank timeout\n");
0491         return -ETIMEDOUT;
0492     }
0493
0494     return 0;
0495 }
0496
0497 static void dpu_encoder_phys_vid_prepare_for_kickoff(
0498         struct dpu_encoder_phys *phys_enc)
0499 {
0500     struct dpu_hw_ctl *ctl;
0501     int rc;
0502     struct drm_encoder *drm_enc;
0503
0504     drm_enc = phys_enc->parent;
0505
0506     ctl = phys_enc->hw_ctl;
0507     if (!ctl->ops.wait_reset_status)
0508         return;
0509
0510     /*
0511      * hw supports hardware initiated ctl reset, so before we kickoff a new
0512      * frame, need to check and wait for hw initiated ctl reset completion
0513      */
0514     rc = ctl->ops.wait_reset_status(ctl);
0515     if (rc) {
0516         DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
0517                 ctl->idx, rc);
0518         msm_disp_snapshot_state(drm_enc->dev);
0519         dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
0520                 phys_enc->irq[INTR_IDX_VSYNC]);
0521     }
0522 }
0523
0524 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
0525 {
0526     unsigned long lock_flags;
0527     int ret;
0528
0529     if (!phys_enc->parent || !phys_enc->parent->dev) {
0530         DPU_ERROR("invalid encoder/device\n");
0531         return;
0532     }
0533
0534     if (!phys_enc->hw_intf) {
0535         DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
0536                 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
0537         return;
0538     }
0539
0540     if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
0541         return;
0542
0543     if (phys_enc->enable_state == DPU_ENC_DISABLED) {
0544         DPU_ERROR("already disabled\n");
0545         return;
0546     }
0547
0548     spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
0549     phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
0550     if (dpu_encoder_phys_vid_is_master(phys_enc))
0551         dpu_encoder_phys_inc_pending(phys_enc);
0552     spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
0553
0554     /*
0555      * Wait for a vsync so we know the ENABLE=0 latched before
0556      * the (connector) source of the vsync's gets disabled,
0557      * otherwise we end up in a funny state if we re-enable
0558      * before the disable latches, which results that some of
0559      * the settings changes for the new modeset (like new
0560      * scanout buffer) don't latch properly..
0561      */
0562     if (dpu_encoder_phys_vid_is_master(phys_enc)) {
0563         ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
0564         if (ret) {
0565             atomic_set(&phys_enc->pending_kickoff_cnt, 0);
0566             DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
0567                   DRMID(phys_enc->parent),
0568                   phys_enc->hw_intf->idx - INTF_0, ret);
0569         }
0570     }
0571
0572     phys_enc->enable_state = DPU_ENC_DISABLED;
0573 }
0574
0575 static void dpu_encoder_phys_vid_handle_post_kickoff(
0576         struct dpu_encoder_phys *phys_enc)
0577 {
0578     unsigned long lock_flags;
0579
0580     /*
0581      * Video mode must flush CTL before enabling timing engine
0582      * Video encoders need to turn on their interfaces now
0583      */
0584     if (phys_enc->enable_state == DPU_ENC_ENABLING) {
0585         trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
0586                     phys_enc->hw_intf->idx - INTF_0);
0587         spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
0588         phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
0589         spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
0590         phys_enc->enable_state = DPU_ENC_ENABLED;
0591     }
0592 }
0593
0594 static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
0595         bool enable)
0596 {
0597     int ret;
0598
0599     trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
0600                 phys_enc->hw_intf->idx - INTF_0,
0601                 enable,
0602                 atomic_read(&phys_enc->vblank_refcount));
0603
0604     if (enable) {
0605         ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
0606         if (WARN_ON(ret))
0607             return;
0608
0609         dpu_core_irq_register_callback(phys_enc->dpu_kms,
0610                 phys_enc->irq[INTR_IDX_UNDERRUN],
0611                 dpu_encoder_phys_vid_underrun_irq,
0612                 phys_enc);
0613     } else {
0614         dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
0615         dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
0616                 phys_enc->irq[INTR_IDX_UNDERRUN]);
0617     }
0618 }
0619
0620 static int dpu_encoder_phys_vid_get_line_count(
0621         struct dpu_encoder_phys *phys_enc)
0622 {
0623     if (!dpu_encoder_phys_vid_is_master(phys_enc))
0624         return -EINVAL;
0625
0626     if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
0627         return -EINVAL;
0628
0629     return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
0630 }
0631
0632 static int dpu_encoder_phys_vid_get_frame_count(
0633         struct dpu_encoder_phys *phys_enc)
0634 {
0635     struct intf_status s = {0};
0636     u32 fetch_start = 0;
0637     struct drm_display_mode mode = phys_enc->cached_mode;
0638
0639     if (!dpu_encoder_phys_vid_is_master(phys_enc))
0640         return -EINVAL;
0641
0642     if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status)
0643         return -EINVAL;
0644
0645     phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s);
0646
0647     if (s.is_prog_fetch_en && s.is_en) {
0648         fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay);
0649         if ((s.line_count > fetch_start) &&
0650             (s.line_count <= mode.vtotal))
0651             return s.frame_count + 1;
0652     }
0653
0654     return s.frame_count;
0655 }
0656
0657 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
0658 {
0659     ops->is_master = dpu_encoder_phys_vid_is_master;
0660     ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;
0661     ops->enable = dpu_encoder_phys_vid_enable;
0662     ops->disable = dpu_encoder_phys_vid_disable;
0663     ops->destroy = dpu_encoder_phys_vid_destroy;
0664     ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
0665     ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
0666     ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
0667     ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
0668     ops->irq_control = dpu_encoder_phys_vid_irq_control;
0669     ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
0670     ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
0671     ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
0672     ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
0673     ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count;
0674 }
0675
0676 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
0677         struct dpu_enc_phys_init_params *p)
0678 {
0679     struct dpu_encoder_phys *phys_enc = NULL;
0680     int i;
0681
0682     if (!p) {
0683         DPU_ERROR("failed to create encoder due to invalid parameter\n");
0684         return ERR_PTR(-EINVAL);
0685     }
0686
0687     phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);
0688     if (!phys_enc) {
0689         DPU_ERROR("failed to create encoder due to memory allocation error\n");
0690         return ERR_PTR(-ENOMEM);
0691     }
0692
0693     phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
0694     phys_enc->intf_idx = p->intf_idx;
0695
0696     DPU_DEBUG_VIDENC(phys_enc, "\n");
0697
0698     dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
0699     phys_enc->parent = p->parent;
0700     phys_enc->parent_ops = p->parent_ops;
0701     phys_enc->dpu_kms = p->dpu_kms;
0702     phys_enc->split_role = p->split_role;
0703     phys_enc->intf_mode = INTF_MODE_VIDEO;
0704     phys_enc->enc_spinlock = p->enc_spinlock;
0705     for (i = 0; i < ARRAY_SIZE(phys_enc->irq); i++)
0706         phys_enc->irq[i] = -EINVAL;
0707
0708     atomic_set(&phys_enc->vblank_refcount, 0);
0709     atomic_set(&phys_enc->pending_kickoff_cnt, 0);
0710     init_waitqueue_head(&phys_enc->pending_kickoff_wq);
0711     phys_enc->enable_state = DPU_ENC_DISABLED;
0712
0713     DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx);
0714
0715     return phys_enc;
0716 }