disp/dpu1/dpu_encoder.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
0004  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0005  * Copyright (C) 2013 Red Hat
0006  * Author: Rob Clark <robdclark@gmail.com>
0007  */
0008
0009 #ifndef __DPU_ENCODER_H__
0010 #define __DPU_ENCODER_H__
0011
0012 #include <drm/drm_crtc.h>
0013 #include "dpu_hw_mdss.h"
0014
0015 #define DPU_ENCODER_FRAME_EVENT_DONE            BIT(0)
0016 #define DPU_ENCODER_FRAME_EVENT_ERROR           BIT(1)
0017 #define DPU_ENCODER_FRAME_EVENT_PANEL_DEAD      BIT(2)
0018 #define DPU_ENCODER_FRAME_EVENT_IDLE            BIT(3)
0019
0020 #define IDLE_TIMEOUT    (66 - 16/2)
0021
0022 /**
0023  * struct msm_display_info - defines display properties
0024  * @intf_type:          DRM_MODE_ENCODER_ type
0025  * @num_of_h_tiles:     Number of horizontal tiles in case of split interface
0026  * @h_tile_instance:    Controller instance used per tile. Number of elements is
0027  *                      based on num_of_h_tiles
0028  * @is_cmd_mode     Boolean to indicate if the CMD mode is requested
0029  * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
0030  *               used instead of panel TE in cmd mode panels
0031  * @dsc:        DSC configuration data for DSC-enabled displays
0032  */
0033 struct msm_display_info {
0034     int intf_type;
0035     uint32_t num_of_h_tiles;
0036     uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
0037     bool is_cmd_mode;
0038     bool is_te_using_watchdog_timer;
0039     struct msm_display_dsc_config *dsc;
0040 };
0041
0042 /**
0043  * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to
0044  * @encoder:    encoder pointer
0045  * @crtc:   crtc pointer
0046  */
0047 void dpu_encoder_assign_crtc(struct drm_encoder *encoder,
0048                  struct drm_crtc *crtc);
0049
0050 /**
0051  * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if
0052  *  the encoder is assigned to the given crtc
0053  * @encoder:    encoder pointer
0054  * @crtc:   crtc pointer
0055  * @enable: true if vblank should be enabled
0056  */
0057 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *encoder,
0058                     struct drm_crtc *crtc, bool enable);
0059
0060 /**
0061  * dpu_encoder_register_frame_event_callback - provide callback to encoder that
0062  *  will be called after the request is complete, or other events.
0063  * @encoder:    encoder pointer
0064  * @cb:     callback pointer, provide NULL to deregister
0065  * @data:   user data provided to callback
0066  */
0067 void dpu_encoder_register_frame_event_callback(struct drm_encoder *encoder,
0068         void (*cb)(void *, u32), void *data);
0069
0070 /**
0071  * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl
0072  *  path (i.e. ctl flush and start) at next appropriate time.
0073  *  Immediately: if no previous commit is outstanding.
0074  *  Delayed: Block until next trigger can be issued.
0075  * @encoder:    encoder pointer
0076  */
0077 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder);
0078
0079 /**
0080  * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous
0081  *        kickoff and trigger the ctl prepare progress for command mode display.
0082  * @encoder:    encoder pointer
0083  */
0084 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder);
0085
0086 /**
0087  * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path
0088  *  (i.e. ctl flush and start) immediately.
0089  * @encoder:    encoder pointer
0090  */
0091 void dpu_encoder_kickoff(struct drm_encoder *encoder);
0092
0093 /**
0094  * dpu_encoder_wakeup_time - get the time of the next vsync
0095  */
0096 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time);
0097
0098 /**
0099  * dpu_encoder_wait_for_event - Waits for encoder events
0100  * @encoder:    encoder pointer
0101  * @event:      event to wait for
0102  * MSM_ENC_COMMIT_DONE -  Wait for hardware to have flushed the current pending
0103  *                        frames to hardware at a vblank or ctl_start
0104  *                        Encoders will map this differently depending on the
0105  *                        panel type.
0106  *                    vid mode -> vsync_irq
0107  *                        cmd mode -> ctl_start
0108  * MSM_ENC_TX_COMPLETE -  Wait for the hardware to transfer all the pixels to
0109  *                        the panel. Encoders will map this differently
0110  *                        depending on the panel type.
0111  *                        vid mode -> vsync_irq
0112  *                        cmd mode -> pp_done
0113  * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
0114  */
0115 int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder,
0116                         enum msm_event_wait event);
0117
0118 /*
0119  * dpu_encoder_get_intf_mode - get interface mode of the given encoder
0120  * @encoder: Pointer to drm encoder object
0121  */
0122 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder);
0123
0124 /**
0125  * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs
0126  * @encoder:    encoder pointer
0127  */
0128 void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder);
0129
0130 /**
0131  * dpu_encoder_init - initialize virtual encoder object
0132  * @dev:        Pointer to drm device structure
0133  * @disp_info:  Pointer to display information structure
0134  * Returns:     Pointer to newly created drm encoder
0135  */
0136 struct drm_encoder *dpu_encoder_init(
0137         struct drm_device *dev,
0138         int drm_enc_mode);
0139
0140 /**
0141  * dpu_encoder_setup - setup dpu_encoder for the display probed
0142  * @dev:        Pointer to drm device structure
0143  * @enc:        Pointer to the drm_encoder
0144  * @disp_info:  Pointer to the display info
0145  */
0146 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
0147         struct msm_display_info *disp_info);
0148
0149 /**
0150  * dpu_encoder_prepare_commit - prepare encoder at the very beginning of an
0151  *  atomic commit, before any registers are written
0152  * @drm_enc:    Pointer to previously created drm encoder structure
0153  */
0154 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc);
0155
0156 /**
0157  * dpu_encoder_set_idle_timeout - set the idle timeout for video
0158  *                    and command mode encoders.
0159  * @drm_enc:    Pointer to previously created drm encoder structure
0160  * @idle_timeout:    idle timeout duration in milliseconds
0161  */
0162 void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc,
0163                             u32 idle_timeout);
0164 /**
0165  * dpu_encoder_get_linecount - get interface line count for the encoder.
0166  * @drm_enc:    Pointer to previously created drm encoder structure
0167  */
0168 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc);
0169
0170 /**
0171  * dpu_encoder_get_vsync_count - get vsync count for the encoder.
0172  * @drm_enc:    Pointer to previously created drm encoder structure
0173  */
0174 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
0175
0176 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
0177
0178 /**
0179  * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
0180  *  in virtual encoder that can collect CRC values
0181  * @drm_enc:    Pointer to previously created drm encoder structure
0182  * Returns:     Number of physical encoders for given drm encoder
0183  */
0184 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc);
0185
0186 /**
0187  * dpu_encoder_setup_misr - enable misr calculations
0188  * @drm_enc:    Pointer to previously created drm encoder structure
0189  */
0190 void dpu_encoder_setup_misr(const struct drm_encoder *drm_encoder);
0191
0192 /**
0193  * dpu_encoder_get_crc - get the crc value from interface blocks
0194  * @drm_enc:    Pointer to previously created drm encoder structure
0195  * Returns:     0 on success, error otherwise
0196  */
0197 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos);
0198
0199 /**
0200  * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
0201  * @drm_enc:    Pointer to previously created drm encoder structure
0202  */
0203 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc);
0204
0205 /**
0206  * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder.
0207  * @drm_enc:    Pointer to previously created drm encoder structure
0208  * @job:        Pointer to the current drm writeback job
0209  */
0210 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
0211         struct drm_writeback_job *job);
0212
0213 /**
0214  * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder.
0215  * @drm_enc:    Pointer to previously created drm encoder structure
0216  * @job:        Pointer to the current drm writeback job
0217  */
0218 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
0219         struct drm_writeback_job *job);
0220
0221 /**
0222  * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit.
0223  * @drm_enc:    Pointer to drm encoder structure
0224  */
0225 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc);
0226
0227 #endif /* __DPU_ENCODER_H__ */