disp/dpu1/dpu_crtc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
0004  * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
0005  * Copyright (C) 2013 Red Hat
0006  * Author: Rob Clark <robdclark@gmail.com>
0007  */
0008
0009 #ifndef _DPU_CRTC_H_
0010 #define _DPU_CRTC_H_
0011
0012 #include <linux/kthread.h>
0013 #include <drm/drm_crtc.h>
0014 #include "dpu_kms.h"
0015 #include "dpu_core_perf.h"
0016
0017 #define DPU_CRTC_NAME_SIZE  12
0018
0019 /* define the maximum number of in-flight frame events */
0020 #define DPU_CRTC_FRAME_EVENT_SIZE   4
0021
0022 /**
0023  * enum dpu_crtc_client_type: crtc client type
0024  * @RT_CLIENT:  RealTime client like video/cmd mode display
0025  *              voting through apps rsc
0026  * @NRT_CLIENT: Non-RealTime client like WB display
0027  *              voting through apps rsc
0028  */
0029 enum dpu_crtc_client_type {
0030     RT_CLIENT,
0031     NRT_CLIENT,
0032 };
0033
0034 /**
0035  * enum dpu_crtc_smmu_state:    smmu state
0036  * @ATTACHED:    all the context banks are attached.
0037  * @DETACHED:    all the context banks are detached.
0038  * @ATTACH_ALL_REQ:  transient state of attaching context banks.
0039  * @DETACH_ALL_REQ:  transient state of detaching context banks.
0040  */
0041 enum dpu_crtc_smmu_state {
0042     ATTACHED = 0,
0043     DETACHED,
0044     ATTACH_ALL_REQ,
0045     DETACH_ALL_REQ,
0046 };
0047
0048 /**
0049  * enum dpu_crtc_smmu_state_transition_type: state transition type
0050  * @NONE: no pending state transitions
0051  * @PRE_COMMIT: state transitions should be done before processing the commit
0052  * @POST_COMMIT: state transitions to be done after processing the commit.
0053  */
0054 enum dpu_crtc_smmu_state_transition_type {
0055     NONE,
0056     PRE_COMMIT,
0057     POST_COMMIT
0058 };
0059
0060 /**
0061  * struct dpu_crtc_smmu_state_data: stores the smmu state and transition type
0062  * @state: current state of smmu context banks
0063  * @transition_type: transition request type
0064  * @transition_error: whether there is error while transitioning the state
0065  */
0066 struct dpu_crtc_smmu_state_data {
0067     uint32_t state;
0068     uint32_t transition_type;
0069     uint32_t transition_error;
0070 };
0071
0072 /**
0073  * enum dpu_crtc_crc_source: CRC source
0074  * @DPU_CRTC_CRC_SOURCE_NONE: no source set
0075  * @DPU_CRTC_CRC_SOURCE_LAYER_MIXER: CRC in layer mixer
0076  * @DPU_CRTC_CRC_SOURCE_ENCODER: CRC in encoder
0077  * @DPU_CRTC_CRC_SOURCE_INVALID: Invalid source
0078  */
0079 enum dpu_crtc_crc_source {
0080     DPU_CRTC_CRC_SOURCE_NONE = 0,
0081     DPU_CRTC_CRC_SOURCE_LAYER_MIXER,
0082     DPU_CRTC_CRC_SOURCE_ENCODER,
0083     DPU_CRTC_CRC_SOURCE_MAX,
0084     DPU_CRTC_CRC_SOURCE_INVALID = -1
0085 };
0086
0087 /**
0088  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
0089  * @hw_lm:  LM HW Driver context
0090  * @lm_ctl: CTL Path HW driver context
0091  * @lm_dspp:    DSPP HW driver context
0092  * @mixer_op_mode:  mixer blending operation mode
0093  * @flush_mask: mixer flush mask for ctl, mixer and pipe
0094  */
0095 struct dpu_crtc_mixer {
0096     struct dpu_hw_mixer *hw_lm;
0097     struct dpu_hw_ctl *lm_ctl;
0098     struct dpu_hw_dspp *hw_dspp;
0099     u32 mixer_op_mode;
0100     u32 flush_mask;
0101 };
0102
0103 /**
0104  * struct dpu_crtc_frame_event: stores crtc frame event for crtc processing
0105  * @work:   base work structure
0106  * @crtc:   Pointer to crtc handling this event
0107  * @list:   event list
0108  * @ts:     timestamp at queue entry
0109  * @event:  event identifier
0110  */
0111 struct dpu_crtc_frame_event {
0112     struct kthread_work work;
0113     struct drm_crtc *crtc;
0114     struct list_head list;
0115     ktime_t ts;
0116     u32 event;
0117 };
0118
0119 /*
0120  * Maximum number of free event structures to cache
0121  */
0122 #define DPU_CRTC_MAX_EVENT_COUNT    16
0123
0124 /**
0125  * struct dpu_crtc - virtualized CRTC data structure
0126  * @base          : Base drm crtc structure
0127  * @name          : ASCII description of this crtc
0128  * @event         : Pointer to last received drm vblank event. If there is a
0129  *                  pending vblank event, this will be non-null.
0130  * @vsync_count   : Running count of received vsync events
0131  * @drm_requested_vblank : Whether vblanks have been enabled in the encoder
0132  * @property_info : Opaque structure for generic property support
0133  * @property_defaults : Array of default values for generic property support
0134  * @vblank_cb_count : count of vblank callback since last reset
0135  * @play_count    : frame count between crtc enable and disable
0136  * @vblank_cb_time  : ktime at vblank count reset
0137  * @enabled       : whether the DPU CRTC is currently enabled. updated in the
0138  *                  commit-thread, not state-swap time which is earlier, so
0139  *                  safe to make decisions on during VBLANK on/off work
0140  * @feature_list  : list of color processing features supported on a crtc
0141  * @active_list   : list of color processing features are active
0142  * @dirty_list    : list of color processing features are dirty
0143  * @ad_dirty: list containing ad properties that are dirty
0144  * @ad_active: list containing ad properties that are active
0145  * @frame_pending : Whether or not an update is pending
0146  * @frame_events  : static allocation of in-flight frame events
0147  * @frame_event_list : available frame event list
0148  * @spin_lock     : spin lock for frame event, transaction status, etc...
0149  * @frame_done_comp    : for frame_event_done synchronization
0150  * @event_thread  : Pointer to event handler thread
0151  * @event_worker  : Event worker queue
0152  * @event_lock    : Spinlock around event handling code
0153  * @phandle: Pointer to power handler
0154  * @cur_perf      : current performance committed to clock/bandwidth driver
0155  * @crc_source    : CRC source
0156  */
0157 struct dpu_crtc {
0158     struct drm_crtc base;
0159     char name[DPU_CRTC_NAME_SIZE];
0160
0161     struct drm_pending_vblank_event *event;
0162     u32 vsync_count;
0163
0164     u32 vblank_cb_count;
0165     u64 play_count;
0166     ktime_t vblank_cb_time;
0167     bool enabled;
0168
0169     struct list_head feature_list;
0170     struct list_head active_list;
0171     struct list_head dirty_list;
0172     struct list_head ad_dirty;
0173     struct list_head ad_active;
0174
0175     atomic_t frame_pending;
0176     struct dpu_crtc_frame_event frame_events[DPU_CRTC_FRAME_EVENT_SIZE];
0177     struct list_head frame_event_list;
0178     spinlock_t spin_lock;
0179     struct completion frame_done_comp;
0180
0181     /* for handling internal event thread */
0182     spinlock_t event_lock;
0183
0184     struct dpu_core_perf_params cur_perf;
0185
0186     struct dpu_crtc_smmu_state_data smmu_state;
0187 };
0188
0189 #define to_dpu_crtc(x) container_of(x, struct dpu_crtc, base)
0190
0191 /**
0192  * struct dpu_crtc_state - dpu container for atomic crtc state
0193  * @base: Base drm crtc state structure
0194  * @bw_control    : true if bw/clk controlled by core bw/clk properties
0195  * @bw_split_vote : true if bw controlled by llcc/dram bw properties
0196  * @lm_bounds     : LM boundaries based on current mode full resolution, no ROI.
0197  *                  Origin top left of CRTC.
0198  * @property_state: Local storage for msm_prop properties
0199  * @property_values: Current crtc property values
0200  * @input_fence_timeout_ns : Cached input fence timeout, in ns
0201  * @new_perf: new performance state being requested
0202  * @num_mixers    : Number of mixers in use
0203  * @mixers        : List of active mixers
0204  * @num_ctls      : Number of ctl paths in use
0205  * @hw_ctls       : List of active ctl paths
0206  * @crc_source    : CRC source
0207  * @crc_frame_skip_count: Number of frames skipped before getting CRC
0208  */
0209 struct dpu_crtc_state {
0210     struct drm_crtc_state base;
0211
0212     bool bw_control;
0213     bool bw_split_vote;
0214     struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
0215
0216     uint64_t input_fence_timeout_ns;
0217
0218     struct dpu_core_perf_params new_perf;
0219
0220     /* HW Resources reserved for the crtc */
0221     u32 num_mixers;
0222     struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
0223
0224     u32 num_ctls;
0225     struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
0226
0227     enum dpu_crtc_crc_source crc_source;
0228     int crc_frame_skip_count;
0229 };
0230
0231 #define to_dpu_crtc_state(x) \
0232     container_of(x, struct dpu_crtc_state, base)
0233
0234 /**
0235  * dpu_crtc_frame_pending - retun the number of pending frames
0236  * @crtc: Pointer to drm crtc object
0237  */
0238 static inline int dpu_crtc_frame_pending(struct drm_crtc *crtc)
0239 {
0240     return crtc ? atomic_read(&to_dpu_crtc(crtc)->frame_pending) : -EINVAL;
0241 }
0242
0243 /**
0244  * dpu_crtc_vblank - enable or disable vblanks for this crtc
0245  * @crtc: Pointer to drm crtc object
0246  * @en: true to enable vblanks, false to disable
0247  */
0248 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en);
0249
0250 /**
0251  * dpu_crtc_vblank_callback - called on vblank irq, issues completion events
0252  * @crtc: Pointer to drm crtc object
0253  */
0254 void dpu_crtc_vblank_callback(struct drm_crtc *crtc);
0255
0256 /**
0257  * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc
0258  * @crtc: Pointer to drm crtc object
0259  */
0260 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc);
0261
0262 /**
0263  * dpu_crtc_complete_commit - callback signalling completion of current commit
0264  * @crtc: Pointer to drm crtc object
0265  */
0266 void dpu_crtc_complete_commit(struct drm_crtc *crtc);
0267
0268 /**
0269  * dpu_crtc_init - create a new crtc object
0270  * @dev: dpu device
0271  * @plane: base plane
0272  * @cursor: cursor plane
0273  * @Return: new crtc object or error
0274  */
0275 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
0276                    struct drm_plane *cursor);
0277
0278 /**
0279  * dpu_crtc_register_custom_event - api for enabling/disabling crtc event
0280  * @kms: Pointer to dpu_kms
0281  * @crtc_drm: Pointer to crtc object
0282  * @event: Event that client is interested
0283  * @en: Flag to enable/disable the event
0284  */
0285 int dpu_crtc_register_custom_event(struct dpu_kms *kms,
0286         struct drm_crtc *crtc_drm, u32 event, bool en);
0287
0288 /**
0289  * dpu_crtc_get_intf_mode - get interface mode of the given crtc
0290  * @crtc: Pointert to crtc
0291  */
0292 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc);
0293
0294 /**
0295  * dpu_crtc_get_client_type - check the crtc type- rt, nrt etc.
0296  * @crtc: Pointer to crtc
0297  */
0298 static inline enum dpu_crtc_client_type dpu_crtc_get_client_type(
0299                         struct drm_crtc *crtc)
0300 {
0301     return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT;
0302 }
0303
0304 #endif /* _DPU_CRTC_H_ */