msm/adreno/adreno_pm4.xml.h

0001 #ifndef ADRENO_PM4_XML
0002 #define ADRENO_PM4_XML
0003
0004 /* Autogenerated file, DO NOT EDIT manually!
0005
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-01-30 18:25:22)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-06-21 15:24:24)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14609 bytes, from 2021-11-24 23:05:10)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  69086 bytes, from 2022-03-03 16:41:33)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2021-11-24 23:05:10)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113358 bytes, from 2022-01-31 23:06:21)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149512 bytes, from 2022-01-31 23:06:21)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 184954 bytes, from 2022-03-03 16:41:33)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-01-30 18:25:22)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-07-22 15:21:56)
0024
0025 Copyright (C) 2013-2022 by the following authors:
0026 - Rob Clark <robdclark@gmail.com> (robclark)
0027 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0028
0029 Permission is hereby granted, free of charge, to any person obtaining
0030 a copy of this software and associated documentation files (the
0031 "Software"), to deal in the Software without restriction, including
0032 without limitation the rights to use, copy, modify, merge, publish,
0033 distribute, sublicense, and/or sell copies of the Software, and to
0034 permit persons to whom the Software is furnished to do so, subject to
0035 the following conditions:
0036
0037 The above copyright notice and this permission notice (including the
0038 next paragraph) shall be included in all copies or substantial
0039 portions of the Software.
0040
0041 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0042 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0043 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0044 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0045 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0046 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0047 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0048 */
0049
0050
0051 enum vgt_event_type {
0052     VS_DEALLOC = 0,
0053     PS_DEALLOC = 1,
0054     VS_DONE_TS = 2,
0055     PS_DONE_TS = 3,
0056     CACHE_FLUSH_TS = 4,
0057     CONTEXT_DONE = 5,
0058     CACHE_FLUSH = 6,
0059     VIZQUERY_START = 7,
0060     HLSQ_FLUSH = 7,
0061     VIZQUERY_END = 8,
0062     SC_WAIT_WC = 9,
0063     WRITE_PRIMITIVE_COUNTS = 9,
0064     START_PRIMITIVE_CTRS = 11,
0065     STOP_PRIMITIVE_CTRS = 12,
0066     RST_PIX_CNT = 13,
0067     RST_VTX_CNT = 14,
0068     TILE_FLUSH = 15,
0069     STAT_EVENT = 16,
0070     CACHE_FLUSH_AND_INV_TS_EVENT = 20,
0071     ZPASS_DONE = 21,
0072     CACHE_FLUSH_AND_INV_EVENT = 22,
0073     RB_DONE_TS = 22,
0074     PERFCOUNTER_START = 23,
0075     PERFCOUNTER_STOP = 24,
0076     VS_FETCH_DONE = 27,
0077     FACENESS_FLUSH = 28,
0078     WT_DONE_TS = 8,
0079     FLUSH_SO_0 = 17,
0080     FLUSH_SO_1 = 18,
0081     FLUSH_SO_2 = 19,
0082     FLUSH_SO_3 = 20,
0083     PC_CCU_INVALIDATE_DEPTH = 24,
0084     PC_CCU_INVALIDATE_COLOR = 25,
0085     PC_CCU_RESOLVE_TS = 26,
0086     PC_CCU_FLUSH_DEPTH_TS = 28,
0087     PC_CCU_FLUSH_COLOR_TS = 29,
0088     BLIT = 30,
0089     UNK_25 = 37,
0090     LRZ_FLUSH = 38,
0091     BLIT_OP_FILL_2D = 39,
0092     BLIT_OP_COPY_2D = 40,
0093     BLIT_OP_SCALE_2D = 42,
0094     CONTEXT_DONE_2D = 43,
0095     UNK_2C = 44,
0096     UNK_2D = 45,
0097     CACHE_INVALIDATE = 49,
0098 };
0099
0100 enum pc_di_primtype {
0101     DI_PT_NONE = 0,
0102     DI_PT_POINTLIST_PSIZE = 1,
0103     DI_PT_LINELIST = 2,
0104     DI_PT_LINESTRIP = 3,
0105     DI_PT_TRILIST = 4,
0106     DI_PT_TRIFAN = 5,
0107     DI_PT_TRISTRIP = 6,
0108     DI_PT_LINELOOP = 7,
0109     DI_PT_RECTLIST = 8,
0110     DI_PT_POINTLIST = 9,
0111     DI_PT_LINE_ADJ = 10,
0112     DI_PT_LINESTRIP_ADJ = 11,
0113     DI_PT_TRI_ADJ = 12,
0114     DI_PT_TRISTRIP_ADJ = 13,
0115     DI_PT_PATCHES0 = 31,
0116     DI_PT_PATCHES1 = 32,
0117     DI_PT_PATCHES2 = 33,
0118     DI_PT_PATCHES3 = 34,
0119     DI_PT_PATCHES4 = 35,
0120     DI_PT_PATCHES5 = 36,
0121     DI_PT_PATCHES6 = 37,
0122     DI_PT_PATCHES7 = 38,
0123     DI_PT_PATCHES8 = 39,
0124     DI_PT_PATCHES9 = 40,
0125     DI_PT_PATCHES10 = 41,
0126     DI_PT_PATCHES11 = 42,
0127     DI_PT_PATCHES12 = 43,
0128     DI_PT_PATCHES13 = 44,
0129     DI_PT_PATCHES14 = 45,
0130     DI_PT_PATCHES15 = 46,
0131     DI_PT_PATCHES16 = 47,
0132     DI_PT_PATCHES17 = 48,
0133     DI_PT_PATCHES18 = 49,
0134     DI_PT_PATCHES19 = 50,
0135     DI_PT_PATCHES20 = 51,
0136     DI_PT_PATCHES21 = 52,
0137     DI_PT_PATCHES22 = 53,
0138     DI_PT_PATCHES23 = 54,
0139     DI_PT_PATCHES24 = 55,
0140     DI_PT_PATCHES25 = 56,
0141     DI_PT_PATCHES26 = 57,
0142     DI_PT_PATCHES27 = 58,
0143     DI_PT_PATCHES28 = 59,
0144     DI_PT_PATCHES29 = 60,
0145     DI_PT_PATCHES30 = 61,
0146     DI_PT_PATCHES31 = 62,
0147 };
0148
0149 enum pc_di_src_sel {
0150     DI_SRC_SEL_DMA = 0,
0151     DI_SRC_SEL_IMMEDIATE = 1,
0152     DI_SRC_SEL_AUTO_INDEX = 2,
0153     DI_SRC_SEL_AUTO_XFB = 3,
0154 };
0155
0156 enum pc_di_face_cull_sel {
0157     DI_FACE_CULL_NONE = 0,
0158     DI_FACE_CULL_FETCH = 1,
0159     DI_FACE_BACKFACE_CULL = 2,
0160     DI_FACE_FRONTFACE_CULL = 3,
0161 };
0162
0163 enum pc_di_index_size {
0164     INDEX_SIZE_IGN = 0,
0165     INDEX_SIZE_16_BIT = 0,
0166     INDEX_SIZE_32_BIT = 1,
0167     INDEX_SIZE_8_BIT = 2,
0168     INDEX_SIZE_INVALID = 0,
0169 };
0170
0171 enum pc_di_vis_cull_mode {
0172     IGNORE_VISIBILITY = 0,
0173     USE_VISIBILITY = 1,
0174 };
0175
0176 enum adreno_pm4_packet_type {
0177     CP_TYPE0_PKT = 0,
0178     CP_TYPE1_PKT = 0x40000000,
0179     CP_TYPE2_PKT = 0x80000000,
0180     CP_TYPE3_PKT = 0xc0000000,
0181     CP_TYPE4_PKT = 0x40000000,
0182     CP_TYPE7_PKT = 0x70000000,
0183 };
0184
0185 enum adreno_pm4_type3_packets {
0186     CP_ME_INIT = 72,
0187     CP_NOP = 16,
0188     CP_PREEMPT_ENABLE = 28,
0189     CP_PREEMPT_TOKEN = 30,
0190     CP_INDIRECT_BUFFER = 63,
0191     CP_INDIRECT_BUFFER_CHAIN = 87,
0192     CP_INDIRECT_BUFFER_PFD = 55,
0193     CP_WAIT_FOR_IDLE = 38,
0194     CP_WAIT_REG_MEM = 60,
0195     CP_WAIT_REG_EQ = 82,
0196     CP_WAIT_REG_GTE = 83,
0197     CP_WAIT_UNTIL_READ = 92,
0198     CP_WAIT_IB_PFD_COMPLETE = 93,
0199     CP_REG_RMW = 33,
0200     CP_SET_BIN_DATA = 47,
0201     CP_SET_BIN_DATA5 = 47,
0202     CP_REG_TO_MEM = 62,
0203     CP_MEM_WRITE = 61,
0204     CP_MEM_WRITE_CNTR = 79,
0205     CP_COND_EXEC = 68,
0206     CP_COND_WRITE = 69,
0207     CP_COND_WRITE5 = 69,
0208     CP_EVENT_WRITE = 70,
0209     CP_EVENT_WRITE_SHD = 88,
0210     CP_EVENT_WRITE_CFL = 89,
0211     CP_EVENT_WRITE_ZPD = 91,
0212     CP_RUN_OPENCL = 49,
0213     CP_DRAW_INDX = 34,
0214     CP_DRAW_INDX_2 = 54,
0215     CP_DRAW_INDX_BIN = 52,
0216     CP_DRAW_INDX_2_BIN = 53,
0217     CP_VIZ_QUERY = 35,
0218     CP_SET_STATE = 37,
0219     CP_SET_CONSTANT = 45,
0220     CP_IM_LOAD = 39,
0221     CP_IM_LOAD_IMMEDIATE = 43,
0222     CP_LOAD_CONSTANT_CONTEXT = 46,
0223     CP_INVALIDATE_STATE = 59,
0224     CP_SET_SHADER_BASES = 74,
0225     CP_SET_BIN_MASK = 80,
0226     CP_SET_BIN_SELECT = 81,
0227     CP_CONTEXT_UPDATE = 94,
0228     CP_INTERRUPT = 64,
0229     CP_IM_STORE = 44,
0230     CP_SET_DRAW_INIT_FLAGS = 75,
0231     CP_SET_PROTECTED_MODE = 95,
0232     CP_BOOTSTRAP_UCODE = 111,
0233     CP_LOAD_STATE = 48,
0234     CP_LOAD_STATE4 = 48,
0235     CP_COND_INDIRECT_BUFFER_PFE = 58,
0236     CP_COND_INDIRECT_BUFFER_PFD = 50,
0237     CP_INDIRECT_BUFFER_PFE = 63,
0238     CP_SET_BIN = 76,
0239     CP_TEST_TWO_MEMS = 113,
0240     CP_REG_WR_NO_CTXT = 120,
0241     CP_RECORD_PFP_TIMESTAMP = 17,
0242     CP_SET_SECURE_MODE = 102,
0243     CP_WAIT_FOR_ME = 19,
0244     CP_SET_DRAW_STATE = 67,
0245     CP_DRAW_INDX_OFFSET = 56,
0246     CP_DRAW_INDIRECT = 40,
0247     CP_DRAW_INDX_INDIRECT = 41,
0248     CP_DRAW_INDIRECT_MULTI = 42,
0249     CP_DRAW_AUTO = 36,
0250     CP_DRAW_PRED_ENABLE_GLOBAL = 25,
0251     CP_DRAW_PRED_ENABLE_LOCAL = 26,
0252     CP_DRAW_PRED_SET = 78,
0253     CP_WIDE_REG_WRITE = 116,
0254     CP_SCRATCH_TO_REG = 77,
0255     CP_REG_TO_SCRATCH = 74,
0256     CP_WAIT_MEM_WRITES = 18,
0257     CP_COND_REG_EXEC = 71,
0258     CP_MEM_TO_REG = 66,
0259     CP_EXEC_CS_INDIRECT = 65,
0260     CP_EXEC_CS = 51,
0261     CP_PERFCOUNTER_ACTION = 80,
0262     CP_SMMU_TABLE_UPDATE = 83,
0263     CP_SET_MARKER = 101,
0264     CP_SET_PSEUDO_REG = 86,
0265     CP_CONTEXT_REG_BUNCH = 92,
0266     CP_YIELD_ENABLE = 28,
0267     CP_SKIP_IB2_ENABLE_GLOBAL = 29,
0268     CP_SKIP_IB2_ENABLE_LOCAL = 35,
0269     CP_SET_SUBDRAW_SIZE = 53,
0270     CP_WHERE_AM_I = 98,
0271     CP_SET_VISIBILITY_OVERRIDE = 100,
0272     CP_PREEMPT_ENABLE_GLOBAL = 105,
0273     CP_PREEMPT_ENABLE_LOCAL = 106,
0274     CP_CONTEXT_SWITCH_YIELD = 107,
0275     CP_SET_RENDER_MODE = 108,
0276     CP_COMPUTE_CHECKPOINT = 110,
0277     CP_MEM_TO_MEM = 115,
0278     CP_BLIT = 44,
0279     CP_REG_TEST = 57,
0280     CP_SET_MODE = 99,
0281     CP_LOAD_STATE6_GEOM = 50,
0282     CP_LOAD_STATE6_FRAG = 52,
0283     CP_LOAD_STATE6 = 54,
0284     IN_IB_PREFETCH_END = 23,
0285     IN_SUBBLK_PREFETCH = 31,
0286     IN_INSTR_PREFETCH = 32,
0287     IN_INSTR_MATCH = 71,
0288     IN_CONST_PREFETCH = 73,
0289     IN_INCR_UPDT_STATE = 85,
0290     IN_INCR_UPDT_CONST = 86,
0291     IN_INCR_UPDT_INSTR = 87,
0292     PKT4 = 4,
0293     CP_SCRATCH_WRITE = 76,
0294     CP_REG_TO_MEM_OFFSET_MEM = 116,
0295     CP_REG_TO_MEM_OFFSET_REG = 114,
0296     CP_WAIT_MEM_GTE = 20,
0297     CP_WAIT_TWO_REGS = 112,
0298     CP_MEMCPY = 117,
0299     CP_SET_BIN_DATA5_OFFSET = 46,
0300     CP_SET_CTXSWITCH_IB = 85,
0301     CP_REG_WRITE = 109,
0302     CP_START_BIN = 80,
0303     CP_END_BIN = 81,
0304 };
0305
0306 enum adreno_state_block {
0307     SB_VERT_TEX = 0,
0308     SB_VERT_MIPADDR = 1,
0309     SB_FRAG_TEX = 2,
0310     SB_FRAG_MIPADDR = 3,
0311     SB_VERT_SHADER = 4,
0312     SB_GEOM_SHADER = 5,
0313     SB_FRAG_SHADER = 6,
0314     SB_COMPUTE_SHADER = 7,
0315 };
0316
0317 enum adreno_state_type {
0318     ST_SHADER = 0,
0319     ST_CONSTANTS = 1,
0320 };
0321
0322 enum adreno_state_src {
0323     SS_DIRECT = 0,
0324     SS_INVALID_ALL_IC = 2,
0325     SS_INVALID_PART_IC = 3,
0326     SS_INDIRECT = 4,
0327     SS_INDIRECT_TCM = 5,
0328     SS_INDIRECT_STM = 6,
0329 };
0330
0331 enum a4xx_state_block {
0332     SB4_VS_TEX = 0,
0333     SB4_HS_TEX = 1,
0334     SB4_DS_TEX = 2,
0335     SB4_GS_TEX = 3,
0336     SB4_FS_TEX = 4,
0337     SB4_CS_TEX = 5,
0338     SB4_VS_SHADER = 8,
0339     SB4_HS_SHADER = 9,
0340     SB4_DS_SHADER = 10,
0341     SB4_GS_SHADER = 11,
0342     SB4_FS_SHADER = 12,
0343     SB4_CS_SHADER = 13,
0344     SB4_SSBO = 14,
0345     SB4_CS_SSBO = 15,
0346 };
0347
0348 enum a4xx_state_type {
0349     ST4_SHADER = 0,
0350     ST4_CONSTANTS = 1,
0351     ST4_UBO = 2,
0352 };
0353
0354 enum a4xx_state_src {
0355     SS4_DIRECT = 0,
0356     SS4_INDIRECT = 2,
0357 };
0358
0359 enum a6xx_state_block {
0360     SB6_VS_TEX = 0,
0361     SB6_HS_TEX = 1,
0362     SB6_DS_TEX = 2,
0363     SB6_GS_TEX = 3,
0364     SB6_FS_TEX = 4,
0365     SB6_CS_TEX = 5,
0366     SB6_VS_SHADER = 8,
0367     SB6_HS_SHADER = 9,
0368     SB6_DS_SHADER = 10,
0369     SB6_GS_SHADER = 11,
0370     SB6_FS_SHADER = 12,
0371     SB6_CS_SHADER = 13,
0372     SB6_IBO = 14,
0373     SB6_CS_IBO = 15,
0374 };
0375
0376 enum a6xx_state_type {
0377     ST6_SHADER = 0,
0378     ST6_CONSTANTS = 1,
0379     ST6_UBO = 2,
0380     ST6_IBO = 3,
0381 };
0382
0383 enum a6xx_state_src {
0384     SS6_DIRECT = 0,
0385     SS6_BINDLESS = 1,
0386     SS6_INDIRECT = 2,
0387     SS6_UBO = 3,
0388 };
0389
0390 enum a4xx_index_size {
0391     INDEX4_SIZE_8_BIT = 0,
0392     INDEX4_SIZE_16_BIT = 1,
0393     INDEX4_SIZE_32_BIT = 2,
0394 };
0395
0396 enum a6xx_patch_type {
0397     TESS_QUADS = 0,
0398     TESS_TRIANGLES = 1,
0399     TESS_ISOLINES = 2,
0400 };
0401
0402 enum a6xx_draw_indirect_opcode {
0403     INDIRECT_OP_NORMAL = 2,
0404     INDIRECT_OP_INDEXED = 4,
0405     INDIRECT_OP_INDIRECT_COUNT = 6,
0406     INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
0407 };
0408
0409 enum cp_draw_pred_src {
0410     PRED_SRC_MEM = 5,
0411 };
0412
0413 enum cp_draw_pred_test {
0414     NE_0_PASS = 0,
0415     EQ_0_PASS = 1,
0416 };
0417
0418 enum cp_cond_function {
0419     WRITE_ALWAYS = 0,
0420     WRITE_LT = 1,
0421     WRITE_LE = 2,
0422     WRITE_EQ = 3,
0423     WRITE_NE = 4,
0424     WRITE_GE = 5,
0425     WRITE_GT = 6,
0426 };
0427
0428 enum render_mode_cmd {
0429     BYPASS = 1,
0430     BINNING = 2,
0431     GMEM = 3,
0432     BLIT2D = 5,
0433     BLIT2DSCALE = 7,
0434     END2D = 8,
0435 };
0436
0437 enum cp_blit_cmd {
0438     BLIT_OP_FILL = 0,
0439     BLIT_OP_COPY = 1,
0440     BLIT_OP_SCALE = 3,
0441 };
0442
0443 enum a6xx_marker {
0444     RM6_BYPASS = 1,
0445     RM6_BINNING = 2,
0446     RM6_GMEM = 4,
0447     RM6_ENDVIS = 5,
0448     RM6_RESOLVE = 6,
0449     RM6_YIELD = 7,
0450     RM6_COMPUTE = 8,
0451     RM6_BLIT2DSCALE = 12,
0452     RM6_IB1LIST_START = 13,
0453     RM6_IB1LIST_END = 14,
0454     RM6_IFPC_ENABLE = 256,
0455     RM6_IFPC_DISABLE = 257,
0456 };
0457
0458 enum pseudo_reg {
0459     SMMU_INFO = 0,
0460     NON_SECURE_SAVE_ADDR = 1,
0461     SECURE_SAVE_ADDR = 2,
0462     NON_PRIV_SAVE_ADDR = 3,
0463     COUNTER = 4,
0464 };
0465
0466 enum compare_mode {
0467     PRED_TEST = 1,
0468     REG_COMPARE = 2,
0469     RENDER_MODE = 3,
0470 };
0471
0472 enum ctxswitch_ib {
0473     RESTORE_IB = 0,
0474     YIELD_RESTORE_IB = 1,
0475     SAVE_IB = 2,
0476     RB_SAVE_IB = 3,
0477 };
0478
0479 enum reg_tracker {
0480     TRACK_CNTL_REG = 1,
0481     TRACK_RENDER_CNTL = 2,
0482     UNK_EVENT_WRITE = 4,
0483 };
0484
0485 #define REG_CP_LOAD_STATE_0                 0x00000000
0486 #define CP_LOAD_STATE_0_DST_OFF__MASK               0x0000ffff
0487 #define CP_LOAD_STATE_0_DST_OFF__SHIFT              0
0488 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
0489 {
0490     return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
0491 }
0492 #define CP_LOAD_STATE_0_STATE_SRC__MASK             0x00070000
0493 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT            16
0494 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
0495 {
0496     return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
0497 }
0498 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK           0x00380000
0499 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT          19
0500 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
0501 {
0502     return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
0503 }
0504 #define CP_LOAD_STATE_0_NUM_UNIT__MASK              0xffc00000
0505 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT             22
0506 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
0507 {
0508     return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
0509 }
0510
0511 #define REG_CP_LOAD_STATE_1                 0x00000001
0512 #define CP_LOAD_STATE_1_STATE_TYPE__MASK            0x00000003
0513 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT           0
0514 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
0515 {
0516     return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
0517 }
0518 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK          0xfffffffc
0519 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT         2
0520 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
0521 {
0522     return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
0523 }
0524
0525 #define REG_CP_LOAD_STATE4_0                    0x00000000
0526 #define CP_LOAD_STATE4_0_DST_OFF__MASK              0x00003fff
0527 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT             0
0528 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
0529 {
0530     return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
0531 }
0532 #define CP_LOAD_STATE4_0_STATE_SRC__MASK            0x00030000
0533 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT           16
0534 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
0535 {
0536     return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
0537 }
0538 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK          0x003c0000
0539 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT         18
0540 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
0541 {
0542     return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
0543 }
0544 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK             0xffc00000
0545 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT            22
0546 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
0547 {
0548     return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
0549 }
0550
0551 #define REG_CP_LOAD_STATE4_1                    0x00000001
0552 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK           0x00000003
0553 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT          0
0554 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
0555 {
0556     return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
0557 }
0558 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK         0xfffffffc
0559 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT            2
0560 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
0561 {
0562     return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
0563 }
0564
0565 #define REG_CP_LOAD_STATE4_2                    0x00000002
0566 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK          0xffffffff
0567 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT         0
0568 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
0569 {
0570     return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
0571 }
0572
0573 #define REG_CP_LOAD_STATE6_0                    0x00000000
0574 #define CP_LOAD_STATE6_0_DST_OFF__MASK              0x00003fff
0575 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT             0
0576 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
0577 {
0578     return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
0579 }
0580 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK           0x0000c000
0581 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT          14
0582 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
0583 {
0584     return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
0585 }
0586 #define CP_LOAD_STATE6_0_STATE_SRC__MASK            0x00030000
0587 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT           16
0588 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
0589 {
0590     return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
0591 }
0592 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK          0x003c0000
0593 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT         18
0594 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
0595 {
0596     return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
0597 }
0598 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK             0xffc00000
0599 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT            22
0600 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
0601 {
0602     return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
0603 }
0604
0605 #define REG_CP_LOAD_STATE6_1                    0x00000001
0606 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK         0xfffffffc
0607 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT            2
0608 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
0609 {
0610     return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
0611 }
0612
0613 #define REG_CP_LOAD_STATE6_2                    0x00000002
0614 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK          0xffffffff
0615 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT         0
0616 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
0617 {
0618     return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
0619 }
0620
0621 #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR             0x00000001
0622
0623 #define REG_CP_DRAW_INDX_0                  0x00000000
0624 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK              0xffffffff
0625 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT             0
0626 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
0627 {
0628     return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
0629 }
0630
0631 #define REG_CP_DRAW_INDX_1                  0x00000001
0632 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK              0x0000003f
0633 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT             0
0634 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
0635 {
0636     return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
0637 }
0638 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK          0x000000c0
0639 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT         6
0640 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
0641 {
0642     return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
0643 }
0644 #define CP_DRAW_INDX_1_VIS_CULL__MASK               0x00000600
0645 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT              9
0646 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
0647 {
0648     return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
0649 }
0650 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK             0x00000800
0651 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT            11
0652 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
0653 {
0654     return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
0655 }
0656 #define CP_DRAW_INDX_1_NOT_EOP                  0x00001000
0657 #define CP_DRAW_INDX_1_SMALL_INDEX              0x00002000
0658 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE        0x00004000
0659 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK          0xff000000
0660 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT         24
0661 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
0662 {
0663     return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
0664 }
0665
0666 #define REG_CP_DRAW_INDX_2                  0x00000002
0667 #define CP_DRAW_INDX_2_NUM_INDICES__MASK            0xffffffff
0668 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT           0
0669 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
0670 {
0671     return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
0672 }
0673
0674 #define REG_CP_DRAW_INDX_3                  0x00000003
0675 #define CP_DRAW_INDX_3_INDX_BASE__MASK              0xffffffff
0676 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT             0
0677 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
0678 {
0679     return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
0680 }
0681
0682 #define REG_CP_DRAW_INDX_4                  0x00000004
0683 #define CP_DRAW_INDX_4_INDX_SIZE__MASK              0xffffffff
0684 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT             0
0685 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
0686 {
0687     return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
0688 }
0689
0690 #define REG_CP_DRAW_INDX_2_0                    0x00000000
0691 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK            0xffffffff
0692 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT           0
0693 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
0694 {
0695     return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
0696 }
0697
0698 #define REG_CP_DRAW_INDX_2_1                    0x00000001
0699 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK            0x0000003f
0700 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT           0
0701 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
0702 {
0703     return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
0704 }
0705 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK            0x000000c0
0706 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT           6
0707 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
0708 {
0709     return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
0710 }
0711 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK             0x00000600
0712 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT            9
0713 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
0714 {
0715     return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
0716 }
0717 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK           0x00000800
0718 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT          11
0719 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
0720 {
0721     return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
0722 }
0723 #define CP_DRAW_INDX_2_1_NOT_EOP                0x00001000
0724 #define CP_DRAW_INDX_2_1_SMALL_INDEX                0x00002000
0725 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE      0x00004000
0726 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK            0xff000000
0727 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT           24
0728 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
0729 {
0730     return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
0731 }
0732
0733 #define REG_CP_DRAW_INDX_2_2                    0x00000002
0734 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK          0xffffffff
0735 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT         0
0736 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
0737 {
0738     return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
0739 }
0740
0741 #define REG_CP_DRAW_INDX_OFFSET_0               0x00000000
0742 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK           0x0000003f
0743 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT          0
0744 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
0745 {
0746     return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
0747 }
0748 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK       0x000000c0
0749 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT      6
0750 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
0751 {
0752     return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
0753 }
0754 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK            0x00000300
0755 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT           8
0756 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
0757 {
0758     return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
0759 }
0760 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK          0x00000c00
0761 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT         10
0762 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
0763 {
0764     return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
0765 }
0766 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK          0x00003000
0767 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT         12
0768 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
0769 {
0770     return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;
0771 }
0772 #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE             0x00010000
0773 #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE           0x00020000
0774
0775 #define REG_CP_DRAW_INDX_OFFSET_1               0x00000001
0776 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK       0xffffffff
0777 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT      0
0778 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
0779 {
0780     return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
0781 }
0782
0783 #define REG_CP_DRAW_INDX_OFFSET_2               0x00000002
0784 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK         0xffffffff
0785 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT        0
0786 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
0787 {
0788     return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
0789 }
0790
0791 #define REG_CP_DRAW_INDX_OFFSET_3               0x00000003
0792 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK          0xffffffff
0793 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT         0
0794 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
0795 {
0796     return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
0797 }
0798
0799
0800 #define REG_CP_DRAW_INDX_OFFSET_4               0x00000004
0801 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK        0xffffffff
0802 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT       0
0803 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
0804 {
0805     return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
0806 }
0807
0808 #define REG_CP_DRAW_INDX_OFFSET_5               0x00000005
0809 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK        0xffffffff
0810 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT       0
0811 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
0812 {
0813     return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
0814 }
0815
0816 #define REG_CP_DRAW_INDX_OFFSET_INDX_BASE           0x00000004
0817
0818 #define REG_CP_DRAW_INDX_OFFSET_6               0x00000006
0819 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK         0xffffffff
0820 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT        0
0821 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
0822 {
0823     return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
0824 }
0825
0826 #define REG_CP_DRAW_INDX_OFFSET_4               0x00000004
0827 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK           0xffffffff
0828 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT          0
0829 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
0830 {
0831     return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
0832 }
0833
0834 #define REG_CP_DRAW_INDX_OFFSET_5               0x00000005
0835 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK           0xffffffff
0836 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT          0
0837 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
0838 {
0839     return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
0840 }
0841
0842 #define REG_A4XX_CP_DRAW_INDIRECT_0             0x00000000
0843 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK         0x0000003f
0844 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT        0
0845 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
0846 {
0847     return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
0848 }
0849 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK     0x000000c0
0850 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT        6
0851 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
0852 {
0853     return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
0854 }
0855 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK          0x00000300
0856 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT         8
0857 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
0858 {
0859     return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
0860 }
0861 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK        0x00000c00
0862 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT       10
0863 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
0864 {
0865     return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
0866 }
0867 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK        0x00003000
0868 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT       12
0869 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
0870 {
0871     return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK;
0872 }
0873 #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE           0x00010000
0874 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE         0x00020000
0875
0876
0877 #define REG_A4XX_CP_DRAW_INDIRECT_1             0x00000001
0878 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK          0xffffffff
0879 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT         0
0880 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
0881 {
0882     return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
0883 }
0884
0885
0886 #define REG_A5XX_CP_DRAW_INDIRECT_1             0x00000001
0887 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK       0xffffffff
0888 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT      0
0889 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
0890 {
0891     return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
0892 }
0893
0894 #define REG_A5XX_CP_DRAW_INDIRECT_2             0x00000002
0895 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK       0xffffffff
0896 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT      0
0897 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
0898 {
0899     return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
0900 }
0901
0902 #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT          0x00000001
0903
0904 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0            0x00000000
0905 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK        0x0000003f
0906 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT       0
0907 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
0908 {
0909     return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
0910 }
0911 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK    0x000000c0
0912 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT   6
0913 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
0914 {
0915     return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
0916 }
0917 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK     0x00000300
0918 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT        8
0919 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
0920 {
0921     return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
0922 }
0923 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK       0x00000c00
0924 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT      10
0925 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
0926 {
0927     return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
0928 }
0929 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK       0x00003000
0930 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT      12
0931 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
0932 {
0933     return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK;
0934 }
0935 #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE          0x00010000
0936 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE        0x00020000
0937
0938
0939 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1            0x00000001
0940 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK        0xffffffff
0941 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT       0
0942 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
0943 {
0944     return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
0945 }
0946
0947 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2            0x00000002
0948 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK        0xffffffff
0949 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT       0
0950 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
0951 {
0952     return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
0953 }
0954
0955 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3            0x00000003
0956 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK     0xffffffff
0957 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT        0
0958 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
0959 {
0960     return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
0961 }
0962
0963
0964 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1            0x00000001
0965 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK     0xffffffff
0966 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT    0
0967 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
0968 {
0969     return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
0970 }
0971
0972 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2            0x00000002
0973 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK     0xffffffff
0974 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT    0
0975 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
0976 {
0977     return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
0978 }
0979
0980 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE        0x00000001
0981
0982 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3            0x00000003
0983 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK      0xffffffff
0984 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT     0
0985 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
0986 {
0987     return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
0988 }
0989
0990 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4            0x00000004
0991 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK      0xffffffff
0992 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT     0
0993 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
0994 {
0995     return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
0996 }
0997
0998 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5            0x00000005
0999 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK      0xffffffff
1000 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT     0
1001 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
1002 {
1003     return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
1004 }
1005
1006 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT         0x00000004
1007
1008 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0           0x00000000
1009 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK       0x0000003f
1010 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT      0
1011 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
1012 {
1013     return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK;
1014 }
1015 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK   0x000000c0
1016 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT  6
1017 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
1018 {
1019     return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK;
1020 }
1021 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK        0x00000300
1022 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT       8
1023 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
1024 {
1025     return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK;
1026 }
1027 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK      0x00000c00
1028 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT     10
1029 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
1030 {
1031     return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK;
1032 }
1033 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK      0x00003000
1034 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT     12
1035 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
1036 {
1037     return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK;
1038 }
1039 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE         0x00010000
1040 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE       0x00020000
1041
1042 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1           0x00000001
1043 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK      0x0000000f
1044 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT     0
1045 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
1046 {
1047     return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK;
1048 }
1049 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK     0x003fff00
1050 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT        8
1051 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
1052 {
1053     return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
1054 }
1055
1056 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT      0x00000002
1057
1058
1059 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT        0x00000003
1060
1061 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE          0x00000005
1062
1063
1064 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED        0x00000003
1065
1066 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED      0x00000005
1067
1068 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED     0x00000006
1069
1070 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED       0x00000008
1071
1072
1073 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT        0x00000003
1074
1075 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT  0x00000005
1076
1077 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT      0x00000007
1078
1079
1080 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED   0x00000003
1081
1082 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005
1083
1084 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED    0x00000006
1085
1086 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED  0x00000008
1087
1088 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED  0x0000000a
1089
1090 #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0            0x00000000
1091 #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE         0x00000001
1092
1093 #define REG_CP_DRAW_PRED_ENABLE_LOCAL_0             0x00000000
1094 #define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE          0x00000001
1095
1096 #define REG_CP_DRAW_PRED_SET_0                  0x00000000
1097 #define CP_DRAW_PRED_SET_0_SRC__MASK                0x000000f0
1098 #define CP_DRAW_PRED_SET_0_SRC__SHIFT               4
1099 static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
1100 {
1101     return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
1102 }
1103 #define CP_DRAW_PRED_SET_0_TEST__MASK               0x00000100
1104 #define CP_DRAW_PRED_SET_0_TEST__SHIFT              8
1105 static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
1106 {
1107     return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
1108 }
1109
1110 #define REG_CP_DRAW_PRED_SET_MEM_ADDR               0x00000001
1111
1112 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1113
1114 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1115 #define CP_SET_DRAW_STATE__0_COUNT__MASK            0x0000ffff
1116 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT           0
1117 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
1118 {
1119     return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
1120 }
1121 #define CP_SET_DRAW_STATE__0_DIRTY              0x00010000
1122 #define CP_SET_DRAW_STATE__0_DISABLE                0x00020000
1123 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS         0x00040000
1124 #define CP_SET_DRAW_STATE__0_LOAD_IMMED             0x00080000
1125 #define CP_SET_DRAW_STATE__0_BINNING                0x00100000
1126 #define CP_SET_DRAW_STATE__0_GMEM               0x00200000
1127 #define CP_SET_DRAW_STATE__0_SYSMEM             0x00400000
1128 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK         0x1f000000
1129 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT            24
1130 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
1131 {
1132     return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
1133 }
1134
1135 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1136 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK          0xffffffff
1137 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT         0
1138 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
1139 {
1140     return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
1141 }
1142
1143 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1144 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK          0xffffffff
1145 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT         0
1146 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
1147 {
1148     return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
1149 }
1150
1151 #define REG_CP_SET_BIN_0                    0x00000000
1152
1153 #define REG_CP_SET_BIN_1                    0x00000001
1154 #define CP_SET_BIN_1_X1__MASK                   0x0000ffff
1155 #define CP_SET_BIN_1_X1__SHIFT                  0
1156 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
1157 {
1158     return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
1159 }
1160 #define CP_SET_BIN_1_Y1__MASK                   0xffff0000
1161 #define CP_SET_BIN_1_Y1__SHIFT                  16
1162 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
1163 {
1164     return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
1165 }
1166
1167 #define REG_CP_SET_BIN_2                    0x00000002
1168 #define CP_SET_BIN_2_X2__MASK                   0x0000ffff
1169 #define CP_SET_BIN_2_X2__SHIFT                  0
1170 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
1171 {
1172     return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
1173 }
1174 #define CP_SET_BIN_2_Y2__MASK                   0xffff0000
1175 #define CP_SET_BIN_2_Y2__SHIFT                  16
1176 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
1177 {
1178     return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
1179 }
1180
1181 #define REG_CP_SET_BIN_DATA_0                   0x00000000
1182 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK           0xffffffff
1183 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT          0
1184 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
1185 {
1186     return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
1187 }
1188
1189 #define REG_CP_SET_BIN_DATA_1                   0x00000001
1190 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK        0xffffffff
1191 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT       0
1192 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
1193 {
1194     return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
1195 }
1196
1197 #define REG_CP_SET_BIN_DATA5_0                  0x00000000
1198 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK           0x003f0000
1199 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT          16
1200 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
1201 {
1202     return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
1203 }
1204 #define CP_SET_BIN_DATA5_0_VSC_N__MASK              0x07c00000
1205 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT             22
1206 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
1207 {
1208     return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
1209 }
1210
1211 #define REG_CP_SET_BIN_DATA5_1                  0x00000001
1212 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK       0xffffffff
1213 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT      0
1214 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
1215 {
1216     return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
1217 }
1218
1219 #define REG_CP_SET_BIN_DATA5_2                  0x00000002
1220 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK       0xffffffff
1221 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT      0
1222 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
1223 {
1224     return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
1225 }
1226
1227 #define REG_CP_SET_BIN_DATA5_3                  0x00000003
1228 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK        0xffffffff
1229 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT       0
1230 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
1231 {
1232     return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
1233 }
1234
1235 #define REG_CP_SET_BIN_DATA5_4                  0x00000004
1236 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK        0xffffffff
1237 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT       0
1238 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
1239 {
1240     return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
1241 }
1242
1243 #define REG_CP_SET_BIN_DATA5_5                  0x00000005
1244 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK       0xffffffff
1245 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT      0
1246 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
1247 {
1248     return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK;
1249 }
1250
1251 #define REG_CP_SET_BIN_DATA5_6                  0x00000006
1252 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK       0xffffffff
1253 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT      0
1254 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
1255 {
1256     return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
1257 }
1258
1259 #define REG_CP_SET_BIN_DATA5_OFFSET_0               0x00000000
1260 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK        0x003f0000
1261 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT       16
1262 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
1263 {
1264     return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK;
1265 }
1266 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK           0x07c00000
1267 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT          22
1268 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
1269 {
1270     return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;
1271 }
1272
1273 #define REG_CP_SET_BIN_DATA5_OFFSET_1               0x00000001
1274 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK     0xffffffff
1275 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT    0
1276 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
1277 {
1278     return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK;
1279 }
1280
1281 #define REG_CP_SET_BIN_DATA5_OFFSET_2               0x00000002
1282 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK     0xffffffff
1283 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT    0
1284 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
1285 {
1286     return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK;
1287 }
1288
1289 #define REG_CP_SET_BIN_DATA5_OFFSET_3               0x00000003
1290 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK    0xffffffff
1291 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT   0
1292 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
1293 {
1294     return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK;
1295 }
1296
1297 #define REG_CP_REG_RMW_0                    0x00000000
1298 #define CP_REG_RMW_0_DST_REG__MASK              0x0003ffff
1299 #define CP_REG_RMW_0_DST_REG__SHIFT             0
1300 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
1301 {
1302     return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;
1303 }
1304 #define CP_REG_RMW_0_ROTATE__MASK               0x1f000000
1305 #define CP_REG_RMW_0_ROTATE__SHIFT              24
1306 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
1307 {
1308     return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;
1309 }
1310 #define CP_REG_RMW_0_SRC1_ADD                   0x20000000
1311 #define CP_REG_RMW_0_SRC1_IS_REG                0x40000000
1312 #define CP_REG_RMW_0_SRC0_IS_REG                0x80000000
1313
1314 #define REG_CP_REG_RMW_1                    0x00000001
1315 #define CP_REG_RMW_1_SRC0__MASK                 0xffffffff
1316 #define CP_REG_RMW_1_SRC0__SHIFT                0
1317 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
1318 {
1319     return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;
1320 }
1321
1322 #define REG_CP_REG_RMW_2                    0x00000002
1323 #define CP_REG_RMW_2_SRC1__MASK                 0xffffffff
1324 #define CP_REG_RMW_2_SRC1__SHIFT                0
1325 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
1326 {
1327     return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;
1328 }
1329
1330 #define REG_CP_REG_TO_MEM_0                 0x00000000
1331 #define CP_REG_TO_MEM_0_REG__MASK               0x0003ffff
1332 #define CP_REG_TO_MEM_0_REG__SHIFT              0
1333 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
1334 {
1335     return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
1336 }
1337 #define CP_REG_TO_MEM_0_CNT__MASK               0x3ffc0000
1338 #define CP_REG_TO_MEM_0_CNT__SHIFT              18
1339 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
1340 {
1341     return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
1342 }
1343 #define CP_REG_TO_MEM_0_64B                 0x40000000
1344 #define CP_REG_TO_MEM_0_ACCUMULATE              0x80000000
1345
1346 #define REG_CP_REG_TO_MEM_1                 0x00000001
1347 #define CP_REG_TO_MEM_1_DEST__MASK              0xffffffff
1348 #define CP_REG_TO_MEM_1_DEST__SHIFT             0
1349 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1350 {
1351     return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1352 }
1353
1354 #define REG_CP_REG_TO_MEM_2                 0x00000002
1355 #define CP_REG_TO_MEM_2_DEST_HI__MASK               0xffffffff
1356 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT              0
1357 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1358 {
1359     return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1360 }
1361
1362 #define REG_CP_REG_TO_MEM_OFFSET_REG_0              0x00000000
1363 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK            0x0003ffff
1364 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT           0
1365 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
1366 {
1367     return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;
1368 }
1369 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK            0x3ffc0000
1370 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT           18
1371 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
1372 {
1373     return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;
1374 }
1375 #define CP_REG_TO_MEM_OFFSET_REG_0_64B              0x40000000
1376 #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE           0x80000000
1377
1378 #define REG_CP_REG_TO_MEM_OFFSET_REG_1              0x00000001
1379 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK           0xffffffff
1380 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT          0
1381 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
1382 {
1383     return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;
1384 }
1385
1386 #define REG_CP_REG_TO_MEM_OFFSET_REG_2              0x00000002
1387 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK        0xffffffff
1388 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT       0
1389 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
1390 {
1391     return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK;
1392 }
1393
1394 #define REG_CP_REG_TO_MEM_OFFSET_REG_3              0x00000003
1395 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK        0x0003ffff
1396 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT       0
1397 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
1398 {
1399     return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK;
1400 }
1401 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH      0x00080000
1402
1403 #define REG_CP_REG_TO_MEM_OFFSET_MEM_0              0x00000000
1404 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK            0x0003ffff
1405 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT           0
1406 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
1407 {
1408     return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;
1409 }
1410 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK            0x3ffc0000
1411 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT           18
1412 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
1413 {
1414     return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;
1415 }
1416 #define CP_REG_TO_MEM_OFFSET_MEM_0_64B              0x40000000
1417 #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE           0x80000000
1418
1419 #define REG_CP_REG_TO_MEM_OFFSET_MEM_1              0x00000001
1420 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK           0xffffffff
1421 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT          0
1422 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
1423 {
1424     return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;
1425 }
1426
1427 #define REG_CP_REG_TO_MEM_OFFSET_MEM_2              0x00000002
1428 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK        0xffffffff
1429 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT       0
1430 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
1431 {
1432     return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK;
1433 }
1434
1435 #define REG_CP_REG_TO_MEM_OFFSET_MEM_3              0x00000003
1436 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK      0xffffffff
1437 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT     0
1438 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
1439 {
1440     return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK;
1441 }
1442
1443 #define REG_CP_REG_TO_MEM_OFFSET_MEM_4              0x00000004
1444 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK      0xffffffff
1445 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT     0
1446 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
1447 {
1448     return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK;
1449 }
1450
1451 #define REG_CP_MEM_TO_REG_0                 0x00000000
1452 #define CP_MEM_TO_REG_0_REG__MASK               0x0003ffff
1453 #define CP_MEM_TO_REG_0_REG__SHIFT              0
1454 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1455 {
1456     return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1457 }
1458 #define CP_MEM_TO_REG_0_CNT__MASK               0x3ff80000
1459 #define CP_MEM_TO_REG_0_CNT__SHIFT              19
1460 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1461 {
1462     return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1463 }
1464 #define CP_MEM_TO_REG_0_SHIFT_BY_2              0x40000000
1465 #define CP_MEM_TO_REG_0_UNK31                   0x80000000
1466
1467 #define REG_CP_MEM_TO_REG_1                 0x00000001
1468 #define CP_MEM_TO_REG_1_SRC__MASK               0xffffffff
1469 #define CP_MEM_TO_REG_1_SRC__SHIFT              0
1470 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1471 {
1472     return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1473 }
1474
1475 #define REG_CP_MEM_TO_REG_2                 0x00000002
1476 #define CP_MEM_TO_REG_2_SRC_HI__MASK                0xffffffff
1477 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT               0
1478 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1479 {
1480     return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1481 }
1482
1483 #define REG_CP_MEM_TO_MEM_0                 0x00000000
1484 #define CP_MEM_TO_MEM_0_NEG_A                   0x00000001
1485 #define CP_MEM_TO_MEM_0_NEG_B                   0x00000002
1486 #define CP_MEM_TO_MEM_0_NEG_C                   0x00000004
1487 #define CP_MEM_TO_MEM_0_DOUBLE                  0x20000000
1488 #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES         0x40000000
1489 #define CP_MEM_TO_MEM_0_UNK31                   0x80000000
1490
1491 #define REG_CP_MEMCPY_0                     0x00000000
1492 #define CP_MEMCPY_0_DWORDS__MASK                0xffffffff
1493 #define CP_MEMCPY_0_DWORDS__SHIFT               0
1494 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
1495 {
1496     return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;
1497 }
1498
1499 #define REG_CP_MEMCPY_1                     0x00000001
1500 #define CP_MEMCPY_1_SRC_LO__MASK                0xffffffff
1501 #define CP_MEMCPY_1_SRC_LO__SHIFT               0
1502 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
1503 {
1504     return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;
1505 }
1506
1507 #define REG_CP_MEMCPY_2                     0x00000002
1508 #define CP_MEMCPY_2_SRC_HI__MASK                0xffffffff
1509 #define CP_MEMCPY_2_SRC_HI__SHIFT               0
1510 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
1511 {
1512     return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;
1513 }
1514
1515 #define REG_CP_MEMCPY_3                     0x00000003
1516 #define CP_MEMCPY_3_DST_LO__MASK                0xffffffff
1517 #define CP_MEMCPY_3_DST_LO__SHIFT               0
1518 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
1519 {
1520     return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;
1521 }
1522
1523 #define REG_CP_MEMCPY_4                     0x00000004
1524 #define CP_MEMCPY_4_DST_HI__MASK                0xffffffff
1525 #define CP_MEMCPY_4_DST_HI__SHIFT               0
1526 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
1527 {
1528     return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;
1529 }
1530
1531 #define REG_CP_REG_TO_SCRATCH_0                 0x00000000
1532 #define CP_REG_TO_SCRATCH_0_REG__MASK               0x0003ffff
1533 #define CP_REG_TO_SCRATCH_0_REG__SHIFT              0
1534 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
1535 {
1536     return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;
1537 }
1538 #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK           0x00700000
1539 #define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT          20
1540 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
1541 {
1542     return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;
1543 }
1544 #define CP_REG_TO_SCRATCH_0_CNT__MASK               0x07000000
1545 #define CP_REG_TO_SCRATCH_0_CNT__SHIFT              24
1546 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
1547 {
1548     return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;
1549 }
1550
1551 #define REG_CP_SCRATCH_TO_REG_0                 0x00000000
1552 #define CP_SCRATCH_TO_REG_0_REG__MASK               0x0003ffff
1553 #define CP_SCRATCH_TO_REG_0_REG__SHIFT              0
1554 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
1555 {
1556     return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;
1557 }
1558 #define CP_SCRATCH_TO_REG_0_UNK18               0x00040000
1559 #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK           0x00700000
1560 #define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT          20
1561 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
1562 {
1563     return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;
1564 }
1565 #define CP_SCRATCH_TO_REG_0_CNT__MASK               0x07000000
1566 #define CP_SCRATCH_TO_REG_0_CNT__SHIFT              24
1567 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
1568 {
1569     return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;
1570 }
1571
1572 #define REG_CP_SCRATCH_WRITE_0                  0x00000000
1573 #define CP_SCRATCH_WRITE_0_SCRATCH__MASK            0x00700000
1574 #define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT           20
1575 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
1576 {
1577     return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;
1578 }
1579
1580 #define REG_CP_MEM_WRITE_0                  0x00000000
1581 #define CP_MEM_WRITE_0_ADDR_LO__MASK                0xffffffff
1582 #define CP_MEM_WRITE_0_ADDR_LO__SHIFT               0
1583 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
1584 {
1585     return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;
1586 }
1587
1588 #define REG_CP_MEM_WRITE_1                  0x00000001
1589 #define CP_MEM_WRITE_1_ADDR_HI__MASK                0xffffffff
1590 #define CP_MEM_WRITE_1_ADDR_HI__SHIFT               0
1591 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
1592 {
1593     return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;
1594 }
1595
1596 #define REG_CP_COND_WRITE_0                 0x00000000
1597 #define CP_COND_WRITE_0_FUNCTION__MASK              0x00000007
1598 #define CP_COND_WRITE_0_FUNCTION__SHIFT             0
1599 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1600 {
1601     return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1602 }
1603 #define CP_COND_WRITE_0_POLL_MEMORY             0x00000010
1604 #define CP_COND_WRITE_0_WRITE_MEMORY                0x00000100
1605
1606 #define REG_CP_COND_WRITE_1                 0x00000001
1607 #define CP_COND_WRITE_1_POLL_ADDR__MASK             0xffffffff
1608 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT            0
1609 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1610 {
1611     return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1612 }
1613
1614 #define REG_CP_COND_WRITE_2                 0x00000002
1615 #define CP_COND_WRITE_2_REF__MASK               0xffffffff
1616 #define CP_COND_WRITE_2_REF__SHIFT              0
1617 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1618 {
1619     return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1620 }
1621
1622 #define REG_CP_COND_WRITE_3                 0x00000003
1623 #define CP_COND_WRITE_3_MASK__MASK              0xffffffff
1624 #define CP_COND_WRITE_3_MASK__SHIFT             0
1625 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1626 {
1627     return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1628 }
1629
1630 #define REG_CP_COND_WRITE_4                 0x00000004
1631 #define CP_COND_WRITE_4_WRITE_ADDR__MASK            0xffffffff
1632 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT           0
1633 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1634 {
1635     return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1636 }
1637
1638 #define REG_CP_COND_WRITE_5                 0x00000005
1639 #define CP_COND_WRITE_5_WRITE_DATA__MASK            0xffffffff
1640 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT           0
1641 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1642 {
1643     return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1644 }
1645
1646 #define REG_CP_COND_WRITE5_0                    0x00000000
1647 #define CP_COND_WRITE5_0_FUNCTION__MASK             0x00000007
1648 #define CP_COND_WRITE5_0_FUNCTION__SHIFT            0
1649 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1650 {
1651     return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1652 }
1653 #define CP_COND_WRITE5_0_SIGNED_COMPARE             0x00000008
1654 #define CP_COND_WRITE5_0_POLL_MEMORY                0x00000010
1655 #define CP_COND_WRITE5_0_POLL_SCRATCH               0x00000020
1656 #define CP_COND_WRITE5_0_WRITE_MEMORY               0x00000100
1657
1658 #define REG_CP_COND_WRITE5_1                    0x00000001
1659 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK         0xffffffff
1660 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT            0
1661 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1662 {
1663     return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1664 }
1665
1666 #define REG_CP_COND_WRITE5_2                    0x00000002
1667 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK         0xffffffff
1668 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT            0
1669 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1670 {
1671     return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1672 }
1673
1674 #define REG_CP_COND_WRITE5_3                    0x00000003
1675 #define CP_COND_WRITE5_3_REF__MASK              0xffffffff
1676 #define CP_COND_WRITE5_3_REF__SHIFT             0
1677 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1678 {
1679     return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1680 }
1681
1682 #define REG_CP_COND_WRITE5_4                    0x00000004
1683 #define CP_COND_WRITE5_4_MASK__MASK             0xffffffff
1684 #define CP_COND_WRITE5_4_MASK__SHIFT                0
1685 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1686 {
1687     return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1688 }
1689
1690 #define REG_CP_COND_WRITE5_5                    0x00000005
1691 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK            0xffffffff
1692 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT           0
1693 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1694 {
1695     return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1696 }
1697
1698 #define REG_CP_COND_WRITE5_6                    0x00000006
1699 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK            0xffffffff
1700 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT           0
1701 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1702 {
1703     return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1704 }
1705
1706 #define REG_CP_COND_WRITE5_7                    0x00000007
1707 #define CP_COND_WRITE5_7_WRITE_DATA__MASK           0xffffffff
1708 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT          0
1709 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1710 {
1711     return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1712 }
1713
1714 #define REG_CP_WAIT_MEM_GTE_0                   0x00000000
1715 #define CP_WAIT_MEM_GTE_0_RESERVED__MASK            0xffffffff
1716 #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT           0
1717 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
1718 {
1719     return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;
1720 }
1721
1722 #define REG_CP_WAIT_MEM_GTE_1                   0x00000001
1723 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK            0xffffffff
1724 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT           0
1725 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
1726 {
1727     return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;
1728 }
1729
1730 #define REG_CP_WAIT_MEM_GTE_2                   0x00000002
1731 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK            0xffffffff
1732 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT           0
1733 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
1734 {
1735     return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;
1736 }
1737
1738 #define REG_CP_WAIT_MEM_GTE_3                   0x00000003
1739 #define CP_WAIT_MEM_GTE_3_REF__MASK             0xffffffff
1740 #define CP_WAIT_MEM_GTE_3_REF__SHIFT                0
1741 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
1742 {
1743     return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;
1744 }
1745
1746 #define REG_CP_WAIT_REG_MEM_0                   0x00000000
1747 #define CP_WAIT_REG_MEM_0_FUNCTION__MASK            0x00000007
1748 #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT           0
1749 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
1750 {
1751     return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
1752 }
1753 #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE            0x00000008
1754 #define CP_WAIT_REG_MEM_0_POLL_MEMORY               0x00000010
1755 #define CP_WAIT_REG_MEM_0_POLL_SCRATCH              0x00000020
1756 #define CP_WAIT_REG_MEM_0_WRITE_MEMORY              0x00000100
1757
1758 #define REG_CP_WAIT_REG_MEM_1                   0x00000001
1759 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK            0xffffffff
1760 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT           0
1761 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
1762 {
1763     return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;
1764 }
1765
1766 #define REG_CP_WAIT_REG_MEM_2                   0x00000002
1767 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK            0xffffffff
1768 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT           0
1769 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
1770 {
1771     return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;
1772 }
1773
1774 #define REG_CP_WAIT_REG_MEM_3                   0x00000003
1775 #define CP_WAIT_REG_MEM_3_REF__MASK             0xffffffff
1776 #define CP_WAIT_REG_MEM_3_REF__SHIFT                0
1777 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
1778 {
1779     return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;
1780 }
1781
1782 #define REG_CP_WAIT_REG_MEM_4                   0x00000004
1783 #define CP_WAIT_REG_MEM_4_MASK__MASK                0xffffffff
1784 #define CP_WAIT_REG_MEM_4_MASK__SHIFT               0
1785 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
1786 {
1787     return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;
1788 }
1789
1790 #define REG_CP_WAIT_REG_MEM_5                   0x00000005
1791 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK       0xffffffff
1792 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT      0
1793 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
1794 {
1795     return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK;
1796 }
1797
1798 #define REG_CP_WAIT_TWO_REGS_0                  0x00000000
1799 #define CP_WAIT_TWO_REGS_0_REG0__MASK               0x0003ffff
1800 #define CP_WAIT_TWO_REGS_0_REG0__SHIFT              0
1801 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
1802 {
1803     return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;
1804 }
1805
1806 #define REG_CP_WAIT_TWO_REGS_1                  0x00000001
1807 #define CP_WAIT_TWO_REGS_1_REG1__MASK               0x0003ffff
1808 #define CP_WAIT_TWO_REGS_1_REG1__SHIFT              0
1809 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
1810 {
1811     return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;
1812 }
1813
1814 #define REG_CP_WAIT_TWO_REGS_2                  0x00000002
1815 #define CP_WAIT_TWO_REGS_2_REF__MASK                0xffffffff
1816 #define CP_WAIT_TWO_REGS_2_REF__SHIFT               0
1817 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
1818 {
1819     return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;
1820 }
1821
1822 #define REG_CP_DISPATCH_COMPUTE_0               0x00000000
1823
1824 #define REG_CP_DISPATCH_COMPUTE_1               0x00000001
1825 #define CP_DISPATCH_COMPUTE_1_X__MASK               0xffffffff
1826 #define CP_DISPATCH_COMPUTE_1_X__SHIFT              0
1827 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1828 {
1829     return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1830 }
1831
1832 #define REG_CP_DISPATCH_COMPUTE_2               0x00000002
1833 #define CP_DISPATCH_COMPUTE_2_Y__MASK               0xffffffff
1834 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT              0
1835 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1836 {
1837     return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1838 }
1839
1840 #define REG_CP_DISPATCH_COMPUTE_3               0x00000003
1841 #define CP_DISPATCH_COMPUTE_3_Z__MASK               0xffffffff
1842 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT              0
1843 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1844 {
1845     return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1846 }
1847
1848 #define REG_CP_SET_RENDER_MODE_0                0x00000000
1849 #define CP_SET_RENDER_MODE_0_MODE__MASK             0x000001ff
1850 #define CP_SET_RENDER_MODE_0_MODE__SHIFT            0
1851 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1852 {
1853     return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1854 }
1855
1856 #define REG_CP_SET_RENDER_MODE_1                0x00000001
1857 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK            0xffffffff
1858 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT           0
1859 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1860 {
1861     return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1862 }
1863
1864 #define REG_CP_SET_RENDER_MODE_2                0x00000002
1865 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK            0xffffffff
1866 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT           0
1867 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1868 {
1869     return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1870 }
1871
1872 #define REG_CP_SET_RENDER_MODE_3                0x00000003
1873 #define CP_SET_RENDER_MODE_3_VSC_ENABLE             0x00000008
1874 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE            0x00000010
1875
1876 #define REG_CP_SET_RENDER_MODE_4                0x00000004
1877
1878 #define REG_CP_SET_RENDER_MODE_5                0x00000005
1879 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK           0xffffffff
1880 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT          0
1881 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1882 {
1883     return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1884 }
1885
1886 #define REG_CP_SET_RENDER_MODE_6                0x00000006
1887 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK            0xffffffff
1888 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT           0
1889 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1890 {
1891     return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1892 }
1893
1894 #define REG_CP_SET_RENDER_MODE_7                0x00000007
1895 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK            0xffffffff
1896 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT           0
1897 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1898 {
1899     return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1900 }
1901
1902 #define REG_CP_COMPUTE_CHECKPOINT_0             0x00000000
1903 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK         0xffffffff
1904 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT        0
1905 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1906 {
1907     return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1908 }
1909
1910 #define REG_CP_COMPUTE_CHECKPOINT_1             0x00000001
1911 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK         0xffffffff
1912 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT        0
1913 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1914 {
1915     return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1916 }
1917
1918 #define REG_CP_COMPUTE_CHECKPOINT_2             0x00000002
1919
1920 #define REG_CP_COMPUTE_CHECKPOINT_3             0x00000003
1921 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK        0xffffffff
1922 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT       0
1923 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1924 {
1925     return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1926 }
1927
1928 #define REG_CP_COMPUTE_CHECKPOINT_4             0x00000004
1929
1930 #define REG_CP_COMPUTE_CHECKPOINT_5             0x00000005
1931 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK         0xffffffff
1932 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT        0
1933 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1934 {
1935     return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1936 }
1937
1938 #define REG_CP_COMPUTE_CHECKPOINT_6             0x00000006
1939 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK         0xffffffff
1940 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT        0
1941 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1942 {
1943     return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1944 }
1945
1946 #define REG_CP_COMPUTE_CHECKPOINT_7             0x00000007
1947
1948 #define REG_CP_PERFCOUNTER_ACTION_0             0x00000000
1949
1950 #define REG_CP_PERFCOUNTER_ACTION_1             0x00000001
1951 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK         0xffffffff
1952 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT        0
1953 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1954 {
1955     return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1956 }
1957
1958 #define REG_CP_PERFCOUNTER_ACTION_2             0x00000002
1959 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK         0xffffffff
1960 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT        0
1961 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1962 {
1963     return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1964 }
1965
1966 #define REG_CP_EVENT_WRITE_0                    0x00000000
1967 #define CP_EVENT_WRITE_0_EVENT__MASK                0x000000ff
1968 #define CP_EVENT_WRITE_0_EVENT__SHIFT               0
1969 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1970 {
1971     return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1972 }
1973 #define CP_EVENT_WRITE_0_TIMESTAMP              0x40000000
1974 #define CP_EVENT_WRITE_0_IRQ                    0x80000000
1975
1976 #define REG_CP_EVENT_WRITE_1                    0x00000001
1977 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK            0xffffffff
1978 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT           0
1979 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1980 {
1981     return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1982 }
1983
1984 #define REG_CP_EVENT_WRITE_2                    0x00000002
1985 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK            0xffffffff
1986 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT           0
1987 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1988 {
1989     return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1990 }
1991
1992 #define REG_CP_EVENT_WRITE_3                    0x00000003
1993
1994 #define REG_CP_BLIT_0                       0x00000000
1995 #define CP_BLIT_0_OP__MASK                  0x0000000f
1996 #define CP_BLIT_0_OP__SHIFT                 0
1997 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1998 {
1999     return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
2000 }
2001
2002 #define REG_CP_BLIT_1                       0x00000001
2003 #define CP_BLIT_1_SRC_X1__MASK                  0x00003fff
2004 #define CP_BLIT_1_SRC_X1__SHIFT                 0
2005 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
2006 {
2007     return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
2008 }
2009 #define CP_BLIT_1_SRC_Y1__MASK                  0x3fff0000
2010 #define CP_BLIT_1_SRC_Y1__SHIFT                 16
2011 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
2012 {
2013     return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
2014 }
2015
2016 #define REG_CP_BLIT_2                       0x00000002
2017 #define CP_BLIT_2_SRC_X2__MASK                  0x00003fff
2018 #define CP_BLIT_2_SRC_X2__SHIFT                 0
2019 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
2020 {
2021     return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
2022 }
2023 #define CP_BLIT_2_SRC_Y2__MASK                  0x3fff0000
2024 #define CP_BLIT_2_SRC_Y2__SHIFT                 16
2025 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
2026 {
2027     return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
2028 }
2029
2030 #define REG_CP_BLIT_3                       0x00000003
2031 #define CP_BLIT_3_DST_X1__MASK                  0x00003fff
2032 #define CP_BLIT_3_DST_X1__SHIFT                 0
2033 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
2034 {
2035     return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
2036 }
2037 #define CP_BLIT_3_DST_Y1__MASK                  0x3fff0000
2038 #define CP_BLIT_3_DST_Y1__SHIFT                 16
2039 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
2040 {
2041     return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
2042 }
2043
2044 #define REG_CP_BLIT_4                       0x00000004
2045 #define CP_BLIT_4_DST_X2__MASK                  0x00003fff
2046 #define CP_BLIT_4_DST_X2__SHIFT                 0
2047 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
2048 {
2049     return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
2050 }
2051 #define CP_BLIT_4_DST_Y2__MASK                  0x3fff0000
2052 #define CP_BLIT_4_DST_Y2__SHIFT                 16
2053 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
2054 {
2055     return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
2056 }
2057
2058 #define REG_CP_EXEC_CS_0                    0x00000000
2059
2060 #define REG_CP_EXEC_CS_1                    0x00000001
2061 #define CP_EXEC_CS_1_NGROUPS_X__MASK                0xffffffff
2062 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT               0
2063 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
2064 {
2065     return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
2066 }
2067
2068 #define REG_CP_EXEC_CS_2                    0x00000002
2069 #define CP_EXEC_CS_2_NGROUPS_Y__MASK                0xffffffff
2070 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT               0
2071 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
2072 {
2073     return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
2074 }
2075
2076 #define REG_CP_EXEC_CS_3                    0x00000003
2077 #define CP_EXEC_CS_3_NGROUPS_Z__MASK                0xffffffff
2078 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT               0
2079 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
2080 {
2081     return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
2082 }
2083
2084 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0              0x00000000
2085
2086
2087 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1              0x00000001
2088 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK           0xffffffff
2089 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT          0
2090 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
2091 {
2092     return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
2093 }
2094
2095 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2              0x00000002
2096 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK     0x00000ffc
2097 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT        2
2098 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
2099 {
2100     return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
2101 }
2102 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK     0x003ff000
2103 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT        12
2104 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
2105 {
2106     return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
2107 }
2108 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK     0xffc00000
2109 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT        22
2110 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
2111 {
2112     return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
2113 }
2114
2115
2116 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1              0x00000001
2117 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK        0xffffffff
2118 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT       0
2119 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
2120 {
2121     return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
2122 }
2123
2124 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2              0x00000002
2125 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK        0xffffffff
2126 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT       0
2127 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
2128 {
2129     return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
2130 }
2131
2132 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3              0x00000003
2133 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK     0x00000ffc
2134 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT        2
2135 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
2136 {
2137     return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
2138 }
2139 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK     0x003ff000
2140 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT        12
2141 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
2142 {
2143     return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
2144 }
2145 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK     0xffc00000
2146 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT        22
2147 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
2148 {
2149     return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
2150 }
2151
2152 #define REG_A6XX_CP_SET_MARKER_0                0x00000000
2153 #define A6XX_CP_SET_MARKER_0_MODE__MASK             0x000001ff
2154 #define A6XX_CP_SET_MARKER_0_MODE__SHIFT            0
2155 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)
2156 {
2157     return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
2158 }
2159 #define A6XX_CP_SET_MARKER_0_MARKER__MASK           0x0000000f
2160 #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT          0
2161 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)
2162 {
2163     return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
2164 }
2165
2166 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2167
2168 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2169 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK      0x00000007
2170 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT     0
2171 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
2172 {
2173     return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
2174 }
2175
2176 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
2177 #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK          0xffffffff
2178 #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT         0
2179 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
2180 {
2181     return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;
2182 }
2183
2184 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
2185 #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK          0xffffffff
2186 #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT         0
2187 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
2188 {
2189     return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;
2190 }
2191
2192 #define REG_A6XX_CP_REG_TEST_0                  0x00000000
2193 #define A6XX_CP_REG_TEST_0_REG__MASK                0x0003ffff
2194 #define A6XX_CP_REG_TEST_0_REG__SHIFT               0
2195 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
2196 {
2197     return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
2198 }
2199 #define A6XX_CP_REG_TEST_0_BIT__MASK                0x01f00000
2200 #define A6XX_CP_REG_TEST_0_BIT__SHIFT               20
2201 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
2202 {
2203     return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
2204 }
2205 #define A6XX_CP_REG_TEST_0_WAIT_FOR_ME              0x02000000
2206
2207 #define REG_CP_COND_REG_EXEC_0                  0x00000000
2208 #define CP_COND_REG_EXEC_0_REG0__MASK               0x0003ffff
2209 #define CP_COND_REG_EXEC_0_REG0__SHIFT              0
2210 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
2211 {
2212     return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
2213 }
2214 #define CP_COND_REG_EXEC_0_BINNING              0x02000000
2215 #define CP_COND_REG_EXEC_0_GMEM                 0x04000000
2216 #define CP_COND_REG_EXEC_0_SYSMEM               0x08000000
2217 #define CP_COND_REG_EXEC_0_MODE__MASK               0xf0000000
2218 #define CP_COND_REG_EXEC_0_MODE__SHIFT              28
2219 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
2220 {
2221     return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
2222 }
2223
2224 #define REG_CP_COND_REG_EXEC_1                  0x00000001
2225 #define CP_COND_REG_EXEC_1_DWORDS__MASK             0xffffffff
2226 #define CP_COND_REG_EXEC_1_DWORDS__SHIFT            0
2227 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
2228 {
2229     return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;
2230 }
2231
2232 #define REG_CP_COND_EXEC_0                  0x00000000
2233 #define CP_COND_EXEC_0_ADDR0_LO__MASK               0xffffffff
2234 #define CP_COND_EXEC_0_ADDR0_LO__SHIFT              0
2235 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
2236 {
2237     return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;
2238 }
2239
2240 #define REG_CP_COND_EXEC_1                  0x00000001
2241 #define CP_COND_EXEC_1_ADDR0_HI__MASK               0xffffffff
2242 #define CP_COND_EXEC_1_ADDR0_HI__SHIFT              0
2243 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
2244 {
2245     return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;
2246 }
2247
2248 #define REG_CP_COND_EXEC_2                  0x00000002
2249 #define CP_COND_EXEC_2_ADDR1_LO__MASK               0xffffffff
2250 #define CP_COND_EXEC_2_ADDR1_LO__SHIFT              0
2251 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
2252 {
2253     return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;
2254 }
2255
2256 #define REG_CP_COND_EXEC_3                  0x00000003
2257 #define CP_COND_EXEC_3_ADDR1_HI__MASK               0xffffffff
2258 #define CP_COND_EXEC_3_ADDR1_HI__SHIFT              0
2259 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
2260 {
2261     return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;
2262 }
2263
2264 #define REG_CP_COND_EXEC_4                  0x00000004
2265 #define CP_COND_EXEC_4_REF__MASK                0xffffffff
2266 #define CP_COND_EXEC_4_REF__SHIFT               0
2267 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
2268 {
2269     return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;
2270 }
2271
2272 #define REG_CP_COND_EXEC_5                  0x00000005
2273 #define CP_COND_EXEC_5_DWORDS__MASK             0xffffffff
2274 #define CP_COND_EXEC_5_DWORDS__SHIFT                0
2275 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
2276 {
2277     return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;
2278 }
2279
2280 #define REG_CP_SET_CTXSWITCH_IB_0               0x00000000
2281 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK         0xffffffff
2282 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT            0
2283 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
2284 {
2285     return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;
2286 }
2287
2288 #define REG_CP_SET_CTXSWITCH_IB_1               0x00000001
2289 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK         0xffffffff
2290 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT            0
2291 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
2292 {
2293     return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;
2294 }
2295
2296 #define REG_CP_SET_CTXSWITCH_IB_2               0x00000002
2297 #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK          0x000fffff
2298 #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT         0
2299 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
2300 {
2301     return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;
2302 }
2303 #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK            0x00300000
2304 #define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT           20
2305 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
2306 {
2307     return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;
2308 }
2309
2310 #define REG_CP_REG_WRITE_0                  0x00000000
2311 #define CP_REG_WRITE_0_TRACKER__MASK                0x00000007
2312 #define CP_REG_WRITE_0_TRACKER__SHIFT               0
2313 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
2314 {
2315     return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
2316 }
2317
2318 #define REG_CP_SMMU_TABLE_UPDATE_0              0x00000000
2319 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK           0xffffffff
2320 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT          0
2321 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
2322 {
2323     return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;
2324 }
2325
2326 #define REG_CP_SMMU_TABLE_UPDATE_1              0x00000001
2327 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK           0x0000ffff
2328 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT          0
2329 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
2330 {
2331     return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;
2332 }
2333 #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK           0xffff0000
2334 #define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT          16
2335 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
2336 {
2337     return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;
2338 }
2339
2340 #define REG_CP_SMMU_TABLE_UPDATE_2              0x00000002
2341 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK         0xffffffff
2342 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT        0
2343 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
2344 {
2345     return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK;
2346 }
2347
2348 #define REG_CP_SMMU_TABLE_UPDATE_3              0x00000003
2349 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK        0xffffffff
2350 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT       0
2351 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
2352 {
2353     return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
2354 }
2355
2356 #define REG_CP_START_BIN_BIN_COUNT              0x00000000
2357
2358 #define REG_CP_START_BIN_PREFIX_ADDR                0x00000001
2359
2360 #define REG_CP_START_BIN_PREFIX_DWORDS              0x00000003
2361
2362 #define REG_CP_START_BIN_BODY_DWORDS                0x00000004
2363
2364
2365 #endif /* ADRENO_PM4_XML */