msm/adreno/adreno_gpu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2013 Red Hat
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  *
0006  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
0007  */
0008
0009 #ifndef __ADRENO_GPU_H__
0010 #define __ADRENO_GPU_H__
0011
0012 #include <linux/firmware.h>
0013 #include <linux/iopoll.h>
0014
0015 #include "msm_gpu.h"
0016
0017 #include "adreno_common.xml.h"
0018 #include "adreno_pm4.xml.h"
0019
0020 extern bool snapshot_debugbus;
0021 extern bool allow_vram_carveout;
0022
0023 enum {
0024     ADRENO_FW_PM4 = 0,
0025     ADRENO_FW_SQE = 0, /* a6xx */
0026     ADRENO_FW_PFP = 1,
0027     ADRENO_FW_GMU = 1, /* a6xx */
0028     ADRENO_FW_GPMU = 2,
0029     ADRENO_FW_MAX,
0030 };
0031
0032 enum adreno_quirks {
0033     ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
0034     ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
0035     ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
0036 };
0037
0038 struct adreno_rev {
0039     uint8_t  core;
0040     uint8_t  major;
0041     uint8_t  minor;
0042     uint8_t  patchid;
0043 };
0044
0045 #define ANY_ID 0xff
0046
0047 #define ADRENO_REV(core, major, minor, patchid) \
0048     ((struct adreno_rev){ core, major, minor, patchid })
0049
0050 struct adreno_gpu_funcs {
0051     struct msm_gpu_funcs base;
0052     int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
0053 };
0054
0055 struct adreno_reglist {
0056     u32 offset;
0057     u32 value;
0058 };
0059
0060 extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
0061
0062 struct adreno_info {
0063     struct adreno_rev rev;
0064     uint32_t revn;
0065     const char *name;
0066     const char *fw[ADRENO_FW_MAX];
0067     uint32_t gmem;
0068     enum adreno_quirks quirks;
0069     struct msm_gpu *(*init)(struct drm_device *dev);
0070     const char *zapfw;
0071     u32 inactive_period;
0072     const struct adreno_reglist *hwcg;
0073     u64 address_space_size;
0074 };
0075
0076 const struct adreno_info *adreno_info(struct adreno_rev rev);
0077
0078 struct adreno_gpu {
0079     struct msm_gpu base;
0080     struct adreno_rev rev;
0081     const struct adreno_info *info;
0082     uint32_t gmem;  /* actual gmem size */
0083     uint32_t revn;  /* numeric revision name */
0084     uint16_t speedbin;
0085     const struct adreno_gpu_funcs *funcs;
0086
0087     /* interesting register offsets to dump: */
0088     const unsigned int *registers;
0089
0090     /*
0091      * Are we loading fw from legacy path?  Prior to addition
0092      * of gpu firmware to linux-firmware, the fw files were
0093      * placed in toplevel firmware directory, following qcom's
0094      * android kernel.  But linux-firmware preferred they be
0095      * placed in a 'qcom' subdirectory.
0096      *
0097      * For backwards compatibility, we try first to load from
0098      * the new path, using request_firmware_direct() to avoid
0099      * any potential timeout waiting for usermode helper, then
0100      * fall back to the old path (with direct load).  And
0101      * finally fall back to request_firmware() with the new
0102      * path to allow the usermode helper.
0103      */
0104     enum {
0105         FW_LOCATION_UNKNOWN = 0,
0106         FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
0107         FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
0108         FW_LOCATION_HELPER,
0109     } fwloc;
0110
0111     /* firmware: */
0112     const struct firmware *fw[ADRENO_FW_MAX];
0113
0114     /*
0115      * Register offsets are different between some GPUs.
0116      * GPU specific offsets will be exported by GPU specific
0117      * code (a3xx_gpu.c) and stored in this common location.
0118      */
0119     const unsigned int *reg_offsets;
0120 };
0121 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
0122
0123 struct adreno_ocmem {
0124     struct ocmem *ocmem;
0125     unsigned long base;
0126     void *hdl;
0127 };
0128
0129 /* platform config data (ie. from DT, or pdata) */
0130 struct adreno_platform_config {
0131     struct adreno_rev rev;
0132 };
0133
0134 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
0135
0136 #define spin_until(X) ({                                   \
0137     int __ret = -ETIMEDOUT;                            \
0138     unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
0139     do {                                               \
0140         if (X) {                                   \
0141             __ret = 0;                         \
0142             break;                             \
0143         }                                          \
0144     } while (time_before(jiffies, __t));               \
0145     __ret;                                             \
0146 })
0147
0148 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
0149
0150 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
0151 {
0152     return (gpu->revn < 300);
0153 }
0154
0155 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
0156 {
0157     return (gpu->revn < 210);
0158 }
0159
0160 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
0161 {
0162     return gpu->revn == 225;
0163 }
0164
0165 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
0166 {
0167     return gpu->revn == 305;
0168 }
0169
0170 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
0171 {
0172     /* yes, 307, because a305c is 306 */
0173     return gpu->revn == 307;
0174 }
0175
0176 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
0177 {
0178     return gpu->revn == 320;
0179 }
0180
0181 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
0182 {
0183     return gpu->revn == 330;
0184 }
0185
0186 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
0187 {
0188     return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
0189 }
0190
0191 static inline int adreno_is_a405(struct adreno_gpu *gpu)
0192 {
0193     return gpu->revn == 405;
0194 }
0195
0196 static inline int adreno_is_a420(struct adreno_gpu *gpu)
0197 {
0198     return gpu->revn == 420;
0199 }
0200
0201 static inline int adreno_is_a430(struct adreno_gpu *gpu)
0202 {
0203     return gpu->revn == 430;
0204 }
0205
0206 static inline int adreno_is_a506(struct adreno_gpu *gpu)
0207 {
0208     return gpu->revn == 506;
0209 }
0210
0211 static inline int adreno_is_a508(struct adreno_gpu *gpu)
0212 {
0213     return gpu->revn == 508;
0214 }
0215
0216 static inline int adreno_is_a509(struct adreno_gpu *gpu)
0217 {
0218     return gpu->revn == 509;
0219 }
0220
0221 static inline int adreno_is_a510(struct adreno_gpu *gpu)
0222 {
0223     return gpu->revn == 510;
0224 }
0225
0226 static inline int adreno_is_a512(struct adreno_gpu *gpu)
0227 {
0228     return gpu->revn == 512;
0229 }
0230
0231 static inline int adreno_is_a530(struct adreno_gpu *gpu)
0232 {
0233     return gpu->revn == 530;
0234 }
0235
0236 static inline int adreno_is_a540(struct adreno_gpu *gpu)
0237 {
0238     return gpu->revn == 540;
0239 }
0240
0241 static inline int adreno_is_a618(struct adreno_gpu *gpu)
0242 {
0243     return gpu->revn == 618;
0244 }
0245
0246 static inline int adreno_is_a619(struct adreno_gpu *gpu)
0247 {
0248     return gpu->revn == 619;
0249 }
0250
0251 static inline int adreno_is_a630(struct adreno_gpu *gpu)
0252 {
0253     return gpu->revn == 630;
0254 }
0255
0256 static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
0257 {
0258     return (gpu->revn == 640) || (gpu->revn == 680);
0259 }
0260
0261 static inline int adreno_is_a650(struct adreno_gpu *gpu)
0262 {
0263     return gpu->revn == 650;
0264 }
0265
0266 static inline int adreno_is_7c3(struct adreno_gpu *gpu)
0267 {
0268     /* The order of args is important here to handle ANY_ID correctly */
0269     return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
0270 }
0271
0272 static inline int adreno_is_a660(struct adreno_gpu *gpu)
0273 {
0274     return gpu->revn == 660;
0275 }
0276
0277 /* check for a615, a616, a618, a619 or any derivatives */
0278 static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
0279 {
0280     return gpu->revn == 615 || gpu->revn == 616 || gpu->revn == 618 || gpu->revn == 619;
0281 }
0282
0283 static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
0284 {
0285     return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
0286 }
0287
0288 /* check for a650, a660, or any derivatives */
0289 static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
0290 {
0291     return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
0292 }
0293
0294 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
0295 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
0296              uint32_t param, uint64_t *value, uint32_t *len);
0297 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
0298              uint32_t param, uint64_t value, uint32_t len);
0299 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
0300         const char *fwname);
0301 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
0302         const struct firmware *fw, u64 *iova);
0303 int adreno_hw_init(struct msm_gpu *gpu);
0304 void adreno_recover(struct msm_gpu *gpu);
0305 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
0306 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
0307 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
0308 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
0309         struct drm_printer *p);
0310 #endif
0311 void adreno_dump_info(struct msm_gpu *gpu);
0312 void adreno_dump(struct msm_gpu *gpu);
0313 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
0314 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
0315
0316 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
0317               struct adreno_ocmem *ocmem);
0318 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
0319
0320 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
0321         struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
0322         int nr_rings);
0323 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
0324 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
0325
0326 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
0327
0328 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
0329 int adreno_gpu_state_put(struct msm_gpu_state *state);
0330 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
0331         bool *encoded);
0332
0333 /*
0334  * Common helper function to initialize the default address space for arm-smmu
0335  * attached targets
0336  */
0337 struct msm_gem_address_space *
0338 adreno_iommu_create_address_space(struct msm_gpu *gpu,
0339         struct platform_device *pdev);
0340
0341 void adreno_set_llc_attributes(struct iommu_domain *iommu);
0342
0343 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
0344
0345 /*
0346  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
0347  * out of secure mode
0348  */
0349 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
0350
0351 /* ringbuffer helpers (the parts that are adreno specific) */
0352
0353 static inline void
0354 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
0355 {
0356     adreno_wait_ring(ring, cnt+1);
0357     OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
0358 }
0359
0360 /* no-op packet: */
0361 static inline void
0362 OUT_PKT2(struct msm_ringbuffer *ring)
0363 {
0364     adreno_wait_ring(ring, 1);
0365     OUT_RING(ring, CP_TYPE2_PKT);
0366 }
0367
0368 static inline void
0369 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
0370 {
0371     adreno_wait_ring(ring, cnt+1);
0372     OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
0373 }
0374
0375 static inline u32 PM4_PARITY(u32 val)
0376 {
0377     return (0x9669 >> (0xF & (val ^
0378         (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
0379         (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
0380         (val >> 28)))) & 1;
0381 }
0382
0383 /* Maximum number of values that can be executed for one opcode */
0384 #define TYPE4_MAX_PAYLOAD 127
0385
0386 #define PKT4(_reg, _cnt) \
0387     (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
0388      (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
0389
0390 static inline void
0391 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
0392 {
0393     adreno_wait_ring(ring, cnt + 1);
0394     OUT_RING(ring, PKT4(regindx, cnt));
0395 }
0396
0397 static inline void
0398 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
0399 {
0400     adreno_wait_ring(ring, cnt + 1);
0401     OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
0402         ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
0403 }
0404
0405 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
0406 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
0407 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
0408 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
0409 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
0410
0411 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
0412 {
0413     return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
0414 }
0415
0416 /*
0417  * Given a register and a count, return a value to program into
0418  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
0419  * registers starting at _reg.
0420  *
0421  * The register base needs to be a multiple of the length. If it is not, the
0422  * hardware will quietly mask off the bits for you and shift the size. For
0423  * example, if you intend the protection to start at 0x07 for a length of 4
0424  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
0425  * expose registers you intended to protect!
0426  */
0427 #define ADRENO_PROTECT_RW(_reg, _len) \
0428     ((1 << 30) | (1 << 29) | \
0429     ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
0430
0431 /*
0432  * Same as above, but allow reads over the range. For areas of mixed use (such
0433  * as performance counters) this allows us to protect a much larger range with a
0434  * single register
0435  */
0436 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
0437     ((1 << 29) \
0438     ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
0439
0440
0441 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
0442     readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
0443         interval, timeout)
0444
0445 #endif /* __ADRENO_GPU_H__ */