msm/adreno/a6xx_hfi.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
0003
0004 #ifndef _A6XX_HFI_H_
0005 #define _A6XX_HFI_H_
0006
0007 struct a6xx_hfi_queue_table_header {
0008     u32 version;
0009     u32 size;       /* Size of the queue table in dwords */
0010     u32 qhdr0_offset;   /* Offset of the first queue header */
0011     u32 qhdr_size;      /* Size of the queue headers */
0012     u32 num_queues;     /* Number of total queues */
0013     u32 active_queues;  /* Number of active queues */
0014 };
0015
0016 struct a6xx_hfi_queue_header {
0017     u32 status;
0018     u32 iova;
0019     u32 type;
0020     u32 size;
0021     u32 msg_size;
0022     u32 dropped;
0023     u32 rx_watermark;
0024     u32 tx_watermark;
0025     u32 rx_request;
0026     u32 tx_request;
0027     u32 read_index;
0028     u32 write_index;
0029 };
0030
0031 struct a6xx_hfi_queue {
0032     struct a6xx_hfi_queue_header *header;
0033     spinlock_t lock;
0034     u32 *data;
0035     atomic_t seqnum;
0036
0037     /*
0038      * Tracking for the start index of the last N messages in the
0039      * queue, for the benefit of devcore dump / crashdec (since
0040      * parsing in the reverse direction to decode the last N
0041      * messages is difficult to do and would rely on heuristics
0042      * which are not guaranteed to be correct)
0043      */
0044 #define HFI_HISTORY_SZ 8
0045     s32 history[HFI_HISTORY_SZ];
0046     u8  history_idx;
0047 };
0048
0049 /* This is the outgoing queue to the GMU */
0050 #define HFI_COMMAND_QUEUE 0
0051
0052 /* THis is the incoming response queue from the GMU */
0053 #define HFI_RESPONSE_QUEUE 1
0054
0055 #define HFI_HEADER_ID(msg) ((msg) & 0xff)
0056 #define HFI_HEADER_SIZE(msg) (((msg) >> 8) & 0xff)
0057 #define HFI_HEADER_SEQNUM(msg) (((msg) >> 20) & 0xfff)
0058
0059 /* FIXME: Do we need this or can we use ARRAY_SIZE? */
0060 #define HFI_RESPONSE_PAYLOAD_SIZE 16
0061
0062 /* HFI message types */
0063
0064 #define HFI_MSG_CMD 0
0065 #define HFI_MSG_ACK 1
0066 #define HFI_MSG_ACK_V1 2
0067
0068 #define HFI_F2H_MSG_ACK 126
0069
0070 struct a6xx_hfi_msg_response {
0071     u32 header;
0072     u32 ret_header;
0073     u32 error;
0074     u32 payload[HFI_RESPONSE_PAYLOAD_SIZE];
0075 };
0076
0077 #define HFI_F2H_MSG_ERROR 100
0078
0079 struct a6xx_hfi_msg_error {
0080     u32 header;
0081     u32 code;
0082     u32 payload[2];
0083 };
0084
0085 #define HFI_H2F_MSG_INIT 0
0086
0087 struct a6xx_hfi_msg_gmu_init_cmd {
0088     u32 header;
0089     u32 seg_id;
0090     u32 dbg_buffer_addr;
0091     u32 dbg_buffer_size;
0092     u32 boot_state;
0093 };
0094
0095 #define HFI_H2F_MSG_FW_VERSION 1
0096
0097 struct a6xx_hfi_msg_fw_version {
0098     u32 header;
0099     u32 supported_version;
0100 };
0101
0102 #define HFI_H2F_MSG_PERF_TABLE 4
0103
0104 struct perf_level {
0105     u32 vote;
0106     u32 freq;
0107 };
0108
0109 struct perf_gx_level {
0110     u32 vote;
0111     u32 acd;
0112     u32 freq;
0113 };
0114
0115 struct a6xx_hfi_msg_perf_table_v1 {
0116     u32 header;
0117     u32 num_gpu_levels;
0118     u32 num_gmu_levels;
0119
0120     struct perf_level gx_votes[16];
0121     struct perf_level cx_votes[4];
0122 };
0123
0124 struct a6xx_hfi_msg_perf_table {
0125     u32 header;
0126     u32 num_gpu_levels;
0127     u32 num_gmu_levels;
0128
0129     struct perf_gx_level gx_votes[16];
0130     struct perf_level cx_votes[4];
0131 };
0132
0133 #define HFI_H2F_MSG_BW_TABLE 3
0134
0135 struct a6xx_hfi_msg_bw_table {
0136     u32 header;
0137     u32 bw_level_num;
0138     u32 cnoc_cmds_num;
0139     u32 ddr_cmds_num;
0140     u32 cnoc_wait_bitmask;
0141     u32 ddr_wait_bitmask;
0142     u32 cnoc_cmds_addrs[6];
0143     u32 cnoc_cmds_data[2][6];
0144     u32 ddr_cmds_addrs[8];
0145     u32 ddr_cmds_data[16][8];
0146 };
0147
0148 #define HFI_H2F_MSG_TEST 5
0149
0150 struct a6xx_hfi_msg_test {
0151     u32 header;
0152 };
0153
0154 #define HFI_H2F_MSG_START 10
0155
0156 struct a6xx_hfi_msg_start {
0157     u32 header;
0158 };
0159
0160 #define HFI_H2F_MSG_CORE_FW_START 14
0161
0162 struct a6xx_hfi_msg_core_fw_start {
0163     u32 header;
0164     u32 handle;
0165 };
0166
0167 #define HFI_H2F_MSG_GX_BW_PERF_VOTE 30
0168
0169 struct a6xx_hfi_gx_bw_perf_vote_cmd {
0170     u32 header;
0171     u32 ack_type;
0172     u32 freq;
0173     u32 bw;
0174 };
0175
0176 #define HFI_H2F_MSG_PREPARE_SLUMBER 33
0177
0178 struct a6xx_hfi_prep_slumber_cmd {
0179     u32 header;
0180     u32 bw;
0181     u32 freq;
0182 };
0183
0184 #endif