msm/adreno/a6xx_gpu_state.h

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
0003
0004 #ifndef _A6XX_CRASH_DUMP_H_
0005 #define _A6XX_CRASH_DUMP_H_
0006
0007 #include "a6xx.xml.h"
0008
0009 #define A6XX_NUM_CONTEXTS 2
0010 #define A6XX_NUM_SHADER_BANKS 3
0011
0012 static const u32 a6xx_gras_cluster[] = {
0013     0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
0014     0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
0015     0x8400, 0x840b,
0016 };
0017
0018 static const u32 a6xx_ps_cluster_rac[] = {
0019     0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
0020     0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
0021     0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
0022     0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
0023 };
0024
0025 static const u32 a6xx_ps_cluster_rbp[] = {
0026     0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
0027     0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
0028 };
0029
0030 static const u32 a6xx_ps_cluster[] = {
0031     0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
0032 };
0033
0034 static const u32 a6xx_fe_cluster[] = {
0035     0x9300, 0x9306, 0x9800, 0x9806, 0x9b00, 0x9b07, 0xa000, 0xa009,
0036     0xa00e, 0xa0ef, 0xa0f8, 0xa0f8,
0037 };
0038
0039 static const u32 a6xx_pc_vs_cluster[] = {
0040     0x9100, 0x9108, 0x9300, 0x9306, 0x9980, 0x9981, 0x9b00, 0x9b07,
0041 };
0042
0043 #define CLUSTER_FE    0
0044 #define CLUSTER_SP_VS 1
0045 #define CLUSTER_PC_VS 2
0046 #define CLUSTER_GRAS  3
0047 #define CLUSTER_SP_PS 4
0048 #define CLUSTER_PS    5
0049
0050 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
0051     { .id = _id, .name = #_id,\
0052         .registers = _reg, \
0053         .count = ARRAY_SIZE(_reg), \
0054         .sel_reg = _sel_reg, .sel_val = _sel_val }
0055
0056 static const struct a6xx_cluster {
0057     u32 id;
0058     const char *name;
0059     const u32 *registers;
0060     size_t count;
0061     u32 sel_reg;
0062     u32 sel_val;
0063 } a6xx_clusters[] = {
0064     CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0),
0065     CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
0066     CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
0067     CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0),
0068     CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0),
0069     CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0),
0070 };
0071
0072 static const u32 a6xx_sp_vs_hlsq_cluster[] = {
0073     0xb800, 0xb803, 0xb820, 0xb822,
0074 };
0075
0076 static const u32 a6xx_sp_vs_sp_cluster[] = {
0077     0xa800, 0xa824, 0xa830, 0xa83c, 0xa840, 0xa864, 0xa870, 0xa895,
0078     0xa8a0, 0xa8af, 0xa8c0, 0xa8c3,
0079 };
0080
0081 static const u32 a6xx_hlsq_duplicate_cluster[] = {
0082     0xbb10, 0xbb11, 0xbb20, 0xbb29,
0083 };
0084
0085 static const u32 a6xx_hlsq_2d_duplicate_cluster[] = {
0086     0xbd80, 0xbd80,
0087 };
0088
0089 static const u32 a6xx_sp_duplicate_cluster[] = {
0090     0xab00, 0xab00, 0xab04, 0xab05, 0xab10, 0xab1b, 0xab20, 0xab20,
0091 };
0092
0093 static const u32 a6xx_tp_duplicate_cluster[] = {
0094     0xb300, 0xb307, 0xb309, 0xb309, 0xb380, 0xb382,
0095 };
0096
0097 static const u32 a6xx_sp_ps_hlsq_cluster[] = {
0098     0xb980, 0xb980, 0xb982, 0xb987, 0xb990, 0xb99b, 0xb9a0, 0xb9a2,
0099     0xb9c0, 0xb9c9,
0100 };
0101
0102 static const u32 a6xx_sp_ps_hlsq_2d_cluster[] = {
0103     0xbd80, 0xbd80,
0104 };
0105
0106 static const u32 a6xx_sp_ps_sp_cluster[] = {
0107     0xa980, 0xa9a8, 0xa9b0, 0xa9bc, 0xa9d0, 0xa9d3, 0xa9e0, 0xa9f3,
0108     0xaa00, 0xaa00, 0xaa30, 0xaa31,
0109 };
0110
0111 static const u32 a6xx_sp_ps_sp_2d_cluster[] = {
0112     0xacc0, 0xacc0,
0113 };
0114
0115 static const u32 a6xx_sp_ps_tp_cluster[] = {
0116     0xb180, 0xb183, 0xb190, 0xb191,
0117 };
0118
0119 static const u32 a6xx_sp_ps_tp_2d_cluster[] = {
0120     0xb4c0, 0xb4d1,
0121 };
0122
0123 #define CLUSTER_DBGAHB(_id, _base, _type, _reg) \
0124     { .name = #_id, .statetype = _type, .base = _base, \
0125         .registers = _reg, .count = ARRAY_SIZE(_reg) }
0126
0127 static const struct a6xx_dbgahb_cluster {
0128     const char *name;
0129     u32 statetype;
0130     u32 base;
0131     const u32 *registers;
0132     size_t count;
0133 } a6xx_dbgahb_clusters[] = {
0134     CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002e000, 0x41, a6xx_sp_vs_hlsq_cluster),
0135     CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002a000, 0x21, a6xx_sp_vs_sp_cluster),
0136     CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002e000, 0x41, a6xx_hlsq_duplicate_cluster),
0137     CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002f000, 0x45, a6xx_hlsq_2d_duplicate_cluster),
0138     CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002a000, 0x21, a6xx_sp_duplicate_cluster),
0139     CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002c000, 0x1, a6xx_tp_duplicate_cluster),
0140     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002e000, 0x42, a6xx_sp_ps_hlsq_cluster),
0141     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002f000, 0x46, a6xx_sp_ps_hlsq_2d_cluster),
0142     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002a000, 0x22, a6xx_sp_ps_sp_cluster),
0143     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002b000, 0x26, a6xx_sp_ps_sp_2d_cluster),
0144     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002c000, 0x2, a6xx_sp_ps_tp_cluster),
0145     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002d000, 0x6, a6xx_sp_ps_tp_2d_cluster),
0146     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002e000, 0x42, a6xx_hlsq_duplicate_cluster),
0147     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002a000, 0x22, a6xx_sp_duplicate_cluster),
0148     CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002c000, 0x2, a6xx_tp_duplicate_cluster),
0149 };
0150
0151 static const u32 a6xx_hlsq_registers[] = {
0152     0xbe00, 0xbe01, 0xbe04, 0xbe05, 0xbe08, 0xbe09, 0xbe10, 0xbe15,
0153     0xbe20, 0xbe23,
0154 };
0155
0156 static const u32 a6xx_sp_registers[] = {
0157     0xae00, 0xae04, 0xae0c, 0xae0c, 0xae0f, 0xae2b, 0xae30, 0xae32,
0158     0xae35, 0xae35, 0xae3a, 0xae3f, 0xae50, 0xae52,
0159 };
0160
0161 static const u32 a6xx_tp_registers[] = {
0162     0xb600, 0xb601, 0xb604, 0xb605, 0xb610, 0xb61b, 0xb620, 0xb623,
0163 };
0164
0165 struct a6xx_registers {
0166     const u32 *registers;
0167     size_t count;
0168     u32 val0;
0169     u32 val1;
0170 };
0171
0172 #define HLSQ_DBG_REGS(_base, _type, _array) \
0173     { .val0 = _base, .val1 = _type, .registers = _array, \
0174         .count = ARRAY_SIZE(_array), }
0175
0176 static const struct a6xx_registers a6xx_hlsq_reglist[] = {
0177     HLSQ_DBG_REGS(0x0002F800, 0x40, a6xx_hlsq_registers),
0178     HLSQ_DBG_REGS(0x0002B800, 0x20, a6xx_sp_registers),
0179     HLSQ_DBG_REGS(0x0002D800, 0x0, a6xx_tp_registers),
0180 };
0181
0182 #define SHADER(_type, _size) \
0183     { .type = _type, .name = #_type, .size = _size }
0184
0185 static const struct a6xx_shader_block {
0186     const char *name;
0187     u32 type;
0188     u32 size;
0189 } a6xx_shader_blocks[] = {
0190     SHADER(A6XX_TP0_TMO_DATA, 0x200),
0191     SHADER(A6XX_TP0_SMO_DATA, 0x80),
0192     SHADER(A6XX_TP0_MIPMAP_BASE_DATA, 0x3c0),
0193     SHADER(A6XX_TP1_TMO_DATA, 0x200),
0194     SHADER(A6XX_TP1_SMO_DATA, 0x80),
0195     SHADER(A6XX_TP1_MIPMAP_BASE_DATA, 0x3c0),
0196     SHADER(A6XX_SP_INST_DATA, 0x800),
0197     SHADER(A6XX_SP_LB_0_DATA, 0x800),
0198     SHADER(A6XX_SP_LB_1_DATA, 0x800),
0199     SHADER(A6XX_SP_LB_2_DATA, 0x800),
0200     SHADER(A6XX_SP_LB_3_DATA, 0x800),
0201     SHADER(A6XX_SP_LB_4_DATA, 0x800),
0202     SHADER(A6XX_SP_LB_5_DATA, 0x200),
0203     SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x2000),
0204     SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
0205     SHADER(A6XX_SP_UAV_DATA, 0x80),
0206     SHADER(A6XX_SP_INST_TAG, 0x80),
0207     SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80),
0208     SHADER(A6XX_SP_TMO_UMO_TAG, 0x80),
0209     SHADER(A6XX_SP_SMO_TAG, 0x80),
0210     SHADER(A6XX_SP_STATE_DATA, 0x3f),
0211     SHADER(A6XX_HLSQ_CHUNK_CVS_RAM, 0x1c0),
0212     SHADER(A6XX_HLSQ_CHUNK_CPS_RAM, 0x280),
0213     SHADER(A6XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40),
0214     SHADER(A6XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40),
0215     SHADER(A6XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x4),
0216     SHADER(A6XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x4),
0217     SHADER(A6XX_HLSQ_CVS_MISC_RAM, 0x1c0),
0218     SHADER(A6XX_HLSQ_CPS_MISC_RAM, 0x580),
0219     SHADER(A6XX_HLSQ_INST_RAM, 0x800),
0220     SHADER(A6XX_HLSQ_GFX_CVS_CONST_RAM, 0x800),
0221     SHADER(A6XX_HLSQ_GFX_CPS_CONST_RAM, 0x800),
0222     SHADER(A6XX_HLSQ_CVS_MISC_RAM_TAG, 0x8),
0223     SHADER(A6XX_HLSQ_CPS_MISC_RAM_TAG, 0x4),
0224     SHADER(A6XX_HLSQ_INST_RAM_TAG, 0x80),
0225     SHADER(A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0xc),
0226     SHADER(A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10),
0227     SHADER(A6XX_HLSQ_PWR_REST_RAM, 0x28),
0228     SHADER(A6XX_HLSQ_PWR_REST_TAG, 0x14),
0229     SHADER(A6XX_HLSQ_DATAPATH_META, 0x40),
0230     SHADER(A6XX_HLSQ_FRONTEND_META, 0x40),
0231     SHADER(A6XX_HLSQ_INDIRECT_META, 0x40),
0232 };
0233
0234 static const u32 a6xx_rb_rac_registers[] = {
0235     0x8e04, 0x8e05, 0x8e07, 0x8e08, 0x8e10, 0x8e1c, 0x8e20, 0x8e25,
0236     0x8e28, 0x8e28, 0x8e2c, 0x8e2f, 0x8e50, 0x8e52,
0237 };
0238
0239 static const u32 a6xx_rb_rbp_registers[] = {
0240     0x8e01, 0x8e01, 0x8e0c, 0x8e0c, 0x8e3b, 0x8e3e, 0x8e40, 0x8e43,
0241     0x8e53, 0x8e5f, 0x8e70, 0x8e77,
0242 };
0243
0244 static const u32 a6xx_registers[] = {
0245     /* RBBM */
0246     0x0000, 0x0002, 0x0010, 0x0010, 0x0012, 0x0012, 0x0018, 0x001b,
0247     0x001e, 0x0032, 0x0038, 0x003c, 0x0042, 0x0042, 0x0044, 0x0044,
0248     0x0047, 0x0047, 0x0056, 0x0056, 0x00ad, 0x00ae, 0x00b0, 0x00fb,
0249     0x0100, 0x011d, 0x0200, 0x020d, 0x0218, 0x023d, 0x0400, 0x04f9,
0250     0x0500, 0x0500, 0x0505, 0x050b, 0x050e, 0x0511, 0x0533, 0x0533,
0251     0x0540, 0x0555,
0252     /* CP */
0253     0x0800, 0x0808, 0x0810, 0x0813, 0x0820, 0x0821, 0x0823, 0x0824,
0254     0x0826, 0x0827, 0x0830, 0x0833, 0x0840, 0x0843, 0x084f, 0x086f,
0255     0x0880, 0x088a, 0x08a0, 0x08ab, 0x08c0, 0x08c4, 0x08d0, 0x08dd,
0256     0x08f0, 0x08f3, 0x0900, 0x0903, 0x0908, 0x0911, 0x0928, 0x093e,
0257     0x0942, 0x094d, 0x0980, 0x0984, 0x098d, 0x0996, 0x0998, 0x099e,
0258     0x09a0, 0x09a6, 0x09a8, 0x09ae, 0x09b0, 0x09b1, 0x09c2, 0x09c8,
0259     0x0a00, 0x0a03,
0260     /* VSC */
0261     0x0c00, 0x0c04, 0x0c06, 0x0c06, 0x0c10, 0x0cd9, 0x0e00, 0x0e0e,
0262     /* UCHE */
0263     0x0e10, 0x0e13, 0x0e17, 0x0e19, 0x0e1c, 0x0e2b, 0x0e30, 0x0e32,
0264     0x0e38, 0x0e39,
0265     /* GRAS */
0266     0x8600, 0x8601, 0x8610, 0x861b, 0x8620, 0x8620, 0x8628, 0x862b,
0267     0x8630, 0x8637,
0268     /* VPC */
0269     0x9600, 0x9604, 0x9624, 0x9637,
0270     /* PC */
0271     0x9e00, 0x9e01, 0x9e03, 0x9e0e, 0x9e11, 0x9e16, 0x9e19, 0x9e19,
0272     0x9e1c, 0x9e1c, 0x9e20, 0x9e23, 0x9e30, 0x9e31, 0x9e34, 0x9e34,
0273     0x9e70, 0x9e72, 0x9e78, 0x9e79, 0x9e80, 0x9fff,
0274     /* VFD */
0275     0xa600, 0xa601, 0xa603, 0xa603, 0xa60a, 0xa60a, 0xa610, 0xa617,
0276     0xa630, 0xa630,
0277 };
0278
0279 #define REGS(_array, _sel_reg, _sel_val) \
0280     { .registers = _array, .count = ARRAY_SIZE(_array), \
0281         .val0 = _sel_reg, .val1 = _sel_val }
0282
0283 static const struct a6xx_registers a6xx_reglist[] = {
0284     REGS(a6xx_registers, 0, 0),
0285     REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
0286     REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
0287 };
0288
0289 static const u32 a6xx_ahb_registers[] = {
0290     /* RBBM_STATUS - RBBM_STATUS3 */
0291     0x210, 0x213,
0292     /* CP_STATUS_1 */
0293     0x825, 0x825,
0294 };
0295
0296 static const u32 a6xx_vbif_registers[] = {
0297     0x3000, 0x3007, 0x300c, 0x3014, 0x3018, 0x302d, 0x3030, 0x3031,
0298     0x3034, 0x3036, 0x303c, 0x303d, 0x3040, 0x3040, 0x3042, 0x3042,
0299     0x3049, 0x3049, 0x3058, 0x3058, 0x305a, 0x3061, 0x3064, 0x3068,
0300     0x306c, 0x306d, 0x3080, 0x3088, 0x308b, 0x308c, 0x3090, 0x3094,
0301     0x3098, 0x3098, 0x309c, 0x309c, 0x30c0, 0x30c0, 0x30c8, 0x30c8,
0302     0x30d0, 0x30d0, 0x30d8, 0x30d8, 0x30e0, 0x30e0, 0x3100, 0x3100,
0303     0x3108, 0x3108, 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120,
0304     0x3124, 0x3125, 0x3129, 0x3129, 0x3131, 0x3131, 0x3154, 0x3154,
0305     0x3156, 0x3156, 0x3158, 0x3158, 0x315a, 0x315a, 0x315c, 0x315c,
0306     0x315e, 0x315e, 0x3160, 0x3160, 0x3162, 0x3162, 0x340c, 0x340c,
0307     0x3410, 0x3410, 0x3800, 0x3801,
0308 };
0309
0310 static const u32 a6xx_gbif_registers[] = {
0311     0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A,
0312 };
0313
0314 static const struct a6xx_registers a6xx_ahb_reglist[] = {
0315     REGS(a6xx_ahb_registers, 0, 0),
0316 };
0317
0318 static const struct a6xx_registers a6xx_vbif_reglist =
0319             REGS(a6xx_vbif_registers, 0, 0);
0320
0321 static const struct a6xx_registers a6xx_gbif_reglist =
0322             REGS(a6xx_gbif_registers, 0, 0);
0323
0324 static const u32 a6xx_gmu_gx_registers[] = {
0325     /* GMU GX */
0326     0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
0327     0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b,
0328     0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b,
0329     0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084,
0330     0x0100, 0x012b, 0x0140, 0x0140,
0331 };
0332
0333 static const u32 a6xx_gmu_cx_registers[] = {
0334     /* GMU CX */
0335     0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a,
0336     0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c,
0337     0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089,
0338     0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0,
0339     0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140,
0340     0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154,
0341     0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,
0342     0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,
0343     0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
0344     /* GMU AO */
0345     0x9300, 0x9316, 0x9400, 0x9400,
0346     /* GPU CC */
0347     0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
0348     0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
0349     0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002,
0350     0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402,
0351     0xb800, 0xb802,
0352     /* GPU CC ACD */
0353     0xbc00, 0xbc16, 0xbc20, 0xbc27,
0354 };
0355
0356 static const u32 a6xx_gmu_cx_rscc_registers[] = {
0357     /* GPU RSCC */
0358     0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347,
0359     0x034c, 0x0387, 0x03ec, 0x03ef, 0x03f4, 0x042f, 0x0494, 0x0497,
0360     0x049c, 0x04d7, 0x053c, 0x053f, 0x0544, 0x057f,
0361 };
0362
0363 static const struct a6xx_registers a6xx_gmu_reglist[] = {
0364     REGS(a6xx_gmu_cx_registers, 0, 0),
0365     REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
0366     REGS(a6xx_gmu_gx_registers, 0, 0),
0367 };
0368
0369 static const struct a6xx_indexed_registers {
0370     const char *name;
0371     u32 addr;
0372     u32 data;
0373     u32 count;
0374 } a6xx_indexed_reglist[] = {
0375     { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
0376         REG_A6XX_CP_SQE_STAT_DATA, 0x33 },
0377     { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
0378         REG_A6XX_CP_DRAW_STATE_DATA, 0x100 },
0379     { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
0380         REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x6000 },
0381     { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
0382         REG_A6XX_CP_ROQ_DBG_DATA, 0x400 },
0383 };
0384
0385 static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
0386     "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
0387         REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060,
0388 };
0389
0390 #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }
0391
0392 static const struct a6xx_debugbus_block {
0393     const char *name;
0394     u32 id;
0395     u32 count;
0396 } a6xx_debugbus_blocks[] = {
0397     DEBUGBUS(A6XX_DBGBUS_CP, 0x100),
0398     DEBUGBUS(A6XX_DBGBUS_RBBM, 0x100),
0399     DEBUGBUS(A6XX_DBGBUS_HLSQ, 0x100),
0400     DEBUGBUS(A6XX_DBGBUS_UCHE, 0x100),
0401     DEBUGBUS(A6XX_DBGBUS_DPM, 0x100),
0402     DEBUGBUS(A6XX_DBGBUS_TESS, 0x100),
0403     DEBUGBUS(A6XX_DBGBUS_PC, 0x100),
0404     DEBUGBUS(A6XX_DBGBUS_VFDP, 0x100),
0405     DEBUGBUS(A6XX_DBGBUS_VPC, 0x100),
0406     DEBUGBUS(A6XX_DBGBUS_TSE, 0x100),
0407     DEBUGBUS(A6XX_DBGBUS_RAS, 0x100),
0408     DEBUGBUS(A6XX_DBGBUS_VSC, 0x100),
0409     DEBUGBUS(A6XX_DBGBUS_COM, 0x100),
0410     DEBUGBUS(A6XX_DBGBUS_LRZ, 0x100),
0411     DEBUGBUS(A6XX_DBGBUS_A2D, 0x100),
0412     DEBUGBUS(A6XX_DBGBUS_CCUFCHE, 0x100),
0413     DEBUGBUS(A6XX_DBGBUS_RBP, 0x100),
0414     DEBUGBUS(A6XX_DBGBUS_DCS, 0x100),
0415     DEBUGBUS(A6XX_DBGBUS_DBGC, 0x100),
0416     DEBUGBUS(A6XX_DBGBUS_GMU_GX, 0x100),
0417     DEBUGBUS(A6XX_DBGBUS_TPFCHE, 0x100),
0418     DEBUGBUS(A6XX_DBGBUS_GPC, 0x100),
0419     DEBUGBUS(A6XX_DBGBUS_LARC, 0x100),
0420     DEBUGBUS(A6XX_DBGBUS_HLSQ_SPTP, 0x100),
0421     DEBUGBUS(A6XX_DBGBUS_RB_0, 0x100),
0422     DEBUGBUS(A6XX_DBGBUS_RB_1, 0x100),
0423     DEBUGBUS(A6XX_DBGBUS_UCHE_WRAPPER, 0x100),
0424     DEBUGBUS(A6XX_DBGBUS_CCU_0, 0x100),
0425     DEBUGBUS(A6XX_DBGBUS_CCU_1, 0x100),
0426     DEBUGBUS(A6XX_DBGBUS_VFD_0, 0x100),
0427     DEBUGBUS(A6XX_DBGBUS_VFD_1, 0x100),
0428     DEBUGBUS(A6XX_DBGBUS_VFD_2, 0x100),
0429     DEBUGBUS(A6XX_DBGBUS_VFD_3, 0x100),
0430     DEBUGBUS(A6XX_DBGBUS_SP_0, 0x100),
0431     DEBUGBUS(A6XX_DBGBUS_SP_1, 0x100),
0432     DEBUGBUS(A6XX_DBGBUS_TPL1_0, 0x100),
0433     DEBUGBUS(A6XX_DBGBUS_TPL1_1, 0x100),
0434     DEBUGBUS(A6XX_DBGBUS_TPL1_2, 0x100),
0435     DEBUGBUS(A6XX_DBGBUS_TPL1_3, 0x100),
0436 };
0437
0438 static const struct a6xx_debugbus_block a6xx_gbif_debugbus_block =
0439             DEBUGBUS(A6XX_DBGBUS_VBIF, 0x100);
0440
0441 static const struct a6xx_debugbus_block a6xx_cx_debugbus_blocks[] = {
0442     DEBUGBUS(A6XX_DBGBUS_GMU_CX, 0x100),
0443     DEBUGBUS(A6XX_DBGBUS_CX, 0x100),
0444 };
0445
0446 #endif