msm/adreno/a6xx_gpu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
0003
0004 #ifndef __A6XX_GPU_H__
0005 #define __A6XX_GPU_H__
0006
0007
0008 #include "adreno_gpu.h"
0009 #include "a6xx.xml.h"
0010
0011 #include "a6xx_gmu.h"
0012
0013 extern bool hang_debug;
0014
0015 struct a6xx_gpu {
0016     struct adreno_gpu base;
0017
0018     struct drm_gem_object *sqe_bo;
0019     uint64_t sqe_iova;
0020
0021     struct msm_ringbuffer *cur_ring;
0022
0023     struct a6xx_gmu gmu;
0024
0025     struct drm_gem_object *shadow_bo;
0026     uint64_t shadow_iova;
0027     uint32_t *shadow;
0028
0029     bool has_whereami;
0030
0031     void __iomem *llc_mmio;
0032     void *llc_slice;
0033     void *htw_llc_slice;
0034     bool have_mmu500;
0035 };
0036
0037 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
0038
0039 /*
0040  * Given a register and a count, return a value to program into
0041  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
0042  * registers starting at _reg.
0043  */
0044 #define A6XX_PROTECT_NORDWR(_reg, _len) \
0045     ((1 << 31) | \
0046     (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
0047
0048 /*
0049  * Same as above, but allow reads over the range. For areas of mixed use (such
0050  * as performance counters) this allows us to protect a much larger range with a
0051  * single register
0052  */
0053 #define A6XX_PROTECT_RDONLY(_reg, _len) \
0054     ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
0055
0056 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
0057 {
0058     if(adreno_is_a630(gpu))
0059         return false;
0060
0061     return true;
0062 }
0063
0064 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
0065         ((_ring)->id * sizeof(uint32_t)))
0066
0067 int a6xx_gmu_resume(struct a6xx_gpu *gpu);
0068 int a6xx_gmu_stop(struct a6xx_gpu *gpu);
0069
0070 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
0071
0072 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
0073
0074 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
0075 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
0076
0077 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
0078 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
0079
0080 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
0081                bool suspended);
0082 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
0083
0084 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
0085         struct drm_printer *p);
0086
0087 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
0088 int a6xx_gpu_state_put(struct msm_gpu_state *state);
0089
0090 #endif /* __A6XX_GPU_H__ */