msm/adreno/a6xx.xml.h

0001 #ifndef A6XX_XML
0002 #define A6XX_XML
0003
0004 /* Autogenerated file, DO NOT EDIT manually!
0005
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-01-30 18:25:22)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-06-21 15:24:24)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14609 bytes, from 2021-11-24 23:05:10)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  69086 bytes, from 2022-03-03 16:41:33)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2021-11-24 23:05:10)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113358 bytes, from 2022-01-31 23:06:21)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149512 bytes, from 2022-01-31 23:06:21)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 184954 bytes, from 2022-03-03 16:41:33)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-01-30 18:25:22)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-07-22 15:21:56)
0024
0025 Copyright (C) 2013-2022 by the following authors:
0026 - Rob Clark <robdclark@gmail.com> (robclark)
0027 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0028
0029 Permission is hereby granted, free of charge, to any person obtaining
0030 a copy of this software and associated documentation files (the
0031 "Software"), to deal in the Software without restriction, including
0032 without limitation the rights to use, copy, modify, merge, publish,
0033 distribute, sublicense, and/or sell copies of the Software, and to
0034 permit persons to whom the Software is furnished to do so, subject to
0035 the following conditions:
0036
0037 The above copyright notice and this permission notice (including the
0038 next paragraph) shall be included in all copies or substantial
0039 portions of the Software.
0040
0041 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0042 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0043 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0044 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0045 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0046 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0047 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0048 */
0049
0050
0051 enum a6xx_tile_mode {
0052     TILE6_LINEAR = 0,
0053     TILE6_2 = 2,
0054     TILE6_3 = 3,
0055 };
0056
0057 enum a6xx_format {
0058     FMT6_A8_UNORM = 2,
0059     FMT6_8_UNORM = 3,
0060     FMT6_8_SNORM = 4,
0061     FMT6_8_UINT = 5,
0062     FMT6_8_SINT = 6,
0063     FMT6_4_4_4_4_UNORM = 8,
0064     FMT6_5_5_5_1_UNORM = 10,
0065     FMT6_1_5_5_5_UNORM = 12,
0066     FMT6_5_6_5_UNORM = 14,
0067     FMT6_8_8_UNORM = 15,
0068     FMT6_8_8_SNORM = 16,
0069     FMT6_8_8_UINT = 17,
0070     FMT6_8_8_SINT = 18,
0071     FMT6_L8_A8_UNORM = 19,
0072     FMT6_16_UNORM = 21,
0073     FMT6_16_SNORM = 22,
0074     FMT6_16_FLOAT = 23,
0075     FMT6_16_UINT = 24,
0076     FMT6_16_SINT = 25,
0077     FMT6_8_8_8_UNORM = 33,
0078     FMT6_8_8_8_SNORM = 34,
0079     FMT6_8_8_8_UINT = 35,
0080     FMT6_8_8_8_SINT = 36,
0081     FMT6_8_8_8_8_UNORM = 48,
0082     FMT6_8_8_8_X8_UNORM = 49,
0083     FMT6_8_8_8_8_SNORM = 50,
0084     FMT6_8_8_8_8_UINT = 51,
0085     FMT6_8_8_8_8_SINT = 52,
0086     FMT6_9_9_9_E5_FLOAT = 53,
0087     FMT6_10_10_10_2_UNORM = 54,
0088     FMT6_10_10_10_2_UNORM_DEST = 55,
0089     FMT6_10_10_10_2_SNORM = 57,
0090     FMT6_10_10_10_2_UINT = 58,
0091     FMT6_10_10_10_2_SINT = 59,
0092     FMT6_11_11_10_FLOAT = 66,
0093     FMT6_16_16_UNORM = 67,
0094     FMT6_16_16_SNORM = 68,
0095     FMT6_16_16_FLOAT = 69,
0096     FMT6_16_16_UINT = 70,
0097     FMT6_16_16_SINT = 71,
0098     FMT6_32_UNORM = 72,
0099     FMT6_32_SNORM = 73,
0100     FMT6_32_FLOAT = 74,
0101     FMT6_32_UINT = 75,
0102     FMT6_32_SINT = 76,
0103     FMT6_32_FIXED = 77,
0104     FMT6_16_16_16_UNORM = 88,
0105     FMT6_16_16_16_SNORM = 89,
0106     FMT6_16_16_16_FLOAT = 90,
0107     FMT6_16_16_16_UINT = 91,
0108     FMT6_16_16_16_SINT = 92,
0109     FMT6_16_16_16_16_UNORM = 96,
0110     FMT6_16_16_16_16_SNORM = 97,
0111     FMT6_16_16_16_16_FLOAT = 98,
0112     FMT6_16_16_16_16_UINT = 99,
0113     FMT6_16_16_16_16_SINT = 100,
0114     FMT6_32_32_UNORM = 101,
0115     FMT6_32_32_SNORM = 102,
0116     FMT6_32_32_FLOAT = 103,
0117     FMT6_32_32_UINT = 104,
0118     FMT6_32_32_SINT = 105,
0119     FMT6_32_32_FIXED = 106,
0120     FMT6_32_32_32_UNORM = 112,
0121     FMT6_32_32_32_SNORM = 113,
0122     FMT6_32_32_32_UINT = 114,
0123     FMT6_32_32_32_SINT = 115,
0124     FMT6_32_32_32_FLOAT = 116,
0125     FMT6_32_32_32_FIXED = 117,
0126     FMT6_32_32_32_32_UNORM = 128,
0127     FMT6_32_32_32_32_SNORM = 129,
0128     FMT6_32_32_32_32_FLOAT = 130,
0129     FMT6_32_32_32_32_UINT = 131,
0130     FMT6_32_32_32_32_SINT = 132,
0131     FMT6_32_32_32_32_FIXED = 133,
0132     FMT6_G8R8B8R8_422_UNORM = 140,
0133     FMT6_R8G8R8B8_422_UNORM = 141,
0134     FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
0135     FMT6_NV21 = 143,
0136     FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
0137     FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
0138     FMT6_NV12_Y = 148,
0139     FMT6_NV12_UV = 149,
0140     FMT6_NV12_VU = 150,
0141     FMT6_NV12_4R = 151,
0142     FMT6_NV12_4R_Y = 152,
0143     FMT6_NV12_4R_UV = 153,
0144     FMT6_P010 = 154,
0145     FMT6_P010_Y = 155,
0146     FMT6_P010_UV = 156,
0147     FMT6_TP10 = 157,
0148     FMT6_TP10_Y = 158,
0149     FMT6_TP10_UV = 159,
0150     FMT6_Z24_UNORM_S8_UINT = 160,
0151     FMT6_ETC2_RG11_UNORM = 171,
0152     FMT6_ETC2_RG11_SNORM = 172,
0153     FMT6_ETC2_R11_UNORM = 173,
0154     FMT6_ETC2_R11_SNORM = 174,
0155     FMT6_ETC1 = 175,
0156     FMT6_ETC2_RGB8 = 176,
0157     FMT6_ETC2_RGBA8 = 177,
0158     FMT6_ETC2_RGB8A1 = 178,
0159     FMT6_DXT1 = 179,
0160     FMT6_DXT3 = 180,
0161     FMT6_DXT5 = 181,
0162     FMT6_RGTC1_UNORM = 183,
0163     FMT6_RGTC1_SNORM = 184,
0164     FMT6_RGTC2_UNORM = 187,
0165     FMT6_RGTC2_SNORM = 188,
0166     FMT6_BPTC_UFLOAT = 190,
0167     FMT6_BPTC_FLOAT = 191,
0168     FMT6_BPTC = 192,
0169     FMT6_ASTC_4x4 = 193,
0170     FMT6_ASTC_5x4 = 194,
0171     FMT6_ASTC_5x5 = 195,
0172     FMT6_ASTC_6x5 = 196,
0173     FMT6_ASTC_6x6 = 197,
0174     FMT6_ASTC_8x5 = 198,
0175     FMT6_ASTC_8x6 = 199,
0176     FMT6_ASTC_8x8 = 200,
0177     FMT6_ASTC_10x5 = 201,
0178     FMT6_ASTC_10x6 = 202,
0179     FMT6_ASTC_10x8 = 203,
0180     FMT6_ASTC_10x10 = 204,
0181     FMT6_ASTC_12x10 = 205,
0182     FMT6_ASTC_12x12 = 206,
0183     FMT6_Z24_UINT_S8_UINT = 234,
0184     FMT6_NONE = 255,
0185 };
0186
0187 enum a6xx_polygon_mode {
0188     POLYMODE6_POINTS = 1,
0189     POLYMODE6_LINES = 2,
0190     POLYMODE6_TRIANGLES = 3,
0191 };
0192
0193 enum a6xx_depth_format {
0194     DEPTH6_NONE = 0,
0195     DEPTH6_16 = 1,
0196     DEPTH6_24_8 = 2,
0197     DEPTH6_32 = 4,
0198 };
0199
0200 enum a6xx_shader_id {
0201     A6XX_TP0_TMO_DATA = 9,
0202     A6XX_TP0_SMO_DATA = 10,
0203     A6XX_TP0_MIPMAP_BASE_DATA = 11,
0204     A6XX_TP1_TMO_DATA = 25,
0205     A6XX_TP1_SMO_DATA = 26,
0206     A6XX_TP1_MIPMAP_BASE_DATA = 27,
0207     A6XX_SP_INST_DATA = 41,
0208     A6XX_SP_LB_0_DATA = 42,
0209     A6XX_SP_LB_1_DATA = 43,
0210     A6XX_SP_LB_2_DATA = 44,
0211     A6XX_SP_LB_3_DATA = 45,
0212     A6XX_SP_LB_4_DATA = 46,
0213     A6XX_SP_LB_5_DATA = 47,
0214     A6XX_SP_CB_BINDLESS_DATA = 48,
0215     A6XX_SP_CB_LEGACY_DATA = 49,
0216     A6XX_SP_UAV_DATA = 50,
0217     A6XX_SP_INST_TAG = 51,
0218     A6XX_SP_CB_BINDLESS_TAG = 52,
0219     A6XX_SP_TMO_UMO_TAG = 53,
0220     A6XX_SP_SMO_TAG = 54,
0221     A6XX_SP_STATE_DATA = 55,
0222     A6XX_HLSQ_CHUNK_CVS_RAM = 73,
0223     A6XX_HLSQ_CHUNK_CPS_RAM = 74,
0224     A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
0225     A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
0226     A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
0227     A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
0228     A6XX_HLSQ_CVS_MISC_RAM = 80,
0229     A6XX_HLSQ_CPS_MISC_RAM = 81,
0230     A6XX_HLSQ_INST_RAM = 82,
0231     A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
0232     A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
0233     A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
0234     A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
0235     A6XX_HLSQ_INST_RAM_TAG = 87,
0236     A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
0237     A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
0238     A6XX_HLSQ_PWR_REST_RAM = 90,
0239     A6XX_HLSQ_PWR_REST_TAG = 91,
0240     A6XX_HLSQ_DATAPATH_META = 96,
0241     A6XX_HLSQ_FRONTEND_META = 97,
0242     A6XX_HLSQ_INDIRECT_META = 98,
0243     A6XX_HLSQ_BACKEND_META = 99,
0244 };
0245
0246 enum a6xx_debugbus_id {
0247     A6XX_DBGBUS_CP = 1,
0248     A6XX_DBGBUS_RBBM = 2,
0249     A6XX_DBGBUS_VBIF = 3,
0250     A6XX_DBGBUS_HLSQ = 4,
0251     A6XX_DBGBUS_UCHE = 5,
0252     A6XX_DBGBUS_DPM = 6,
0253     A6XX_DBGBUS_TESS = 7,
0254     A6XX_DBGBUS_PC = 8,
0255     A6XX_DBGBUS_VFDP = 9,
0256     A6XX_DBGBUS_VPC = 10,
0257     A6XX_DBGBUS_TSE = 11,
0258     A6XX_DBGBUS_RAS = 12,
0259     A6XX_DBGBUS_VSC = 13,
0260     A6XX_DBGBUS_COM = 14,
0261     A6XX_DBGBUS_LRZ = 16,
0262     A6XX_DBGBUS_A2D = 17,
0263     A6XX_DBGBUS_CCUFCHE = 18,
0264     A6XX_DBGBUS_GMU_CX = 19,
0265     A6XX_DBGBUS_RBP = 20,
0266     A6XX_DBGBUS_DCS = 21,
0267     A6XX_DBGBUS_DBGC = 22,
0268     A6XX_DBGBUS_CX = 23,
0269     A6XX_DBGBUS_GMU_GX = 24,
0270     A6XX_DBGBUS_TPFCHE = 25,
0271     A6XX_DBGBUS_GBIF_GX = 26,
0272     A6XX_DBGBUS_GPC = 29,
0273     A6XX_DBGBUS_LARC = 30,
0274     A6XX_DBGBUS_HLSQ_SPTP = 31,
0275     A6XX_DBGBUS_RB_0 = 32,
0276     A6XX_DBGBUS_RB_1 = 33,
0277     A6XX_DBGBUS_UCHE_WRAPPER = 36,
0278     A6XX_DBGBUS_CCU_0 = 40,
0279     A6XX_DBGBUS_CCU_1 = 41,
0280     A6XX_DBGBUS_VFD_0 = 56,
0281     A6XX_DBGBUS_VFD_1 = 57,
0282     A6XX_DBGBUS_VFD_2 = 58,
0283     A6XX_DBGBUS_VFD_3 = 59,
0284     A6XX_DBGBUS_SP_0 = 64,
0285     A6XX_DBGBUS_SP_1 = 65,
0286     A6XX_DBGBUS_TPL1_0 = 72,
0287     A6XX_DBGBUS_TPL1_1 = 73,
0288     A6XX_DBGBUS_TPL1_2 = 74,
0289     A6XX_DBGBUS_TPL1_3 = 75,
0290 };
0291
0292 enum a6xx_cp_perfcounter_select {
0293     PERF_CP_ALWAYS_COUNT = 0,
0294     PERF_CP_BUSY_GFX_CORE_IDLE = 1,
0295     PERF_CP_BUSY_CYCLES = 2,
0296     PERF_CP_NUM_PREEMPTIONS = 3,
0297     PERF_CP_PREEMPTION_REACTION_DELAY = 4,
0298     PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
0299     PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
0300     PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
0301     PERF_CP_PREDICATED_DRAWS_KILLED = 8,
0302     PERF_CP_MODE_SWITCH = 9,
0303     PERF_CP_ZPASS_DONE = 10,
0304     PERF_CP_CONTEXT_DONE = 11,
0305     PERF_CP_CACHE_FLUSH = 12,
0306     PERF_CP_LONG_PREEMPTIONS = 13,
0307     PERF_CP_SQE_I_CACHE_STARVE = 14,
0308     PERF_CP_SQE_IDLE = 15,
0309     PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
0310     PERF_CP_SQE_PM4_STARVE_SDS = 17,
0311     PERF_CP_SQE_MRB_STARVE = 18,
0312     PERF_CP_SQE_RRB_STARVE = 19,
0313     PERF_CP_SQE_VSD_STARVE = 20,
0314     PERF_CP_VSD_DECODE_STARVE = 21,
0315     PERF_CP_SQE_PIPE_OUT_STALL = 22,
0316     PERF_CP_SQE_SYNC_STALL = 23,
0317     PERF_CP_SQE_PM4_WFI_STALL = 24,
0318     PERF_CP_SQE_SYS_WFI_STALL = 25,
0319     PERF_CP_SQE_T4_EXEC = 26,
0320     PERF_CP_SQE_LOAD_STATE_EXEC = 27,
0321     PERF_CP_SQE_SAVE_SDS_STATE = 28,
0322     PERF_CP_SQE_DRAW_EXEC = 29,
0323     PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
0324     PERF_CP_SQE_EXEC_PROFILED = 31,
0325     PERF_CP_MEMORY_POOL_EMPTY = 32,
0326     PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
0327     PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
0328     PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
0329     PERF_CP_AHB_STALL_SQE_GMU = 36,
0330     PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
0331     PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
0332     PERF_CP_CLUSTER0_EMPTY = 39,
0333     PERF_CP_CLUSTER1_EMPTY = 40,
0334     PERF_CP_CLUSTER2_EMPTY = 41,
0335     PERF_CP_CLUSTER3_EMPTY = 42,
0336     PERF_CP_CLUSTER4_EMPTY = 43,
0337     PERF_CP_CLUSTER5_EMPTY = 44,
0338     PERF_CP_PM4_DATA = 45,
0339     PERF_CP_PM4_HEADERS = 46,
0340     PERF_CP_VBIF_READ_BEATS = 47,
0341     PERF_CP_VBIF_WRITE_BEATS = 48,
0342     PERF_CP_SQE_INSTR_COUNTER = 49,
0343 };
0344
0345 enum a6xx_rbbm_perfcounter_select {
0346     PERF_RBBM_ALWAYS_COUNT = 0,
0347     PERF_RBBM_ALWAYS_ON = 1,
0348     PERF_RBBM_TSE_BUSY = 2,
0349     PERF_RBBM_RAS_BUSY = 3,
0350     PERF_RBBM_PC_DCALL_BUSY = 4,
0351     PERF_RBBM_PC_VSD_BUSY = 5,
0352     PERF_RBBM_STATUS_MASKED = 6,
0353     PERF_RBBM_COM_BUSY = 7,
0354     PERF_RBBM_DCOM_BUSY = 8,
0355     PERF_RBBM_VBIF_BUSY = 9,
0356     PERF_RBBM_VSC_BUSY = 10,
0357     PERF_RBBM_TESS_BUSY = 11,
0358     PERF_RBBM_UCHE_BUSY = 12,
0359     PERF_RBBM_HLSQ_BUSY = 13,
0360 };
0361
0362 enum a6xx_pc_perfcounter_select {
0363     PERF_PC_BUSY_CYCLES = 0,
0364     PERF_PC_WORKING_CYCLES = 1,
0365     PERF_PC_STALL_CYCLES_VFD = 2,
0366     PERF_PC_STALL_CYCLES_TSE = 3,
0367     PERF_PC_STALL_CYCLES_VPC = 4,
0368     PERF_PC_STALL_CYCLES_UCHE = 5,
0369     PERF_PC_STALL_CYCLES_TESS = 6,
0370     PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
0371     PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
0372     PERF_PC_PASS1_TF_STALL_CYCLES = 9,
0373     PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
0374     PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
0375     PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
0376     PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
0377     PERF_PC_STARVE_CYCLES_DI = 14,
0378     PERF_PC_VIS_STREAMS_LOADED = 15,
0379     PERF_PC_INSTANCES = 16,
0380     PERF_PC_VPC_PRIMITIVES = 17,
0381     PERF_PC_DEAD_PRIM = 18,
0382     PERF_PC_LIVE_PRIM = 19,
0383     PERF_PC_VERTEX_HITS = 20,
0384     PERF_PC_IA_VERTICES = 21,
0385     PERF_PC_IA_PRIMITIVES = 22,
0386     PERF_PC_GS_PRIMITIVES = 23,
0387     PERF_PC_HS_INVOCATIONS = 24,
0388     PERF_PC_DS_INVOCATIONS = 25,
0389     PERF_PC_VS_INVOCATIONS = 26,
0390     PERF_PC_GS_INVOCATIONS = 27,
0391     PERF_PC_DS_PRIMITIVES = 28,
0392     PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
0393     PERF_PC_3D_DRAWCALLS = 30,
0394     PERF_PC_2D_DRAWCALLS = 31,
0395     PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
0396     PERF_TESS_BUSY_CYCLES = 33,
0397     PERF_TESS_WORKING_CYCLES = 34,
0398     PERF_TESS_STALL_CYCLES_PC = 35,
0399     PERF_TESS_STARVE_CYCLES_PC = 36,
0400     PERF_PC_TSE_TRANSACTION = 37,
0401     PERF_PC_TSE_VERTEX = 38,
0402     PERF_PC_TESS_PC_UV_TRANS = 39,
0403     PERF_PC_TESS_PC_UV_PATCHES = 40,
0404     PERF_PC_TESS_FACTOR_TRANS = 41,
0405 };
0406
0407 enum a6xx_vfd_perfcounter_select {
0408     PERF_VFD_BUSY_CYCLES = 0,
0409     PERF_VFD_STALL_CYCLES_UCHE = 1,
0410     PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
0411     PERF_VFD_STALL_CYCLES_SP_INFO = 3,
0412     PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
0413     PERF_VFD_STARVE_CYCLES_UCHE = 5,
0414     PERF_VFD_RBUFFER_FULL = 6,
0415     PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
0416     PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
0417     PERF_VFD_NUM_ATTRIBUTES = 9,
0418     PERF_VFD_UPPER_SHADER_FIBERS = 10,
0419     PERF_VFD_LOWER_SHADER_FIBERS = 11,
0420     PERF_VFD_MODE_0_FIBERS = 12,
0421     PERF_VFD_MODE_1_FIBERS = 13,
0422     PERF_VFD_MODE_2_FIBERS = 14,
0423     PERF_VFD_MODE_3_FIBERS = 15,
0424     PERF_VFD_MODE_4_FIBERS = 16,
0425     PERF_VFD_TOTAL_VERTICES = 17,
0426     PERF_VFDP_STALL_CYCLES_VFD = 18,
0427     PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
0428     PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
0429     PERF_VFDP_STARVE_CYCLES_PC = 21,
0430     PERF_VFDP_VS_STAGE_WAVES = 22,
0431 };
0432
0433 enum a6xx_hlsq_perfcounter_select {
0434     PERF_HLSQ_BUSY_CYCLES = 0,
0435     PERF_HLSQ_STALL_CYCLES_UCHE = 1,
0436     PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
0437     PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
0438     PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
0439     PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
0440     PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
0441     PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
0442     PERF_HLSQ_QUADS = 8,
0443     PERF_HLSQ_CS_INVOCATIONS = 9,
0444     PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
0445     PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
0446     PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
0447     PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
0448     PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
0449     PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
0450     PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
0451     PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
0452     PERF_HLSQ_STALL_CYCLES_VPC = 18,
0453     PERF_HLSQ_PIXELS = 19,
0454     PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
0455 };
0456
0457 enum a6xx_vpc_perfcounter_select {
0458     PERF_VPC_BUSY_CYCLES = 0,
0459     PERF_VPC_WORKING_CYCLES = 1,
0460     PERF_VPC_STALL_CYCLES_UCHE = 2,
0461     PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
0462     PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
0463     PERF_VPC_STALL_CYCLES_PC = 5,
0464     PERF_VPC_STALL_CYCLES_SP_LM = 6,
0465     PERF_VPC_STARVE_CYCLES_SP = 7,
0466     PERF_VPC_STARVE_CYCLES_LRZ = 8,
0467     PERF_VPC_PC_PRIMITIVES = 9,
0468     PERF_VPC_SP_COMPONENTS = 10,
0469     PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
0470     PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
0471     PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
0472     PERF_VPC_LM_TRANSACTION = 14,
0473     PERF_VPC_STREAMOUT_TRANSACTION = 15,
0474     PERF_VPC_VS_BUSY_CYCLES = 16,
0475     PERF_VPC_PS_BUSY_CYCLES = 17,
0476     PERF_VPC_VS_WORKING_CYCLES = 18,
0477     PERF_VPC_PS_WORKING_CYCLES = 19,
0478     PERF_VPC_STARVE_CYCLES_RB = 20,
0479     PERF_VPC_NUM_VPCRAM_READ_POS = 21,
0480     PERF_VPC_WIT_FULL_CYCLES = 22,
0481     PERF_VPC_VPCRAM_FULL_CYCLES = 23,
0482     PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
0483     PERF_VPC_NUM_VPCRAM_WRITE = 25,
0484     PERF_VPC_NUM_VPCRAM_READ_SO = 26,
0485     PERF_VPC_NUM_ATTR_REQ_LM = 27,
0486 };
0487
0488 enum a6xx_tse_perfcounter_select {
0489     PERF_TSE_BUSY_CYCLES = 0,
0490     PERF_TSE_CLIPPING_CYCLES = 1,
0491     PERF_TSE_STALL_CYCLES_RAS = 2,
0492     PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
0493     PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
0494     PERF_TSE_STARVE_CYCLES_PC = 5,
0495     PERF_TSE_INPUT_PRIM = 6,
0496     PERF_TSE_INPUT_NULL_PRIM = 7,
0497     PERF_TSE_TRIVAL_REJ_PRIM = 8,
0498     PERF_TSE_CLIPPED_PRIM = 9,
0499     PERF_TSE_ZERO_AREA_PRIM = 10,
0500     PERF_TSE_FACENESS_CULLED_PRIM = 11,
0501     PERF_TSE_ZERO_PIXEL_PRIM = 12,
0502     PERF_TSE_OUTPUT_NULL_PRIM = 13,
0503     PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
0504     PERF_TSE_CINVOCATION = 15,
0505     PERF_TSE_CPRIMITIVES = 16,
0506     PERF_TSE_2D_INPUT_PRIM = 17,
0507     PERF_TSE_2D_ALIVE_CYCLES = 18,
0508     PERF_TSE_CLIP_PLANES = 19,
0509 };
0510
0511 enum a6xx_ras_perfcounter_select {
0512     PERF_RAS_BUSY_CYCLES = 0,
0513     PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
0514     PERF_RAS_STALL_CYCLES_LRZ = 2,
0515     PERF_RAS_STARVE_CYCLES_TSE = 3,
0516     PERF_RAS_SUPER_TILES = 4,
0517     PERF_RAS_8X4_TILES = 5,
0518     PERF_RAS_MASKGEN_ACTIVE = 6,
0519     PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
0520     PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
0521     PERF_RAS_PRIM_KILLED_INVISILBE = 9,
0522     PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
0523     PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
0524     PERF_RAS_BLOCKS = 12,
0525 };
0526
0527 enum a6xx_uche_perfcounter_select {
0528     PERF_UCHE_BUSY_CYCLES = 0,
0529     PERF_UCHE_STALL_CYCLES_ARBITER = 1,
0530     PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
0531     PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
0532     PERF_UCHE_VBIF_READ_BEATS_TP = 4,
0533     PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
0534     PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
0535     PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
0536     PERF_UCHE_VBIF_READ_BEATS_SP = 8,
0537     PERF_UCHE_READ_REQUESTS_TP = 9,
0538     PERF_UCHE_READ_REQUESTS_VFD = 10,
0539     PERF_UCHE_READ_REQUESTS_HLSQ = 11,
0540     PERF_UCHE_READ_REQUESTS_LRZ = 12,
0541     PERF_UCHE_READ_REQUESTS_SP = 13,
0542     PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
0543     PERF_UCHE_WRITE_REQUESTS_SP = 15,
0544     PERF_UCHE_WRITE_REQUESTS_VPC = 16,
0545     PERF_UCHE_WRITE_REQUESTS_VSC = 17,
0546     PERF_UCHE_EVICTS = 18,
0547     PERF_UCHE_BANK_REQ0 = 19,
0548     PERF_UCHE_BANK_REQ1 = 20,
0549     PERF_UCHE_BANK_REQ2 = 21,
0550     PERF_UCHE_BANK_REQ3 = 22,
0551     PERF_UCHE_BANK_REQ4 = 23,
0552     PERF_UCHE_BANK_REQ5 = 24,
0553     PERF_UCHE_BANK_REQ6 = 25,
0554     PERF_UCHE_BANK_REQ7 = 26,
0555     PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
0556     PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
0557     PERF_UCHE_GMEM_READ_BEATS = 29,
0558     PERF_UCHE_TPH_REF_FULL = 30,
0559     PERF_UCHE_TPH_VICTIM_FULL = 31,
0560     PERF_UCHE_TPH_EXT_FULL = 32,
0561     PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
0562     PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
0563     PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
0564     PERF_UCHE_VBIF_READ_BEATS_PC = 36,
0565     PERF_UCHE_READ_REQUESTS_PC = 37,
0566     PERF_UCHE_RAM_READ_REQ = 38,
0567     PERF_UCHE_RAM_WRITE_REQ = 39,
0568 };
0569
0570 enum a6xx_tp_perfcounter_select {
0571     PERF_TP_BUSY_CYCLES = 0,
0572     PERF_TP_STALL_CYCLES_UCHE = 1,
0573     PERF_TP_LATENCY_CYCLES = 2,
0574     PERF_TP_LATENCY_TRANS = 3,
0575     PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
0576     PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
0577     PERF_TP_L1_CACHELINE_REQUESTS = 6,
0578     PERF_TP_L1_CACHELINE_MISSES = 7,
0579     PERF_TP_SP_TP_TRANS = 8,
0580     PERF_TP_TP_SP_TRANS = 9,
0581     PERF_TP_OUTPUT_PIXELS = 10,
0582     PERF_TP_FILTER_WORKLOAD_16BIT = 11,
0583     PERF_TP_FILTER_WORKLOAD_32BIT = 12,
0584     PERF_TP_QUADS_RECEIVED = 13,
0585     PERF_TP_QUADS_OFFSET = 14,
0586     PERF_TP_QUADS_SHADOW = 15,
0587     PERF_TP_QUADS_ARRAY = 16,
0588     PERF_TP_QUADS_GRADIENT = 17,
0589     PERF_TP_QUADS_1D = 18,
0590     PERF_TP_QUADS_2D = 19,
0591     PERF_TP_QUADS_BUFFER = 20,
0592     PERF_TP_QUADS_3D = 21,
0593     PERF_TP_QUADS_CUBE = 22,
0594     PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
0595     PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
0596     PERF_TP_OUTPUT_PIXELS_POINT = 25,
0597     PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
0598     PERF_TP_OUTPUT_PIXELS_MIP = 27,
0599     PERF_TP_OUTPUT_PIXELS_ANISO = 28,
0600     PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
0601     PERF_TP_FLAG_CACHE_REQUESTS = 30,
0602     PERF_TP_FLAG_CACHE_MISSES = 31,
0603     PERF_TP_L1_5_L2_REQUESTS = 32,
0604     PERF_TP_2D_OUTPUT_PIXELS = 33,
0605     PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
0606     PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
0607     PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
0608     PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
0609     PERF_TP_TPA2TPC_TRANS = 38,
0610     PERF_TP_L1_MISSES_ASTC_1TILE = 39,
0611     PERF_TP_L1_MISSES_ASTC_2TILE = 40,
0612     PERF_TP_L1_MISSES_ASTC_4TILE = 41,
0613     PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
0614     PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
0615     PERF_TP_L1_BANK_CONFLICT = 44,
0616     PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
0617     PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
0618     PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
0619     PERF_TP_FRONTEND_WORKING_CYCLES = 48,
0620     PERF_TP_L1_TAG_WORKING_CYCLES = 49,
0621     PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
0622     PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
0623     PERF_TP_BACKEND_WORKING_CYCLES = 52,
0624     PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
0625     PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
0626     PERF_TP_STARVE_CYCLES_SP = 55,
0627     PERF_TP_STARVE_CYCLES_UCHE = 56,
0628 };
0629
0630 enum a6xx_sp_perfcounter_select {
0631     PERF_SP_BUSY_CYCLES = 0,
0632     PERF_SP_ALU_WORKING_CYCLES = 1,
0633     PERF_SP_EFU_WORKING_CYCLES = 2,
0634     PERF_SP_STALL_CYCLES_VPC = 3,
0635     PERF_SP_STALL_CYCLES_TP = 4,
0636     PERF_SP_STALL_CYCLES_UCHE = 5,
0637     PERF_SP_STALL_CYCLES_RB = 6,
0638     PERF_SP_NON_EXECUTION_CYCLES = 7,
0639     PERF_SP_WAVE_CONTEXTS = 8,
0640     PERF_SP_WAVE_CONTEXT_CYCLES = 9,
0641     PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
0642     PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
0643     PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
0644     PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
0645     PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
0646     PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
0647     PERF_SP_WAVE_CTRL_CYCLES = 16,
0648     PERF_SP_WAVE_LOAD_CYCLES = 17,
0649     PERF_SP_WAVE_EMIT_CYCLES = 18,
0650     PERF_SP_WAVE_NOP_CYCLES = 19,
0651     PERF_SP_WAVE_WAIT_CYCLES = 20,
0652     PERF_SP_WAVE_FETCH_CYCLES = 21,
0653     PERF_SP_WAVE_IDLE_CYCLES = 22,
0654     PERF_SP_WAVE_END_CYCLES = 23,
0655     PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
0656     PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
0657     PERF_SP_WAVE_JOIN_CYCLES = 26,
0658     PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
0659     PERF_SP_LM_STORE_INSTRUCTIONS = 28,
0660     PERF_SP_LM_ATOMICS = 29,
0661     PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
0662     PERF_SP_GM_STORE_INSTRUCTIONS = 31,
0663     PERF_SP_GM_ATOMICS = 32,
0664     PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
0665     PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
0666     PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
0667     PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
0668     PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
0669     PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
0670     PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
0671     PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
0672     PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
0673     PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
0674     PERF_SP_VS_INSTRUCTIONS = 43,
0675     PERF_SP_FS_INSTRUCTIONS = 44,
0676     PERF_SP_ADDR_LOCK_COUNT = 45,
0677     PERF_SP_UCHE_READ_TRANS = 46,
0678     PERF_SP_UCHE_WRITE_TRANS = 47,
0679     PERF_SP_EXPORT_VPC_TRANS = 48,
0680     PERF_SP_EXPORT_RB_TRANS = 49,
0681     PERF_SP_PIXELS_KILLED = 50,
0682     PERF_SP_ICL1_REQUESTS = 51,
0683     PERF_SP_ICL1_MISSES = 52,
0684     PERF_SP_HS_INSTRUCTIONS = 53,
0685     PERF_SP_DS_INSTRUCTIONS = 54,
0686     PERF_SP_GS_INSTRUCTIONS = 55,
0687     PERF_SP_CS_INSTRUCTIONS = 56,
0688     PERF_SP_GPR_READ = 57,
0689     PERF_SP_GPR_WRITE = 58,
0690     PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
0691     PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
0692     PERF_SP_LM_BANK_CONFLICTS = 61,
0693     PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
0694     PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
0695     PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
0696     PERF_SP_LM_WORKING_CYCLES = 65,
0697     PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
0698     PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
0699     PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
0700     PERF_SP_STARVE_CYCLES_HLSQ = 69,
0701     PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
0702     PERF_SP_WORKING_EU = 71,
0703     PERF_SP_ANY_EU_WORKING = 72,
0704     PERF_SP_WORKING_EU_FS_STAGE = 73,
0705     PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
0706     PERF_SP_WORKING_EU_VS_STAGE = 75,
0707     PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
0708     PERF_SP_WORKING_EU_CS_STAGE = 77,
0709     PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
0710     PERF_SP_GPR_READ_PREFETCH = 79,
0711     PERF_SP_GPR_READ_CONFLICT = 80,
0712     PERF_SP_GPR_WRITE_CONFLICT = 81,
0713     PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
0714     PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
0715     PERF_SP_EXECUTABLE_WAVES = 84,
0716 };
0717
0718 enum a6xx_rb_perfcounter_select {
0719     PERF_RB_BUSY_CYCLES = 0,
0720     PERF_RB_STALL_CYCLES_HLSQ = 1,
0721     PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
0722     PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
0723     PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
0724     PERF_RB_STARVE_CYCLES_SP = 5,
0725     PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
0726     PERF_RB_STARVE_CYCLES_CCU = 7,
0727     PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
0728     PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
0729     PERF_RB_Z_WORKLOAD = 10,
0730     PERF_RB_HLSQ_ACTIVE = 11,
0731     PERF_RB_Z_READ = 12,
0732     PERF_RB_Z_WRITE = 13,
0733     PERF_RB_C_READ = 14,
0734     PERF_RB_C_WRITE = 15,
0735     PERF_RB_TOTAL_PASS = 16,
0736     PERF_RB_Z_PASS = 17,
0737     PERF_RB_Z_FAIL = 18,
0738     PERF_RB_S_FAIL = 19,
0739     PERF_RB_BLENDED_FXP_COMPONENTS = 20,
0740     PERF_RB_BLENDED_FP16_COMPONENTS = 21,
0741     PERF_RB_PS_INVOCATIONS = 22,
0742     PERF_RB_2D_ALIVE_CYCLES = 23,
0743     PERF_RB_2D_STALL_CYCLES_A2D = 24,
0744     PERF_RB_2D_STARVE_CYCLES_SRC = 25,
0745     PERF_RB_2D_STARVE_CYCLES_SP = 26,
0746     PERF_RB_2D_STARVE_CYCLES_DST = 27,
0747     PERF_RB_2D_VALID_PIXELS = 28,
0748     PERF_RB_3D_PIXELS = 29,
0749     PERF_RB_BLENDER_WORKING_CYCLES = 30,
0750     PERF_RB_ZPROC_WORKING_CYCLES = 31,
0751     PERF_RB_CPROC_WORKING_CYCLES = 32,
0752     PERF_RB_SAMPLER_WORKING_CYCLES = 33,
0753     PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
0754     PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
0755     PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
0756     PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
0757     PERF_RB_STALL_CYCLES_VPC = 38,
0758     PERF_RB_2D_INPUT_TRANS = 39,
0759     PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
0760     PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
0761     PERF_RB_BLENDED_FP32_COMPONENTS = 42,
0762     PERF_RB_COLOR_PIX_TILES = 43,
0763     PERF_RB_STALL_CYCLES_CCU = 44,
0764     PERF_RB_EARLY_Z_ARB3_GRANT = 45,
0765     PERF_RB_LATE_Z_ARB3_GRANT = 46,
0766     PERF_RB_EARLY_Z_SKIP_GRANT = 47,
0767 };
0768
0769 enum a6xx_vsc_perfcounter_select {
0770     PERF_VSC_BUSY_CYCLES = 0,
0771     PERF_VSC_WORKING_CYCLES = 1,
0772     PERF_VSC_STALL_CYCLES_UCHE = 2,
0773     PERF_VSC_EOT_NUM = 3,
0774     PERF_VSC_INPUT_TILES = 4,
0775 };
0776
0777 enum a6xx_ccu_perfcounter_select {
0778     PERF_CCU_BUSY_CYCLES = 0,
0779     PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
0780     PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
0781     PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
0782     PERF_CCU_DEPTH_BLOCKS = 4,
0783     PERF_CCU_COLOR_BLOCKS = 5,
0784     PERF_CCU_DEPTH_BLOCK_HIT = 6,
0785     PERF_CCU_COLOR_BLOCK_HIT = 7,
0786     PERF_CCU_PARTIAL_BLOCK_READ = 8,
0787     PERF_CCU_GMEM_READ = 9,
0788     PERF_CCU_GMEM_WRITE = 10,
0789     PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
0790     PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
0791     PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
0792     PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
0793     PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
0794     PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
0795     PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
0796     PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
0797     PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
0798     PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
0799     PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
0800     PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
0801     PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
0802     PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
0803     PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
0804     PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
0805     PERF_CCU_2D_RD_REQ = 27,
0806     PERF_CCU_2D_WR_REQ = 28,
0807 };
0808
0809 enum a6xx_lrz_perfcounter_select {
0810     PERF_LRZ_BUSY_CYCLES = 0,
0811     PERF_LRZ_STARVE_CYCLES_RAS = 1,
0812     PERF_LRZ_STALL_CYCLES_RB = 2,
0813     PERF_LRZ_STALL_CYCLES_VSC = 3,
0814     PERF_LRZ_STALL_CYCLES_VPC = 4,
0815     PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
0816     PERF_LRZ_STALL_CYCLES_UCHE = 6,
0817     PERF_LRZ_LRZ_READ = 7,
0818     PERF_LRZ_LRZ_WRITE = 8,
0819     PERF_LRZ_READ_LATENCY = 9,
0820     PERF_LRZ_MERGE_CACHE_UPDATING = 10,
0821     PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
0822     PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
0823     PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
0824     PERF_LRZ_FULL_8X8_TILES = 14,
0825     PERF_LRZ_PARTIAL_8X8_TILES = 15,
0826     PERF_LRZ_TILE_KILLED = 16,
0827     PERF_LRZ_TOTAL_PIXEL = 17,
0828     PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
0829     PERF_LRZ_FULLY_COVERED_TILES = 19,
0830     PERF_LRZ_PARTIAL_COVERED_TILES = 20,
0831     PERF_LRZ_FEEDBACK_ACCEPT = 21,
0832     PERF_LRZ_FEEDBACK_DISCARD = 22,
0833     PERF_LRZ_FEEDBACK_STALL = 23,
0834     PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
0835     PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
0836     PERF_LRZ_STALL_CYCLES_VC = 26,
0837     PERF_LRZ_RAS_MASK_TRANS = 27,
0838 };
0839
0840 enum a6xx_cmp_perfcounter_select {
0841     PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
0842     PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
0843     PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
0844     PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
0845     PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
0846     PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
0847     PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
0848     PERF_CMPDECMP_VBIF_READ_DATA = 7,
0849     PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
0850     PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
0851     PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
0852     PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
0853     PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
0854     PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
0855     PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
0856     PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
0857     PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
0858     PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
0859     PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
0860     PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
0861     PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
0862     PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
0863     PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
0864     PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
0865     PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
0866     PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
0867     PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
0868     PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
0869     PERF_CMPDECMP_2D_RD_DATA = 28,
0870     PERF_CMPDECMP_2D_WR_DATA = 29,
0871     PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
0872     PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
0873     PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
0874     PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
0875     PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
0876     PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
0877     PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
0878     PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
0879     PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
0880     PERF_CMPDECMP_2D_PIXELS = 39,
0881 };
0882
0883 enum a6xx_2d_ifmt {
0884     R2D_UNORM8 = 16,
0885     R2D_INT32 = 7,
0886     R2D_INT16 = 6,
0887     R2D_INT8 = 5,
0888     R2D_FLOAT32 = 4,
0889     R2D_FLOAT16 = 3,
0890     R2D_UNORM8_SRGB = 1,
0891     R2D_RAW = 0,
0892 };
0893
0894 enum a6xx_ztest_mode {
0895     A6XX_EARLY_Z = 0,
0896     A6XX_LATE_Z = 1,
0897     A6XX_EARLY_LRZ_LATE_Z = 2,
0898 };
0899
0900 enum a6xx_sequenced_thread_dist {
0901     DIST_SCREEN_COORD = 0,
0902     DIST_ALL_TO_RB0 = 1,
0903 };
0904
0905 enum a6xx_single_prim_mode {
0906     NO_FLUSH = 0,
0907     FLUSH_PER_OVERLAP_AND_OVERWRITE = 1,
0908     FLUSH_PER_OVERLAP = 3,
0909 };
0910
0911 enum a6xx_raster_mode {
0912     TYPE_TILED = 0,
0913     TYPE_WRITER = 1,
0914 };
0915
0916 enum a6xx_raster_direction {
0917     LR_TB = 0,
0918     RL_TB = 1,
0919     LR_BT = 2,
0920     RB_BT = 3,
0921 };
0922
0923 enum a6xx_render_mode {
0924     RENDERING_PASS = 0,
0925     BINNING_PASS = 1,
0926 };
0927
0928 enum a6xx_buffers_location {
0929     BUFFERS_IN_GMEM = 0,
0930     BUFFERS_IN_SYSMEM = 3,
0931 };
0932
0933 enum a6xx_fragcoord_sample_mode {
0934     FRAGCOORD_CENTER = 0,
0935     FRAGCOORD_SAMPLE = 3,
0936 };
0937
0938 enum a6xx_rotation {
0939     ROTATE_0 = 0,
0940     ROTATE_90 = 1,
0941     ROTATE_180 = 2,
0942     ROTATE_270 = 3,
0943     ROTATE_HFLIP = 4,
0944     ROTATE_VFLIP = 5,
0945 };
0946
0947 enum a6xx_tess_spacing {
0948     TESS_EQUAL = 0,
0949     TESS_FRACTIONAL_ODD = 2,
0950     TESS_FRACTIONAL_EVEN = 3,
0951 };
0952
0953 enum a6xx_tess_output {
0954     TESS_POINTS = 0,
0955     TESS_LINES = 1,
0956     TESS_CW_TRIS = 2,
0957     TESS_CCW_TRIS = 3,
0958 };
0959
0960 enum a6xx_threadsize {
0961     THREAD64 = 0,
0962     THREAD128 = 1,
0963 };
0964
0965 enum a6xx_isam_mode {
0966     ISAMMODE_GL = 2,
0967 };
0968
0969 enum a6xx_tex_filter {
0970     A6XX_TEX_NEAREST = 0,
0971     A6XX_TEX_LINEAR = 1,
0972     A6XX_TEX_ANISO = 2,
0973     A6XX_TEX_CUBIC = 3,
0974 };
0975
0976 enum a6xx_tex_clamp {
0977     A6XX_TEX_REPEAT = 0,
0978     A6XX_TEX_CLAMP_TO_EDGE = 1,
0979     A6XX_TEX_MIRROR_REPEAT = 2,
0980     A6XX_TEX_CLAMP_TO_BORDER = 3,
0981     A6XX_TEX_MIRROR_CLAMP = 4,
0982 };
0983
0984 enum a6xx_tex_aniso {
0985     A6XX_TEX_ANISO_1 = 0,
0986     A6XX_TEX_ANISO_2 = 1,
0987     A6XX_TEX_ANISO_4 = 2,
0988     A6XX_TEX_ANISO_8 = 3,
0989     A6XX_TEX_ANISO_16 = 4,
0990 };
0991
0992 enum a6xx_reduction_mode {
0993     A6XX_REDUCTION_MODE_AVERAGE = 0,
0994     A6XX_REDUCTION_MODE_MIN = 1,
0995     A6XX_REDUCTION_MODE_MAX = 2,
0996 };
0997
0998 enum a6xx_tex_swiz {
0999     A6XX_TEX_X = 0,
1000     A6XX_TEX_Y = 1,
1001     A6XX_TEX_Z = 2,
1002     A6XX_TEX_W = 3,
1003     A6XX_TEX_ZERO = 4,
1004     A6XX_TEX_ONE = 5,
1005 };
1006
1007 enum a6xx_tex_type {
1008     A6XX_TEX_1D = 0,
1009     A6XX_TEX_2D = 1,
1010     A6XX_TEX_CUBE = 2,
1011     A6XX_TEX_3D = 3,
1012     A6XX_TEX_BUFFER = 4,
1013 };
1014
1015 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE          0x00000001
1016 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR           0x00000002
1017 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW    0x00000040
1018 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR         0x00000080
1019 #define A6XX_RBBM_INT_0_MASK_CP_SW              0x00000100
1020 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR            0x00000200
1021 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS      0x00000400
1022 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS      0x00000800
1023 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS          0x00001000
1024 #define A6XX_RBBM_INT_0_MASK_CP_IB2             0x00002000
1025 #define A6XX_RBBM_INT_0_MASK_CP_IB1             0x00004000
1026 #define A6XX_RBBM_INT_0_MASK_CP_RB              0x00008000
1027 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS          0x00020000
1028 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS          0x00040000
1029 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS          0x00100000
1030 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW      0x00400000
1031 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT           0x00800000
1032 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS            0x01000000
1033 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR         0x02000000
1034 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0          0x04000000
1035 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1          0x08000000
1036 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ           0x40000000
1037 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG           0x80000000
1038 #define A6XX_CP_INT_CP_OPCODE_ERROR             0x00000001
1039 #define A6XX_CP_INT_CP_UCODE_ERROR              0x00000002
1040 #define A6XX_CP_INT_CP_HW_FAULT_ERROR               0x00000004
1041 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR        0x00000010
1042 #define A6XX_CP_INT_CP_AHB_ERROR                0x00000020
1043 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR             0x00000040
1044 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR          0x00000080
1045 #define REG_A6XX_CP_RB_BASE                 0x00000800
1046
1047 #define REG_A6XX_CP_RB_BASE_HI                  0x00000801
1048
1049 #define REG_A6XX_CP_RB_CNTL                 0x00000802
1050
1051 #define REG_A6XX_CP_RB_RPTR_ADDR_LO             0x00000804
1052
1053 #define REG_A6XX_CP_RB_RPTR_ADDR_HI             0x00000805
1054
1055 #define REG_A6XX_CP_RB_RPTR                 0x00000806
1056
1057 #define REG_A6XX_CP_RB_WPTR                 0x00000807
1058
1059 #define REG_A6XX_CP_SQE_CNTL                    0x00000808
1060
1061 #define REG_A6XX_CP_CP2GMU_STATUS               0x00000812
1062 #define A6XX_CP_CP2GMU_STATUS_IFPC              0x00000001
1063
1064 #define REG_A6XX_CP_HW_FAULT                    0x00000821
1065
1066 #define REG_A6XX_CP_INTERRUPT_STATUS                0x00000823
1067
1068 #define REG_A6XX_CP_PROTECT_STATUS              0x00000824
1069
1070 #define REG_A6XX_CP_SQE_INSTR_BASE              0x00000830
1071
1072 #define REG_A6XX_CP_MISC_CNTL                   0x00000840
1073
1074 #define REG_A6XX_CP_APRIV_CNTL                  0x00000844
1075
1076 #define REG_A6XX_CP_ROQ_THRESHOLDS_1                0x000008c1
1077 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK            0x000000ff
1078 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT           0
1079 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)
1080 {
1081     return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK;
1082 }
1083 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK            0x0000ff00
1084 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT           8
1085 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)
1086 {
1087     return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK;
1088 }
1089 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK        0x00ff0000
1090 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT       16
1091 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
1092 {
1093     return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
1094 }
1095 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK        0xff000000
1096 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT       24
1097 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
1098 {
1099     return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
1100 }
1101
1102 #define REG_A6XX_CP_ROQ_THRESHOLDS_2                0x000008c2
1103 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK        0x000001ff
1104 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT       0
1105 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
1106 {
1107     return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
1108 }
1109 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK         0xffff0000
1110 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT        16
1111 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
1112 {
1113     return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
1114 }
1115
1116 #define REG_A6XX_CP_MEM_POOL_SIZE               0x000008c3
1117
1118 #define REG_A6XX_CP_CHICKEN_DBG                 0x00000841
1119
1120 #define REG_A6XX_CP_ADDR_MODE_CNTL              0x00000842
1121
1122 #define REG_A6XX_CP_DBG_ECO_CNTL                0x00000843
1123
1124 #define REG_A6XX_CP_PROTECT_CNTL                0x0000084f
1125
1126 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1127
1128 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1129
1130 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1131
1132 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1133 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK         0x0003ffff
1134 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT            0
1135 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1136 {
1137     return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1138 }
1139 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK          0x7ffc0000
1140 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT         18
1141 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1142 {
1143     return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
1144 }
1145 #define A6XX_CP_PROTECT_REG_READ                0x80000000
1146
1147 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL             0x000008a0
1148
1149 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO         0x000008a1
1150
1151 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI         0x000008a2
1152
1153 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO  0x000008a3
1154
1155 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI  0x000008a4
1156
1157 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO  0x000008a5
1158
1159 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI  0x000008a6
1160
1161 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
1162
1163 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1164
1165 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
1166
1167 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO            0x00000900
1168
1169 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI            0x00000901
1170
1171 #define REG_A6XX_CP_CRASH_DUMP_CNTL             0x00000902
1172
1173 #define REG_A6XX_CP_CRASH_DUMP_STATUS               0x00000903
1174
1175 #define REG_A6XX_CP_SQE_STAT_ADDR               0x00000908
1176
1177 #define REG_A6XX_CP_SQE_STAT_DATA               0x00000909
1178
1179 #define REG_A6XX_CP_DRAW_STATE_ADDR             0x0000090a
1180
1181 #define REG_A6XX_CP_DRAW_STATE_DATA             0x0000090b
1182
1183 #define REG_A6XX_CP_ROQ_DBG_ADDR                0x0000090c
1184
1185 #define REG_A6XX_CP_ROQ_DBG_DATA                0x0000090d
1186
1187 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR               0x0000090e
1188
1189 #define REG_A6XX_CP_MEM_POOL_DBG_DATA               0x0000090f
1190
1191 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR              0x00000910
1192
1193 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA              0x00000911
1194
1195 #define REG_A6XX_CP_IB1_BASE                    0x00000928
1196
1197 #define REG_A6XX_CP_IB1_BASE_HI                 0x00000929
1198
1199 #define REG_A6XX_CP_IB1_REM_SIZE                0x0000092a
1200
1201 #define REG_A6XX_CP_IB2_BASE                    0x0000092b
1202
1203 #define REG_A6XX_CP_IB2_BASE_HI                 0x0000092c
1204
1205 #define REG_A6XX_CP_IB2_REM_SIZE                0x0000092d
1206
1207 #define REG_A6XX_CP_SDS_BASE                    0x0000092e
1208
1209 #define REG_A6XX_CP_SDS_BASE_HI                 0x0000092f
1210
1211 #define REG_A6XX_CP_SDS_REM_SIZE                0x00000930
1212
1213 #define REG_A6XX_CP_MRB_BASE                    0x00000931
1214
1215 #define REG_A6XX_CP_MRB_BASE_HI                 0x00000932
1216
1217 #define REG_A6XX_CP_MRB_REM_SIZE                0x00000933
1218
1219 #define REG_A6XX_CP_VSD_BASE                    0x00000934
1220
1221 #define REG_A6XX_CP_VSD_BASE_HI                 0x00000935
1222
1223 #define REG_A6XX_CP_MRB_DWORDS                  0x00000946
1224
1225 #define REG_A6XX_CP_VSD_DWORDS                  0x00000947
1226
1227 #define REG_A6XX_CP_CSQ_IB1_STAT                0x00000949
1228 #define A6XX_CP_CSQ_IB1_STAT_REM__MASK              0xffff0000
1229 #define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT             16
1230 static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
1231 {
1232     return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
1233 }
1234
1235 #define REG_A6XX_CP_CSQ_IB2_STAT                0x0000094a
1236 #define A6XX_CP_CSQ_IB2_STAT_REM__MASK              0xffff0000
1237 #define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT             16
1238 static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
1239 {
1240     return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1241 }
1242
1243 #define REG_A6XX_CP_MRQ_MRB_STAT                0x0000094c
1244 #define A6XX_CP_MRQ_MRB_STAT_REM__MASK              0xffff0000
1245 #define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT             16
1246 static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)
1247 {
1248     return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK;
1249 }
1250
1251 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO            0x00000980
1252
1253 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI            0x00000981
1254
1255 #define REG_A6XX_CP_AHB_CNTL                    0x0000098d
1256
1257 #define REG_A6XX_CP_APERTURE_CNTL_HOST              0x00000a00
1258
1259 #define REG_A6XX_CP_APERTURE_CNTL_CD                0x00000a03
1260
1261 #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE             0x00000b34
1262
1263 #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE             0x00000b82
1264
1265 #define REG_A6XX_VSC_ADDR_MODE_CNTL             0x00000c01
1266
1267 #define REG_A6XX_RBBM_INT_0_STATUS              0x00000201
1268
1269 #define REG_A6XX_RBBM_STATUS                    0x00000210
1270 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB           0x00800000
1271 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP            0x00400000
1272 #define A6XX_RBBM_STATUS_HLSQ_BUSY              0x00200000
1273 #define A6XX_RBBM_STATUS_VSC_BUSY               0x00100000
1274 #define A6XX_RBBM_STATUS_TPL1_BUSY              0x00080000
1275 #define A6XX_RBBM_STATUS_SP_BUSY                0x00040000
1276 #define A6XX_RBBM_STATUS_UCHE_BUSY              0x00020000
1277 #define A6XX_RBBM_STATUS_VPC_BUSY               0x00010000
1278 #define A6XX_RBBM_STATUS_VFD_BUSY               0x00008000
1279 #define A6XX_RBBM_STATUS_TESS_BUSY              0x00004000
1280 #define A6XX_RBBM_STATUS_PC_VSD_BUSY                0x00002000
1281 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY              0x00001000
1282 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY              0x00000800
1283 #define A6XX_RBBM_STATUS_LRZ_BUSY               0x00000400
1284 #define A6XX_RBBM_STATUS_A2D_BUSY               0x00000200
1285 #define A6XX_RBBM_STATUS_CCU_BUSY               0x00000100
1286 #define A6XX_RBBM_STATUS_RB_BUSY                0x00000080
1287 #define A6XX_RBBM_STATUS_RAS_BUSY               0x00000040
1288 #define A6XX_RBBM_STATUS_TSE_BUSY               0x00000020
1289 #define A6XX_RBBM_STATUS_VBIF_BUSY              0x00000010
1290 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY              0x00000008
1291 #define A6XX_RBBM_STATUS_CP_BUSY                0x00000004
1292 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER          0x00000002
1293 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER          0x00000001
1294
1295 #define REG_A6XX_RBBM_STATUS3                   0x00000213
1296 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT         0x01000000
1297
1298 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS          0x00000215
1299
1300 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
1301
1302 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
1303
1304 static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
1305
1306 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
1307
1308 static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
1309
1310 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
1311
1312 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
1313
1314 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
1315
1316 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
1317
1318 static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
1319
1320 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
1321
1322 static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
1323
1324 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
1325
1326 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
1327
1328 static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
1329
1330 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
1331
1332 #define REG_A6XX_RBBM_PERFCTR_CNTL              0x00000500
1333
1334 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0             0x00000501
1335
1336 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1             0x00000502
1337
1338 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2             0x00000503
1339
1340 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3             0x00000504
1341
1342 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO         0x00000505
1343
1344 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI         0x00000506
1345
1346 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
1347
1348 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED           0x0000050b
1349
1350 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD         0x0000050e
1351
1352 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS          0x0000050f
1353
1354 #define REG_A6XX_RBBM_ISDB_CNT                  0x00000533
1355
1356 #define REG_A6XX_RBBM_PRIMCTR_0_LO              0x00000540
1357
1358 #define REG_A6XX_RBBM_PRIMCTR_0_HI              0x00000541
1359
1360 #define REG_A6XX_RBBM_PRIMCTR_1_LO              0x00000542
1361
1362 #define REG_A6XX_RBBM_PRIMCTR_1_HI              0x00000543
1363
1364 #define REG_A6XX_RBBM_PRIMCTR_2_LO              0x00000544
1365
1366 #define REG_A6XX_RBBM_PRIMCTR_2_HI              0x00000545
1367
1368 #define REG_A6XX_RBBM_PRIMCTR_3_LO              0x00000546
1369
1370 #define REG_A6XX_RBBM_PRIMCTR_3_HI              0x00000547
1371
1372 #define REG_A6XX_RBBM_PRIMCTR_4_LO              0x00000548
1373
1374 #define REG_A6XX_RBBM_PRIMCTR_4_HI              0x00000549
1375
1376 #define REG_A6XX_RBBM_PRIMCTR_5_LO              0x0000054a
1377
1378 #define REG_A6XX_RBBM_PRIMCTR_5_HI              0x0000054b
1379
1380 #define REG_A6XX_RBBM_PRIMCTR_6_LO              0x0000054c
1381
1382 #define REG_A6XX_RBBM_PRIMCTR_6_HI              0x0000054d
1383
1384 #define REG_A6XX_RBBM_PRIMCTR_7_LO              0x0000054e
1385
1386 #define REG_A6XX_RBBM_PRIMCTR_7_HI              0x0000054f
1387
1388 #define REG_A6XX_RBBM_PRIMCTR_8_LO              0x00000550
1389
1390 #define REG_A6XX_RBBM_PRIMCTR_8_HI              0x00000551
1391
1392 #define REG_A6XX_RBBM_PRIMCTR_9_LO              0x00000552
1393
1394 #define REG_A6XX_RBBM_PRIMCTR_9_HI              0x00000553
1395
1396 #define REG_A6XX_RBBM_PRIMCTR_10_LO             0x00000554
1397
1398 #define REG_A6XX_RBBM_PRIMCTR_10_HI             0x00000555
1399
1400 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL             0x0000f400
1401
1402 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO        0x0000f800
1403
1404 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI        0x0000f801
1405
1406 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE           0x0000f802
1407
1408 #define REG_A6XX_RBBM_SECVID_TSB_CNTL               0x0000f803
1409
1410 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL         0x0000f810
1411
1412 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL          0x00000010
1413
1414 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL          0x00000011
1415
1416 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD         0x0000001c
1417 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE       0x00000001
1418
1419 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL           0x0000001f
1420
1421 #define REG_A6XX_RBBM_INT_CLEAR_CMD             0x00000037
1422
1423 #define REG_A6XX_RBBM_INT_0_MASK                0x00000038
1424
1425 #define REG_A6XX_RBBM_SP_HYST_CNT               0x00000042
1426
1427 #define REG_A6XX_RBBM_SW_RESET_CMD              0x00000043
1428
1429 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT             0x00000044
1430
1431 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD            0x00000045
1432
1433 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2           0x00000046
1434
1435 #define REG_A6XX_RBBM_CLOCK_CNTL                0x000000ae
1436
1437 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0                0x000000b0
1438
1439 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1                0x000000b1
1440
1441 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2                0x000000b2
1442
1443 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3                0x000000b3
1444
1445 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0               0x000000b4
1446
1447 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1               0x000000b5
1448
1449 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2               0x000000b6
1450
1451 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3               0x000000b7
1452
1453 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0               0x000000b8
1454
1455 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1               0x000000b9
1456
1457 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2               0x000000ba
1458
1459 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3               0x000000bb
1460
1461 #define REG_A6XX_RBBM_CLOCK_HYST_SP0                0x000000bc
1462
1463 #define REG_A6XX_RBBM_CLOCK_HYST_SP1                0x000000bd
1464
1465 #define REG_A6XX_RBBM_CLOCK_HYST_SP2                0x000000be
1466
1467 #define REG_A6XX_RBBM_CLOCK_HYST_SP3                0x000000bf
1468
1469 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0                0x000000c0
1470
1471 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1                0x000000c1
1472
1473 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2                0x000000c2
1474
1475 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3                0x000000c3
1476
1477 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0               0x000000c4
1478
1479 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1               0x000000c5
1480
1481 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2               0x000000c6
1482
1483 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3               0x000000c7
1484
1485 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0               0x000000c8
1486
1487 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1               0x000000c9
1488
1489 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2               0x000000ca
1490
1491 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3               0x000000cb
1492
1493 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0               0x000000cc
1494
1495 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1               0x000000cd
1496
1497 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2               0x000000ce
1498
1499 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3               0x000000cf
1500
1501 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0               0x000000d0
1502
1503 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1               0x000000d1
1504
1505 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2               0x000000d2
1506
1507 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3               0x000000d3
1508
1509 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0              0x000000d4
1510
1511 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1              0x000000d5
1512
1513 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2              0x000000d6
1514
1515 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3              0x000000d7
1516
1517 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0              0x000000d8
1518
1519 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1              0x000000d9
1520
1521 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2              0x000000da
1522
1523 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3              0x000000db
1524
1525 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0              0x000000dc
1526
1527 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1              0x000000dd
1528
1529 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2              0x000000de
1530
1531 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3              0x000000df
1532
1533 #define REG_A6XX_RBBM_CLOCK_HYST_TP0                0x000000e0
1534
1535 #define REG_A6XX_RBBM_CLOCK_HYST_TP1                0x000000e1
1536
1537 #define REG_A6XX_RBBM_CLOCK_HYST_TP2                0x000000e2
1538
1539 #define REG_A6XX_RBBM_CLOCK_HYST_TP3                0x000000e3
1540
1541 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0               0x000000e4
1542
1543 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1               0x000000e5
1544
1545 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2               0x000000e6
1546
1547 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3               0x000000e7
1548
1549 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0               0x000000e8
1550
1551 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1               0x000000e9
1552
1553 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2               0x000000ea
1554
1555 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3               0x000000eb
1556
1557 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0               0x000000ec
1558
1559 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1               0x000000ed
1560
1561 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2               0x000000ee
1562
1563 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3               0x000000ef
1564
1565 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0                0x000000f0
1566
1567 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1                0x000000f1
1568
1569 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2                0x000000f2
1570
1571 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3                0x000000f3
1572
1573 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0               0x000000f4
1574
1575 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1               0x000000f5
1576
1577 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2               0x000000f6
1578
1579 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3               0x000000f7
1580
1581 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0               0x000000f8
1582
1583 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1               0x000000f9
1584
1585 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2               0x000000fa
1586
1587 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3               0x000000fb
1588
1589 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0            0x00000100
1590
1591 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1            0x00000101
1592
1593 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2            0x00000102
1594
1595 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3            0x00000103
1596
1597 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC                0x00000104
1598
1599 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC               0x00000105
1600
1601 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC               0x00000106
1602
1603 #define REG_A6XX_RBBM_CLOCK_HYST_RAC                0x00000107
1604
1605 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM           0x00000108
1606
1607 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM          0x00000109
1608
1609 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM           0x0000010a
1610
1611 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE               0x0000010b
1612
1613 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE              0x0000010c
1614
1615 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE              0x0000010d
1616
1617 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE              0x0000010e
1618
1619 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE              0x0000010f
1620
1621 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE               0x00000110
1622
1623 #define REG_A6XX_RBBM_CLOCK_MODE_VFD                0x00000111
1624
1625 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD               0x00000112
1626
1627 #define REG_A6XX_RBBM_CLOCK_HYST_VFD                0x00000113
1628
1629 #define REG_A6XX_RBBM_CLOCK_MODE_GPC                0x00000114
1630
1631 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC               0x00000115
1632
1633 #define REG_A6XX_RBBM_CLOCK_HYST_GPC                0x00000116
1634
1635 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2            0x00000117
1636
1637 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX             0x00000118
1638
1639 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX            0x00000119
1640
1641 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX             0x0000011a
1642
1643 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ               0x0000011b
1644
1645 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ              0x0000011c
1646
1647 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ               0x0000011d
1648
1649 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE           0x00000120
1650
1651 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE          0x00000121
1652
1653 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE           0x00000122
1654
1655 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A              0x00000600
1656
1657 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B              0x00000601
1658
1659 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C              0x00000602
1660
1661 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D              0x00000603
1662 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK     0x000000ff
1663 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT        0
1664 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
1665 {
1666     return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
1667 }
1668 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK       0x0000ff00
1669 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT      8
1670 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
1671 {
1672     return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
1673 }
1674
1675 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT              0x00000604
1676 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK        0x0000003f
1677 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT       0
1678 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
1679 {
1680     return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
1681 }
1682 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK          0x00007000
1683 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT         12
1684 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
1685 {
1686     return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
1687 }
1688 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK           0xf0000000
1689 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT          28
1690 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
1691 {
1692     return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
1693 }
1694
1695 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM              0x00000605
1696 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK         0x0f000000
1697 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT        24
1698 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
1699 {
1700     return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
1701 }
1702
1703 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0             0x00000608
1704
1705 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1             0x00000609
1706
1707 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2             0x0000060a
1708
1709 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3             0x0000060b
1710
1711 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0            0x0000060c
1712
1713 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1            0x0000060d
1714
1715 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2            0x0000060e
1716
1717 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3            0x0000060f
1718
1719 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0            0x00000610
1720 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK       0x0000000f
1721 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT      0
1722 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
1723 {
1724     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
1725 }
1726 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK       0x000000f0
1727 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT      4
1728 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
1729 {
1730     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
1731 }
1732 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK       0x00000f00
1733 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT      8
1734 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
1735 {
1736     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
1737 }
1738 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK       0x0000f000
1739 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT      12
1740 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
1741 {
1742     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
1743 }
1744 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK       0x000f0000
1745 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT      16
1746 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
1747 {
1748     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
1749 }
1750 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK       0x00f00000
1751 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT      20
1752 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
1753 {
1754     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
1755 }
1756 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK       0x0f000000
1757 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT      24
1758 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
1759 {
1760     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
1761 }
1762 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK       0xf0000000
1763 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT      28
1764 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
1765 {
1766     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
1767 }
1768
1769 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1            0x00000611
1770 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK       0x0000000f
1771 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT      0
1772 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
1773 {
1774     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
1775 }
1776 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK       0x000000f0
1777 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT      4
1778 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
1779 {
1780     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
1781 }
1782 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK      0x00000f00
1783 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT     8
1784 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
1785 {
1786     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
1787 }
1788 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK      0x0000f000
1789 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT     12
1790 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
1791 {
1792     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
1793 }
1794 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK      0x000f0000
1795 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT     16
1796 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
1797 {
1798     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
1799 }
1800 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK      0x00f00000
1801 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT     20
1802 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
1803 {
1804     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
1805 }
1806 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK      0x0f000000
1807 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT     24
1808 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
1809 {
1810     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
1811 }
1812 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK      0xf0000000
1813 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT     28
1814 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
1815 {
1816     return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
1817 }
1818
1819 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1         0x0000062f
1820
1821 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2         0x00000630
1822
1823 static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
1824
1825 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE         0x0000c800
1826
1827 #define REG_A6XX_HLSQ_DBG_READ_SEL              0x0000d000
1828
1829 #define REG_A6XX_UCHE_ADDR_MODE_CNTL                0x00000e00
1830
1831 #define REG_A6XX_UCHE_MODE_CNTL                 0x00000e01
1832
1833 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO            0x00000e05
1834
1835 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI            0x00000e06
1836
1837 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO            0x00000e07
1838
1839 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI            0x00000e08
1840
1841 #define REG_A6XX_UCHE_TRAP_BASE_LO              0x00000e09
1842
1843 #define REG_A6XX_UCHE_TRAP_BASE_HI              0x00000e0a
1844
1845 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO             0x00000e0b
1846
1847 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI             0x00000e0c
1848
1849 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO             0x00000e0d
1850
1851 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI             0x00000e0e
1852
1853 #define REG_A6XX_UCHE_CACHE_WAYS                0x00000e17
1854
1855 #define REG_A6XX_UCHE_FILTER_CNTL               0x00000e18
1856
1857 #define REG_A6XX_UCHE_CLIENT_PF                 0x00000e19
1858 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK           0x000000ff
1859 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT          0
1860 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
1861 {
1862     return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
1863 }
1864
1865 static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
1866
1867 #define REG_A6XX_UCHE_CMDQ_CONFIG               0x00000e3c
1868
1869 #define REG_A6XX_VBIF_VERSION                   0x00003000
1870
1871 #define REG_A6XX_VBIF_CLKON                 0x00003001
1872 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS            0x00000002
1873
1874 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN             0x0000302a
1875
1876 #define REG_A6XX_VBIF_XIN_HALT_CTRL0                0x00003080
1877
1878 #define REG_A6XX_VBIF_XIN_HALT_CTRL1                0x00003081
1879
1880 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL             0x00003084
1881
1882 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0               0x00003085
1883
1884 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1               0x00003086
1885 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK        0x0000000f
1886 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT       0
1887 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
1888 {
1889     return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
1890 }
1891
1892 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0               0x00003087
1893
1894 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1               0x00003088
1895 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK        0x000001ff
1896 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT       0
1897 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
1898 {
1899     return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
1900 }
1901
1902 #define REG_A6XX_VBIF_TEST_BUS_OUT              0x0000308c
1903
1904 #define REG_A6XX_VBIF_PERF_CNT_SEL0             0x000030d0
1905
1906 #define REG_A6XX_VBIF_PERF_CNT_SEL1             0x000030d1
1907
1908 #define REG_A6XX_VBIF_PERF_CNT_SEL2             0x000030d2
1909
1910 #define REG_A6XX_VBIF_PERF_CNT_SEL3             0x000030d3
1911
1912 #define REG_A6XX_VBIF_PERF_CNT_LOW0             0x000030d8
1913
1914 #define REG_A6XX_VBIF_PERF_CNT_LOW1             0x000030d9
1915
1916 #define REG_A6XX_VBIF_PERF_CNT_LOW2             0x000030da
1917
1918 #define REG_A6XX_VBIF_PERF_CNT_LOW3             0x000030db
1919
1920 #define REG_A6XX_VBIF_PERF_CNT_HIGH0                0x000030e0
1921
1922 #define REG_A6XX_VBIF_PERF_CNT_HIGH1                0x000030e1
1923
1924 #define REG_A6XX_VBIF_PERF_CNT_HIGH2                0x000030e2
1925
1926 #define REG_A6XX_VBIF_PERF_CNT_HIGH3                0x000030e3
1927
1928 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0              0x00003100
1929
1930 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1              0x00003101
1931
1932 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2              0x00003102
1933
1934 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0             0x00003110
1935
1936 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1             0x00003111
1937
1938 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2             0x00003112
1939
1940 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0            0x00003118
1941
1942 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1            0x00003119
1943
1944 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2            0x0000311a
1945
1946 #define REG_A6XX_GBIF_SCACHE_CNTL0              0x00003c01
1947
1948 #define REG_A6XX_GBIF_SCACHE_CNTL1              0x00003c02
1949
1950 #define REG_A6XX_GBIF_QSB_SIDE0                 0x00003c03
1951
1952 #define REG_A6XX_GBIF_QSB_SIDE1                 0x00003c04
1953
1954 #define REG_A6XX_GBIF_QSB_SIDE2                 0x00003c05
1955
1956 #define REG_A6XX_GBIF_QSB_SIDE3                 0x00003c06
1957
1958 #define REG_A6XX_GBIF_HALT                  0x00003c45
1959
1960 #define REG_A6XX_GBIF_HALT_ACK                  0x00003c46
1961
1962 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN               0x00003cc0
1963
1964 #define REG_A6XX_GBIF_PERF_CNT_SEL              0x00003cc2
1965
1966 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL              0x00003cc3
1967
1968 #define REG_A6XX_GBIF_PERF_CNT_LOW0             0x00003cc4
1969
1970 #define REG_A6XX_GBIF_PERF_CNT_LOW1             0x00003cc5
1971
1972 #define REG_A6XX_GBIF_PERF_CNT_LOW2             0x00003cc6
1973
1974 #define REG_A6XX_GBIF_PERF_CNT_LOW3             0x00003cc7
1975
1976 #define REG_A6XX_GBIF_PERF_CNT_HIGH0                0x00003cc8
1977
1978 #define REG_A6XX_GBIF_PERF_CNT_HIGH1                0x00003cc9
1979
1980 #define REG_A6XX_GBIF_PERF_CNT_HIGH2                0x00003cca
1981
1982 #define REG_A6XX_GBIF_PERF_CNT_HIGH3                0x00003ccb
1983
1984 #define REG_A6XX_GBIF_PWR_CNT_LOW0              0x00003ccc
1985
1986 #define REG_A6XX_GBIF_PWR_CNT_LOW1              0x00003ccd
1987
1988 #define REG_A6XX_GBIF_PWR_CNT_LOW2              0x00003cce
1989
1990 #define REG_A6XX_GBIF_PWR_CNT_HIGH0             0x00003ccf
1991
1992 #define REG_A6XX_GBIF_PWR_CNT_HIGH1             0x00003cd0
1993
1994 #define REG_A6XX_GBIF_PWR_CNT_HIGH2             0x00003cd1
1995
1996 #define REG_A6XX_VSC_DBG_ECO_CNTL               0x00000c00
1997
1998 #define REG_A6XX_VSC_BIN_SIZE                   0x00000c02
1999 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK               0x000000ff
2000 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT              0
2001 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2002 {
2003     return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2004 }
2005 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK              0x0001ff00
2006 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT             8
2007 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2008 {
2009     return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2010 }
2011
2012 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS         0x00000c03
2013
2014 #define REG_A6XX_VSC_BIN_COUNT                  0x00000c06
2015 #define A6XX_VSC_BIN_COUNT_NX__MASK             0x000007fe
2016 #define A6XX_VSC_BIN_COUNT_NX__SHIFT                1
2017 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2018 {
2019     return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
2020 }
2021 #define A6XX_VSC_BIN_COUNT_NY__MASK             0x001ff800
2022 #define A6XX_VSC_BIN_COUNT_NY__SHIFT                11
2023 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
2024 {
2025     return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
2026 }
2027
2028 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2029
2030 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2031 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK            0x000003ff
2032 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT           0
2033 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2034 {
2035     return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
2036 }
2037 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK            0x000ffc00
2038 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT           10
2039 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2040 {
2041     return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2042 }
2043 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK            0x03f00000
2044 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT           20
2045 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2046 {
2047     return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
2048 }
2049 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK            0xfc000000
2050 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT           26
2051 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2052 {
2053     return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2054 }
2055
2056 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS              0x00000c30
2057
2058 #define REG_A6XX_VSC_PRIM_STRM_PITCH                0x00000c32
2059
2060 #define REG_A6XX_VSC_PRIM_STRM_LIMIT                0x00000c33
2061
2062 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS              0x00000c34
2063
2064 #define REG_A6XX_VSC_DRAW_STRM_PITCH                0x00000c36
2065
2066 #define REG_A6XX_VSC_DRAW_STRM_LIMIT                0x00000c37
2067
2068 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2069
2070 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2071
2072 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2073
2074 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2075
2076 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2077
2078 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2079
2080 #define REG_A6XX_UCHE_UNKNOWN_0E12              0x00000e12
2081
2082 #define REG_A6XX_GRAS_CL_CNTL                   0x00008000
2083 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE              0x00000001
2084 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE            0x00000002
2085 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE         0x00000004
2086 #define A6XX_GRAS_CL_CNTL_UNK5                  0x00000020
2087 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z           0x00000040
2088 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE           0x00000080
2089 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE          0x00000100
2090 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE        0x00000200
2091
2092 #define REG_A6XX_GRAS_VS_CL_CNTL                0x00008001
2093 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK            0x000000ff
2094 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT           0
2095 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2096 {
2097     return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2098 }
2099 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK            0x0000ff00
2100 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT           8
2101 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2102 {
2103     return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2104 }
2105
2106 #define REG_A6XX_GRAS_DS_CL_CNTL                0x00008002
2107 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK            0x000000ff
2108 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT           0
2109 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
2110 {
2111     return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
2112 }
2113 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK            0x0000ff00
2114 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT           8
2115 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
2116 {
2117     return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
2118 }
2119
2120 #define REG_A6XX_GRAS_GS_CL_CNTL                0x00008003
2121 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK            0x000000ff
2122 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT           0
2123 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
2124 {
2125     return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
2126 }
2127 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK            0x0000ff00
2128 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT           8
2129 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
2130 {
2131     return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
2132 }
2133
2134 #define REG_A6XX_GRAS_MAX_LAYER_INDEX               0x00008004
2135
2136 #define REG_A6XX_GRAS_CNTL                  0x00008005
2137 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL               0x00000001
2138 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID            0x00000002
2139 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE              0x00000004
2140 #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL              0x00000008
2141 #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID           0x00000010
2142 #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE             0x00000020
2143 #define A6XX_GRAS_CNTL_COORD_MASK__MASK             0x000003c0
2144 #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT            6
2145 static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2146 {
2147     return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
2148 }
2149
2150 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ         0x00008006
2151 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK      0x000001ff
2152 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT     0
2153 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2154 {
2155     return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2156 }
2157 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK      0x0007fc00
2158 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT     10
2159 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2160 {
2161     return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2162 }
2163
2164 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2165
2166 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2167 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK            0xffffffff
2168 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT           0
2169 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
2170 {
2171     return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
2172 }
2173
2174 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
2175 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK             0xffffffff
2176 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT            0
2177 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
2178 {
2179     return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
2180 }
2181
2182 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
2183 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK            0xffffffff
2184 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT           0
2185 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
2186 {
2187     return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
2188 }
2189
2190 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
2191 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK             0xffffffff
2192 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT            0
2193 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
2194 {
2195     return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
2196 }
2197
2198 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
2199 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK            0xffffffff
2200 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT           0
2201 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
2202 {
2203     return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
2204 }
2205
2206 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
2207 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK             0xffffffff
2208 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT            0
2209 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
2210 {
2211     return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
2212 }
2213
2214 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2215
2216 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2217 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK              0xffffffff
2218 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT             0
2219 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
2220 {
2221     return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
2222 }
2223
2224 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
2225 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK              0xffffffff
2226 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT             0
2227 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
2228 {
2229     return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
2230 }
2231
2232 #define REG_A6XX_GRAS_SU_CNTL                   0x00008090
2233 #define A6XX_GRAS_SU_CNTL_CULL_FRONT                0x00000001
2234 #define A6XX_GRAS_SU_CNTL_CULL_BACK             0x00000002
2235 #define A6XX_GRAS_SU_CNTL_FRONT_CW              0x00000004
2236 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK           0x000007f8
2237 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT          3
2238 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2239 {
2240     return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2241 }
2242 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET               0x00000800
2243 #define A6XX_GRAS_SU_CNTL_UNK12__MASK               0x00001000
2244 #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT              12
2245 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
2246 {
2247     return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2248 }
2249 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK           0x00002000
2250 #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT          13
2251 static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
2252 {
2253     return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK;
2254 }
2255 #define A6XX_GRAS_SU_CNTL_UNK15__MASK               0x00018000
2256 #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT              15
2257 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2258 {
2259     return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2260 }
2261 #define A6XX_GRAS_SU_CNTL_UNK17                 0x00020000
2262 #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE          0x00040000
2263 #define A6XX_GRAS_SU_CNTL_UNK19__MASK               0x00780000
2264 #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT              19
2265 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
2266 {
2267     return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
2268 }
2269
2270 #define REG_A6XX_GRAS_SU_POINT_MINMAX               0x00008091
2271 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK         0x0000ffff
2272 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT            0
2273 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2274 {
2275     return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2276 }
2277 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK         0xffff0000
2278 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT            16
2279 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2280 {
2281     return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2282 }
2283
2284 #define REG_A6XX_GRAS_SU_POINT_SIZE             0x00008092
2285 #define A6XX_GRAS_SU_POINT_SIZE__MASK               0x0000ffff
2286 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT              0
2287 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2288 {
2289     return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2290 }
2291
2292 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL           0x00008094
2293 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK      0x00000003
2294 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT     0
2295 static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
2296 {
2297     return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
2298 }
2299
2300 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE          0x00008095
2301 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK            0xffffffff
2302 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT           0
2303 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2304 {
2305     return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2306 }
2307
2308 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET         0x00008096
2309 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK           0xffffffff
2310 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT          0
2311 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2312 {
2313     return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2314 }
2315
2316 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP       0x00008097
2317 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK     0xffffffff
2318 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT        0
2319 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2320 {
2321     return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2322 }
2323
2324 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO          0x00008098
2325 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK   0x00000007
2326 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT  0
2327 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2328 {
2329     return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2330 }
2331 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK       0x00000008
2332 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT      3
2333 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
2334 {
2335     return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
2336 }
2337
2338 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL          0x00008099
2339 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN    0x00000001
2340 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK    0x00000006
2341 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT   1
2342 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val)
2343 {
2344     return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK;
2345 }
2346 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN   0x00000008
2347 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK       0x00000030
2348 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT      4
2349 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val)
2350 {
2351     return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK;
2352 }
2353
2354 #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL            0x0000809a
2355 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0           0x00000001
2356 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN       0x00000002
2357
2358 #define REG_A6XX_GRAS_VS_LAYER_CNTL             0x0000809b
2359 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER            0x00000001
2360 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW         0x00000002
2361
2362 #define REG_A6XX_GRAS_GS_LAYER_CNTL             0x0000809c
2363 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER            0x00000001
2364 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW         0x00000002
2365
2366 #define REG_A6XX_GRAS_DS_LAYER_CNTL             0x0000809d
2367 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER            0x00000001
2368 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW         0x00000002
2369
2370 #define REG_A6XX_GRAS_SC_CNTL                   0x000080a0
2371 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK      0x00000007
2372 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT     0
2373 static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
2374 {
2375     return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK;
2376 }
2377 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK        0x00000018
2378 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT       3
2379 static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val)
2380 {
2381     return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK;
2382 }
2383 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK         0x00000020
2384 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT            5
2385 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
2386 {
2387     return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK;
2388 }
2389 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK        0x000000c0
2390 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT       6
2391 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
2392 {
2393     return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK;
2394 }
2395 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK   0x00000100
2396 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT  8
2397 static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val)
2398 {
2399     return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK;
2400 }
2401 #define A6XX_GRAS_SC_CNTL_UNK9__MASK                0x00000e00
2402 #define A6XX_GRAS_SC_CNTL_UNK9__SHIFT               9
2403 static inline uint32_t A6XX_GRAS_SC_CNTL_UNK9(uint32_t val)
2404 {
2405     return ((val) << A6XX_GRAS_SC_CNTL_UNK9__SHIFT) & A6XX_GRAS_SC_CNTL_UNK9__MASK;
2406 }
2407 #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN             0x00001000
2408
2409 #define REG_A6XX_GRAS_BIN_CONTROL               0x000080a1
2410 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK            0x0000003f
2411 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT           0
2412 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2413 {
2414     return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2415 }
2416 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK            0x00007f00
2417 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT           8
2418 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2419 {
2420     return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2421 }
2422 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK         0x001c0000
2423 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT        18
2424 static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
2425 {
2426     return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK;
2427 }
2428 #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS       0x00200000
2429 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK        0x00c00000
2430 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT       22
2431 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
2432 {
2433     return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK;
2434 }
2435 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
2436 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT    24
2437 static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
2438 {
2439     return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
2440 }
2441 #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK           0x08000000
2442 #define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT          27
2443 static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val)
2444 {
2445     return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK;
2446 }
2447
2448 #define REG_A6XX_GRAS_RAS_MSAA_CNTL             0x000080a2
2449 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK           0x00000003
2450 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT          0
2451 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2452 {
2453     return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2454 }
2455 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK          0x00000004
2456 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT         2
2457 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
2458 {
2459     return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
2460 }
2461 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK          0x00000008
2462 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT         3
2463 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
2464 {
2465     return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
2466 }
2467
2468 #define REG_A6XX_GRAS_DEST_MSAA_CNTL                0x000080a3
2469 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK          0x00000003
2470 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT         0
2471 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2472 {
2473     return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
2474 }
2475 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE           0x00000004
2476
2477 #define REG_A6XX_GRAS_SAMPLE_CONFIG             0x000080a4
2478 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0                0x00000001
2479 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE         0x00000002
2480
2481 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0             0x000080a5
2482 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK        0x0000000f
2483 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT       0
2484 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
2485 {
2486     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
2487 }
2488 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK        0x000000f0
2489 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT       4
2490 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
2491 {
2492     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
2493 }
2494 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK        0x00000f00
2495 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT       8
2496 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
2497 {
2498     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
2499 }
2500 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK        0x0000f000
2501 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT       12
2502 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
2503 {
2504     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
2505 }
2506 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK        0x000f0000
2507 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT       16
2508 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
2509 {
2510     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
2511 }
2512 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK        0x00f00000
2513 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT       20
2514 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
2515 {
2516     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
2517 }
2518 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK        0x0f000000
2519 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT       24
2520 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
2521 {
2522     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
2523 }
2524 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK        0xf0000000
2525 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT       28
2526 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
2527 {
2528     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
2529 }
2530
2531 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1             0x000080a6
2532 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK        0x0000000f
2533 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT       0
2534 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
2535 {
2536     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
2537 }
2538 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK        0x000000f0
2539 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT       4
2540 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
2541 {
2542     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
2543 }
2544 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK        0x00000f00
2545 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT       8
2546 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
2547 {
2548     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
2549 }
2550 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK        0x0000f000
2551 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT       12
2552 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
2553 {
2554     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
2555 }
2556 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK        0x000f0000
2557 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT       16
2558 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
2559 {
2560     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
2561 }
2562 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK        0x00f00000
2563 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT       20
2564 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
2565 {
2566     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
2567 }
2568 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK        0x0f000000
2569 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT       24
2570 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
2571 {
2572     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
2573 }
2574 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK        0xf0000000
2575 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT       28
2576 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
2577 {
2578     return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
2579 }
2580
2581 #define REG_A6XX_GRAS_UNKNOWN_80AF              0x000080af
2582
2583 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
2584
2585 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
2586 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK          0x0000ffff
2587 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT         0
2588 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2589 {
2590     return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2591 }
2592 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK          0xffff0000
2593 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT         16
2594 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2595 {
2596     return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2597 }
2598
2599 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
2600 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK          0x0000ffff
2601 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT         0
2602 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2603 {
2604     return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2605 }
2606 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK          0xffff0000
2607 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT         16
2608 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2609 {
2610     return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2611 }
2612
2613 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
2614
2615 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
2616 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK        0x0000ffff
2617 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT       0
2618 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
2619 {
2620     return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
2621 }
2622 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK        0xffff0000
2623 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT       16
2624 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
2625 {
2626     return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
2627 }
2628
2629 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
2630 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK        0x0000ffff
2631 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT       0
2632 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
2633 {
2634     return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
2635 }
2636 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK        0xffff0000
2637 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT       16
2638 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
2639 {
2640     return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
2641 }
2642
2643 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL          0x000080f0
2644 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK          0x00003fff
2645 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT         0
2646 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2647 {
2648     return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2649 }
2650 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK          0x3fff0000
2651 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT         16
2652 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2653 {
2654     return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2655 }
2656
2657 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR          0x000080f1
2658 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK          0x00003fff
2659 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT         0
2660 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2661 {
2662     return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2663 }
2664 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK          0x3fff0000
2665 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT         16
2666 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2667 {
2668     return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2669 }
2670
2671 #define REG_A6XX_GRAS_LRZ_CNTL                  0x00008100
2672 #define A6XX_GRAS_LRZ_CNTL_ENABLE               0x00000001
2673 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE                0x00000002
2674 #define A6XX_GRAS_LRZ_CNTL_GREATER              0x00000004
2675 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE                0x00000008
2676 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE            0x00000010
2677 #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE          0x00000020
2678 #define A6XX_GRAS_LRZ_CNTL_UNK6__MASK               0x000003c0
2679 #define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT              6
2680 static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
2681 {
2682     return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
2683 }
2684
2685 #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL             0x00008101
2686 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID            0x00000001
2687 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK   0x00000006
2688 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT  1
2689 static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
2690 {
2691     return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK;
2692 }
2693
2694 #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0            0x00008102
2695 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK     0x000000ff
2696 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT    0
2697 static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val)
2698 {
2699     return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK;
2700 }
2701
2702 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE               0x00008103
2703 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK             0xffffffff
2704 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT            0
2705 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
2706 {
2707     return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
2708 }
2709
2710 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH              0x00008105
2711 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK          0x000000ff
2712 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT         0
2713 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
2714 {
2715     return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
2716 }
2717 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK        0x1ffffc00
2718 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT       10
2719 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
2720 {
2721     return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
2722 }
2723
2724 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE        0x00008106
2725 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK      0xffffffff
2726 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT     0
2727 static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
2728 {
2729     return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
2730 }
2731
2732 #define REG_A6XX_GRAS_SAMPLE_CNTL               0x00008109
2733 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE         0x00000001
2734
2735 #define REG_A6XX_GRAS_UNKNOWN_810A              0x0000810a
2736 #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK           0x000007ff
2737 #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT          0
2738 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)
2739 {
2740     return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK;
2741 }
2742 #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK          0x07ff0000
2743 #define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT         16
2744 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)
2745 {
2746     return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK;
2747 }
2748 #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK          0xf0000000
2749 #define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT         28
2750 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)
2751 {
2752     return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK;
2753 }
2754
2755 #define REG_A6XX_GRAS_UNKNOWN_8110              0x00008110
2756
2757 #define REG_A6XX_GRAS_2D_BLIT_CNTL              0x00008400
2758 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK         0x00000007
2759 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT            0
2760 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
2761 {
2762     return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
2763 }
2764 #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN          0x00000008
2765 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK           0x00000070
2766 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT          4
2767 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val)
2768 {
2769     return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK;
2770 }
2771 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR          0x00000080
2772 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK       0x0000ff00
2773 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT      8
2774 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
2775 {
2776     return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
2777 }
2778 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR              0x00010000
2779 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK          0x00060000
2780 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT         17
2781 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
2782 {
2783     return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
2784 }
2785 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8                0x00080000
2786 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK           0x00f00000
2787 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT          20
2788 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
2789 {
2790     return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
2791 }
2792 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK           0x1f000000
2793 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT          24
2794 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
2795 {
2796     return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
2797 }
2798 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK        0x20000000
2799 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT       29
2800 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
2801 {
2802     return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK;
2803 }
2804
2805 #define REG_A6XX_GRAS_2D_SRC_TL_X               0x00008401
2806
2807 #define REG_A6XX_GRAS_2D_SRC_BR_X               0x00008402
2808
2809 #define REG_A6XX_GRAS_2D_SRC_TL_Y               0x00008403
2810
2811 #define REG_A6XX_GRAS_2D_SRC_BR_Y               0x00008404
2812
2813 #define REG_A6XX_GRAS_2D_DST_TL                 0x00008405
2814 #define A6XX_GRAS_2D_DST_TL_X__MASK             0x00003fff
2815 #define A6XX_GRAS_2D_DST_TL_X__SHIFT                0
2816 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
2817 {
2818     return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
2819 }
2820 #define A6XX_GRAS_2D_DST_TL_Y__MASK             0x3fff0000
2821 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT                16
2822 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
2823 {
2824     return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
2825 }
2826
2827 #define REG_A6XX_GRAS_2D_DST_BR                 0x00008406
2828 #define A6XX_GRAS_2D_DST_BR_X__MASK             0x00003fff
2829 #define A6XX_GRAS_2D_DST_BR_X__SHIFT                0
2830 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
2831 {
2832     return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
2833 }
2834 #define A6XX_GRAS_2D_DST_BR_Y__MASK             0x3fff0000
2835 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT                16
2836 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
2837 {
2838     return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
2839 }
2840
2841 #define REG_A6XX_GRAS_2D_UNKNOWN_8407               0x00008407
2842
2843 #define REG_A6XX_GRAS_2D_UNKNOWN_8408               0x00008408
2844
2845 #define REG_A6XX_GRAS_2D_UNKNOWN_8409               0x00008409
2846
2847 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1             0x0000840a
2848 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK         0x00003fff
2849 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT            0
2850 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
2851 {
2852     return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
2853 }
2854 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK         0x3fff0000
2855 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT            16
2856 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
2857 {
2858     return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
2859 }
2860
2861 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2             0x0000840b
2862 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK         0x00003fff
2863 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT            0
2864 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
2865 {
2866     return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
2867 }
2868 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK         0x3fff0000
2869 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT            16
2870 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
2871 {
2872     return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
2873 }
2874
2875 #define REG_A6XX_GRAS_DBG_ECO_CNTL              0x00008600
2876 #define A6XX_GRAS_DBG_ECO_CNTL_UNK7             0x00000080
2877 #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS          0x00000800
2878
2879 #define REG_A6XX_GRAS_ADDR_MODE_CNTL                0x00008601
2880
2881 static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
2882
2883 static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
2884
2885 static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
2886
2887 #define REG_A6XX_RB_BIN_CONTROL                 0x00008800
2888 #define A6XX_RB_BIN_CONTROL_BINW__MASK              0x0000003f
2889 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT             0
2890 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
2891 {
2892     return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
2893 }
2894 #define A6XX_RB_BIN_CONTROL_BINH__MASK              0x00007f00
2895 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT             8
2896 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
2897 {
2898     return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
2899 }
2900 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK           0x001c0000
2901 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT          18
2902 static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
2903 {
2904     return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK;
2905 }
2906 #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS         0x00200000
2907 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK      0x00c00000
2908 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT     22
2909 static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
2910 {
2911     return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK;
2912 }
2913 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK   0x07000000
2914 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT  24
2915 static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
2916 {
2917     return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
2918 }
2919
2920 #define REG_A6XX_RB_RENDER_CNTL                 0x00008801
2921 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK    0x00000038
2922 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT   3
2923 static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
2924 {
2925     return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK;
2926 }
2927 #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN           0x00000040
2928 #define A6XX_RB_RENDER_CNTL_BINNING             0x00000080
2929 #define A6XX_RB_RENDER_CNTL_UNK8__MASK              0x00000700
2930 #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT             8
2931 static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
2932 {
2933     return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
2934 }
2935 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK           0x00000100
2936 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT          8
2937 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
2938 {
2939     return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK;
2940 }
2941 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK      0x00000600
2942 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT     9
2943 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
2944 {
2945     return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK;
2946 }
2947 #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN           0x00000800
2948 #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN      0x00001000
2949 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH              0x00004000
2950 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK         0x00ff0000
2951 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT            16
2952 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2953 {
2954     return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2955 }
2956
2957 #define REG_A6XX_RB_RAS_MSAA_CNTL               0x00008802
2958 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK         0x00000003
2959 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT            0
2960 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2961 {
2962     return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2963 }
2964 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK            0x00000004
2965 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT           2
2966 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
2967 {
2968     return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
2969 }
2970 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK            0x00000008
2971 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT           3
2972 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
2973 {
2974     return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
2975 }
2976
2977 #define REG_A6XX_RB_DEST_MSAA_CNTL              0x00008803
2978 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK            0x00000003
2979 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT           0
2980 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2981 {
2982     return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2983 }
2984 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE         0x00000004
2985
2986 #define REG_A6XX_RB_SAMPLE_CONFIG               0x00008804
2987 #define A6XX_RB_SAMPLE_CONFIG_UNK0              0x00000001
2988 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE           0x00000002
2989
2990 #define REG_A6XX_RB_SAMPLE_LOCATION_0               0x00008805
2991 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK      0x0000000f
2992 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT     0
2993 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
2994 {
2995     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
2996 }
2997 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK      0x000000f0
2998 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT     4
2999 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
3000 {
3001     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
3002 }
3003 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK      0x00000f00
3004 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT     8
3005 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
3006 {
3007     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
3008 }
3009 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK      0x0000f000
3010 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT     12
3011 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
3012 {
3013     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
3014 }
3015 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK      0x000f0000
3016 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT     16
3017 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
3018 {
3019     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
3020 }
3021 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK      0x00f00000
3022 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT     20
3023 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
3024 {
3025     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
3026 }
3027 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK      0x0f000000
3028 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT     24
3029 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
3030 {
3031     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
3032 }
3033 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK      0xf0000000
3034 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT     28
3035 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
3036 {
3037     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
3038 }
3039
3040 #define REG_A6XX_RB_SAMPLE_LOCATION_1               0x00008806
3041 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK      0x0000000f
3042 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT     0
3043 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
3044 {
3045     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
3046 }
3047 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK      0x000000f0
3048 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT     4
3049 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
3050 {
3051     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
3052 }
3053 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK      0x00000f00
3054 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT     8
3055 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
3056 {
3057     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
3058 }
3059 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK      0x0000f000
3060 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT     12
3061 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
3062 {
3063     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
3064 }
3065 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK      0x000f0000
3066 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT     16
3067 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
3068 {
3069     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
3070 }
3071 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK      0x00f00000
3072 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT     20
3073 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
3074 {
3075     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
3076 }
3077 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK      0x0f000000
3078 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT     24
3079 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
3080 {
3081     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
3082 }
3083 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK      0xf0000000
3084 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT     28
3085 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
3086 {
3087     return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
3088 }
3089
3090 #define REG_A6XX_RB_RENDER_CONTROL0             0x00008809
3091 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL          0x00000001
3092 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID       0x00000002
3093 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE         0x00000004
3094 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL         0x00000008
3095 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID      0x00000010
3096 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE        0x00000020
3097 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK        0x000003c0
3098 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT       6
3099 static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3100 {
3101     return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3102 }
3103 #define A6XX_RB_RENDER_CONTROL0_UNK10               0x00000400
3104
3105 #define REG_A6XX_RB_RENDER_CONTROL1             0x0000880a
3106 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK          0x00000001
3107 #define A6XX_RB_RENDER_CONTROL1_UNK1                0x00000002
3108 #define A6XX_RB_RENDER_CONTROL1_FACENESS            0x00000004
3109 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID            0x00000008
3110 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK   0x00000030
3111 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT  4
3112 static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
3113 {
3114     return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK;
3115 }
3116 #define A6XX_RB_RENDER_CONTROL1_SIZE                0x00000040
3117 #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN            0x00000080
3118 #define A6XX_RB_RENDER_CONTROL1_FOVEATION           0x00000100
3119
3120 #define REG_A6XX_RB_FS_OUTPUT_CNTL0             0x0000880b
3121 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE        0x00000001
3122 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z           0x00000002
3123 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK        0x00000004
3124 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF      0x00000008
3125
3126 #define REG_A6XX_RB_FS_OUTPUT_CNTL1             0x0000880c
3127 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK           0x0000000f
3128 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT          0
3129 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
3130 {
3131     return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
3132 }
3133
3134 #define REG_A6XX_RB_RENDER_COMPONENTS               0x0000880d
3135 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK         0x0000000f
3136 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT            0
3137 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3138 {
3139     return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
3140 }
3141 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK         0x000000f0
3142 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT            4
3143 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3144 {
3145     return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
3146 }
3147 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK         0x00000f00
3148 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT            8
3149 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3150 {
3151     return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
3152 }
3153 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK         0x0000f000
3154 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT            12
3155 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3156 {
3157     return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
3158 }
3159 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK         0x000f0000
3160 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT            16
3161 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3162 {
3163     return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
3164 }
3165 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK         0x00f00000
3166 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT            20
3167 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3168 {
3169     return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
3170 }
3171 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK         0x0f000000
3172 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT            24
3173 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3174 {
3175     return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
3176 }
3177 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK         0xf0000000
3178 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT            28
3179 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3180 {
3181     return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
3182 }
3183
3184 #define REG_A6XX_RB_DITHER_CNTL                 0x0000880e
3185 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK      0x00000003
3186 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT     0
3187 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
3188 {
3189     return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
3190 }
3191 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK      0x0000000c
3192 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT     2
3193 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
3194 {
3195     return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
3196 }
3197 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK      0x00000030
3198 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT     4
3199 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
3200 {
3201     return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
3202 }
3203 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK      0x000000c0
3204 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT     6
3205 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
3206 {
3207     return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
3208 }
3209 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK      0x00000300
3210 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT     8
3211 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
3212 {
3213     return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
3214 }
3215 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK      0x00000c00
3216 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT     10
3217 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
3218 {
3219     return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
3220 }
3221 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK      0x00001000
3222 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT     12
3223 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
3224 {
3225     return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
3226 }
3227 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK      0x0000c000
3228 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT     14
3229 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
3230 {
3231     return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
3232 }
3233
3234 #define REG_A6XX_RB_SRGB_CNTL                   0x0000880f
3235 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0             0x00000001
3236 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1             0x00000002
3237 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2             0x00000004
3238 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3             0x00000008
3239 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4             0x00000010
3240 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5             0x00000020
3241 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6             0x00000040
3242 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7             0x00000080
3243
3244 #define REG_A6XX_RB_SAMPLE_CNTL                 0x00008810
3245 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE           0x00000001
3246
3247 #define REG_A6XX_RB_UNKNOWN_8811                0x00008811
3248
3249 #define REG_A6XX_RB_UNKNOWN_8818                0x00008818
3250
3251 #define REG_A6XX_RB_UNKNOWN_8819                0x00008819
3252
3253 #define REG_A6XX_RB_UNKNOWN_881A                0x0000881a
3254
3255 #define REG_A6XX_RB_UNKNOWN_881B                0x0000881b
3256
3257 #define REG_A6XX_RB_UNKNOWN_881C                0x0000881c
3258
3259 #define REG_A6XX_RB_UNKNOWN_881D                0x0000881d
3260
3261 #define REG_A6XX_RB_UNKNOWN_881E                0x0000881e
3262
3263 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3264
3265 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3266 #define A6XX_RB_MRT_CONTROL_BLEND               0x00000001
3267 #define A6XX_RB_MRT_CONTROL_BLEND2              0x00000002
3268 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE              0x00000004
3269 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK          0x00000078
3270 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT         3
3271 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3272 {
3273     return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3274 }
3275 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK      0x00000780
3276 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT     7
3277 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3278 {
3279     return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3280 }
3281
3282 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
3283 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK      0x0000001f
3284 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT     0
3285 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3286 {
3287     return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3288 }
3289 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK    0x000000e0
3290 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT   5
3291 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3292 {
3293     return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3294 }
3295 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK     0x00001f00
3296 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT    8
3297 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3298 {
3299     return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3300 }
3301 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK    0x001f0000
3302 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT   16
3303 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3304 {
3305     return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3306 }
3307 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK  0x00e00000
3308 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
3309 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3310 {
3311     return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3312 }
3313 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK   0x1f000000
3314 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT  24
3315 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3316 {
3317     return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3318 }
3319
3320 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
3321 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK         0x000000ff
3322 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT        0
3323 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
3324 {
3325     return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3326 }
3327 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK      0x00000300
3328 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT     8
3329 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
3330 {
3331     return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3332 }
3333 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK            0x00000400
3334 #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT           10
3335 static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
3336 {
3337     return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK;
3338 }
3339 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK           0x00006000
3340 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT          13
3341 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3342 {
3343     return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3344 }
3345
3346 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
3347 #define A6XX_RB_MRT_PITCH__MASK                 0x0000ffff
3348 #define A6XX_RB_MRT_PITCH__SHIFT                0
3349 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
3350 {
3351     return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
3352 }
3353
3354 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3355 #define A6XX_RB_MRT_ARRAY_PITCH__MASK               0x1fffffff
3356 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT              0
3357 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3358 {
3359     return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3360 }
3361
3362 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3363 #define A6XX_RB_MRT_BASE__MASK                  0xffffffff
3364 #define A6XX_RB_MRT_BASE__SHIFT                 0
3365 static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
3366 {
3367     return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
3368 }
3369
3370 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3371 #define A6XX_RB_MRT_BASE_GMEM__MASK             0xfffff000
3372 #define A6XX_RB_MRT_BASE_GMEM__SHIFT                12
3373 static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
3374 {
3375     return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK;
3376 }
3377
3378 #define REG_A6XX_RB_BLEND_RED_F32               0x00008860
3379 #define A6XX_RB_BLEND_RED_F32__MASK             0xffffffff
3380 #define A6XX_RB_BLEND_RED_F32__SHIFT                0
3381 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
3382 {
3383     return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
3384 }
3385
3386 #define REG_A6XX_RB_BLEND_GREEN_F32             0x00008861
3387 #define A6XX_RB_BLEND_GREEN_F32__MASK               0xffffffff
3388 #define A6XX_RB_BLEND_GREEN_F32__SHIFT              0
3389 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
3390 {
3391     return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
3392 }
3393
3394 #define REG_A6XX_RB_BLEND_BLUE_F32              0x00008862
3395 #define A6XX_RB_BLEND_BLUE_F32__MASK                0xffffffff
3396 #define A6XX_RB_BLEND_BLUE_F32__SHIFT               0
3397 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
3398 {
3399     return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
3400 }
3401
3402 #define REG_A6XX_RB_BLEND_ALPHA_F32             0x00008863
3403 #define A6XX_RB_BLEND_ALPHA_F32__MASK               0xffffffff
3404 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT              0
3405 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
3406 {
3407     return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
3408 }
3409
3410 #define REG_A6XX_RB_ALPHA_CONTROL               0x00008864
3411 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK           0x000000ff
3412 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT          0
3413 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3414 {
3415     return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3416 }
3417 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST            0x00000100
3418 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK     0x00000e00
3419 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT        9
3420 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3421 {
3422     return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3423 }
3424
3425 #define REG_A6XX_RB_BLEND_CNTL                  0x00008865
3426 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK           0x000000ff
3427 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT          0
3428 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3429 {
3430     return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3431 }
3432 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND            0x00000100
3433 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE         0x00000200
3434 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE            0x00000400
3435 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE             0x00000800
3436 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK            0xffff0000
3437 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT           16
3438 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3439 {
3440     return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3441 }
3442
3443 #define REG_A6XX_RB_DEPTH_PLANE_CNTL                0x00008870
3444 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK           0x00000003
3445 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT          0
3446 static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
3447 {
3448     return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
3449 }
3450
3451 #define REG_A6XX_RB_DEPTH_CNTL                  0x00008871
3452 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE            0x00000001
3453 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE           0x00000002
3454 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK              0x0000001c
3455 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT             2
3456 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3457 {
3458     return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3459 }
3460 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE           0x00000020
3461 #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE            0x00000040
3462 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE          0x00000080
3463
3464 #define REG_A6XX_RB_DEPTH_BUFFER_INFO               0x00008872
3465 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK        0x00000007
3466 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT       0
3467 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
3468 {
3469     return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3470 }
3471 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK            0x00000018
3472 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT           3
3473 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
3474 {
3475     return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
3476 }
3477
3478 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH              0x00008873
3479 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK            0x00003fff
3480 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT           0
3481 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3482 {
3483     return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
3484 }
3485
3486 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH            0x00008874
3487 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK          0x0fffffff
3488 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT         0
3489 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3490 {
3491     return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3492 }
3493
3494 #define REG_A6XX_RB_DEPTH_BUFFER_BASE               0x00008875
3495 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK             0xffffffff
3496 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT            0
3497 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
3498 {
3499     return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
3500 }
3501
3502 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM          0x00008877
3503 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK            0xfffff000
3504 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT           12
3505 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
3506 {
3507     return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK;
3508 }
3509
3510 #define REG_A6XX_RB_Z_BOUNDS_MIN                0x00008878
3511 #define A6XX_RB_Z_BOUNDS_MIN__MASK              0xffffffff
3512 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT             0
3513 static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
3514 {
3515     return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
3516 }
3517
3518 #define REG_A6XX_RB_Z_BOUNDS_MAX                0x00008879
3519 #define A6XX_RB_Z_BOUNDS_MAX__MASK              0xffffffff
3520 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT             0
3521 static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
3522 {
3523     return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
3524 }
3525
3526 #define REG_A6XX_RB_STENCIL_CONTROL             0x00008880
3527 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE          0x00000001
3528 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF       0x00000002
3529 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ            0x00000004
3530 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK          0x00000700
3531 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT         8
3532 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3533 {
3534     return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
3535 }
3536 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK          0x00003800
3537 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT         11
3538 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3539 {
3540     return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
3541 }
3542 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK         0x0001c000
3543 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT            14
3544 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3545 {
3546     return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3547 }
3548 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK         0x000e0000
3549 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT            17
3550 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3551 {
3552     return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3553 }
3554 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK           0x00700000
3555 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT          20
3556 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3557 {
3558     return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3559 }
3560 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK           0x03800000
3561 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT          23
3562 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3563 {
3564     return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3565 }
3566 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK          0x1c000000
3567 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT         26
3568 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3569 {
3570     return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3571 }
3572 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK          0xe0000000
3573 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT         29
3574 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3575 {
3576     return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3577 }
3578
3579 #define REG_A6XX_RB_STENCIL_INFO                0x00008881
3580 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL           0x00000001
3581 #define A6XX_RB_STENCIL_INFO_UNK1               0x00000002
3582
3583 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH            0x00008882
3584 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK          0x00000fff
3585 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT         0
3586 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
3587 {
3588     return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
3589 }
3590
3591 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH          0x00008883
3592 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK        0x00ffffff
3593 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT       0
3594 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3595 {
3596     return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3597 }
3598
3599 #define REG_A6XX_RB_STENCIL_BUFFER_BASE             0x00008884
3600 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK           0xffffffff
3601 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT          0
3602 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
3603 {
3604     return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
3605 }
3606
3607 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM            0x00008886
3608 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK          0xfffff000
3609 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT         12
3610 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
3611 {
3612     return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK;
3613 }
3614
3615 #define REG_A6XX_RB_STENCILREF                  0x00008887
3616 #define A6XX_RB_STENCILREF_REF__MASK                0x000000ff
3617 #define A6XX_RB_STENCILREF_REF__SHIFT               0
3618 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
3619 {
3620     return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
3621 }
3622 #define A6XX_RB_STENCILREF_BFREF__MASK              0x0000ff00
3623 #define A6XX_RB_STENCILREF_BFREF__SHIFT             8
3624 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
3625 {
3626     return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
3627 }
3628
3629 #define REG_A6XX_RB_STENCILMASK                 0x00008888
3630 #define A6XX_RB_STENCILMASK_MASK__MASK              0x000000ff
3631 #define A6XX_RB_STENCILMASK_MASK__SHIFT             0
3632 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
3633 {
3634     return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
3635 }
3636 #define A6XX_RB_STENCILMASK_BFMASK__MASK            0x0000ff00
3637 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT           8
3638 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
3639 {
3640     return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
3641 }
3642
3643 #define REG_A6XX_RB_STENCILWRMASK               0x00008889
3644 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK          0x000000ff
3645 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT         0
3646 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
3647 {
3648     return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
3649 }
3650 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK            0x0000ff00
3651 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT           8
3652 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
3653 {
3654     return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
3655 }
3656
3657 #define REG_A6XX_RB_WINDOW_OFFSET               0x00008890
3658 #define A6XX_RB_WINDOW_OFFSET_X__MASK               0x00003fff
3659 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT              0
3660 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
3661 {
3662     return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
3663 }
3664 #define A6XX_RB_WINDOW_OFFSET_Y__MASK               0x3fff0000
3665 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT              16
3666 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3667 {
3668     return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
3669 }
3670
3671 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL            0x00008891
3672 #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0           0x00000001
3673 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY           0x00000002
3674
3675 #define REG_A6XX_RB_LRZ_CNTL                    0x00008898
3676 #define A6XX_RB_LRZ_CNTL_ENABLE                 0x00000001
3677
3678 #define REG_A6XX_RB_Z_CLAMP_MIN                 0x000088c0
3679 #define A6XX_RB_Z_CLAMP_MIN__MASK               0xffffffff
3680 #define A6XX_RB_Z_CLAMP_MIN__SHIFT              0
3681 static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
3682 {
3683     return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
3684 }
3685
3686 #define REG_A6XX_RB_Z_CLAMP_MAX                 0x000088c1
3687 #define A6XX_RB_Z_CLAMP_MAX__MASK               0xffffffff
3688 #define A6XX_RB_Z_CLAMP_MAX__SHIFT              0
3689 static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
3690 {
3691     return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
3692 }
3693
3694 #define REG_A6XX_RB_UNKNOWN_88D0                0x000088d0
3695 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK             0x00001fff
3696 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT            0
3697 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
3698 {
3699     return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK;
3700 }
3701 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK            0x07ff0000
3702 #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT           16
3703 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
3704 {
3705     return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK;
3706 }
3707
3708 #define REG_A6XX_RB_BLIT_SCISSOR_TL             0x000088d1
3709 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK             0x00003fff
3710 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT            0
3711 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
3712 {
3713     return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
3714 }
3715 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK             0x3fff0000
3716 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT            16
3717 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
3718 {
3719     return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
3720 }
3721
3722 #define REG_A6XX_RB_BLIT_SCISSOR_BR             0x000088d2
3723 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK             0x00003fff
3724 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT            0
3725 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
3726 {
3727     return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
3728 }
3729 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK             0x3fff0000
3730 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT            16
3731 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
3732 {
3733     return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
3734 }
3735
3736 #define REG_A6XX_RB_BIN_CONTROL2                0x000088d3
3737 #define A6XX_RB_BIN_CONTROL2_BINW__MASK             0x0000003f
3738 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT            0
3739 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
3740 {
3741     return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
3742 }
3743 #define A6XX_RB_BIN_CONTROL2_BINH__MASK             0x00007f00
3744 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT            8
3745 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
3746 {
3747     return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
3748 }
3749
3750 #define REG_A6XX_RB_WINDOW_OFFSET2              0x000088d4
3751 #define A6XX_RB_WINDOW_OFFSET2_X__MASK              0x00003fff
3752 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT             0
3753 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
3754 {
3755     return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
3756 }
3757 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK              0x3fff0000
3758 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT             16
3759 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
3760 {
3761     return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
3762 }
3763
3764 #define REG_A6XX_RB_MSAA_CNTL                   0x000088d5
3765 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK             0x00000018
3766 #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT            3
3767 static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3768 {
3769     return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
3770 }
3771
3772 #define REG_A6XX_RB_BLIT_BASE_GMEM              0x000088d6
3773 #define A6XX_RB_BLIT_BASE_GMEM__MASK                0xfffff000
3774 #define A6XX_RB_BLIT_BASE_GMEM__SHIFT               12
3775 static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
3776 {
3777     return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK;
3778 }
3779
3780 #define REG_A6XX_RB_BLIT_DST_INFO               0x000088d7
3781 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK           0x00000003
3782 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT          0
3783 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3784 {
3785     return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
3786 }
3787 #define A6XX_RB_BLIT_DST_INFO_FLAGS             0x00000004
3788 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK         0x00000018
3789 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT            3
3790 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
3791 {
3792     return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
3793 }
3794 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK          0x00000060
3795 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT         5
3796 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3797 {
3798     return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
3799 }
3800 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK        0x00007f80
3801 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT       7
3802 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
3803 {
3804     return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
3805 }
3806 #define A6XX_RB_BLIT_DST_INFO_UNK15             0x00008000
3807
3808 #define REG_A6XX_RB_BLIT_DST                    0x000088d8
3809 #define A6XX_RB_BLIT_DST__MASK                  0xffffffff
3810 #define A6XX_RB_BLIT_DST__SHIFT                 0
3811 static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
3812 {
3813     return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
3814 }
3815
3816 #define REG_A6XX_RB_BLIT_DST_PITCH              0x000088da
3817 #define A6XX_RB_BLIT_DST_PITCH__MASK                0x0000ffff
3818 #define A6XX_RB_BLIT_DST_PITCH__SHIFT               0
3819 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
3820 {
3821     return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
3822 }
3823
3824 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH            0x000088db
3825 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK          0x1fffffff
3826 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT         0
3827 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3828 {
3829     return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3830 }
3831
3832 #define REG_A6XX_RB_BLIT_FLAG_DST               0x000088dc
3833 #define A6XX_RB_BLIT_FLAG_DST__MASK             0xffffffff
3834 #define A6XX_RB_BLIT_FLAG_DST__SHIFT                0
3835 static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
3836 {
3837     return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
3838 }
3839
3840 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH             0x000088de
3841 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK         0x000007ff
3842 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT        0
3843 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
3844 {
3845     return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
3846 }
3847 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK       0x0ffff800
3848 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT      11
3849 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
3850 {
3851     return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
3852 }
3853
3854 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0            0x000088df
3855
3856 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1            0x000088e0
3857
3858 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2            0x000088e1
3859
3860 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3            0x000088e2
3861
3862 #define REG_A6XX_RB_BLIT_INFO                   0x000088e3
3863 #define A6XX_RB_BLIT_INFO_UNK0                  0x00000001
3864 #define A6XX_RB_BLIT_INFO_GMEM                  0x00000002
3865 #define A6XX_RB_BLIT_INFO_SAMPLE_0              0x00000004
3866 #define A6XX_RB_BLIT_INFO_DEPTH                 0x00000008
3867 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK          0x000000f0
3868 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT         4
3869 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
3870 {
3871     return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
3872 }
3873 #define A6XX_RB_BLIT_INFO_UNK8__MASK                0x00000300
3874 #define A6XX_RB_BLIT_INFO_UNK8__SHIFT               8
3875 static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val)
3876 {
3877     return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK;
3878 }
3879 #define A6XX_RB_BLIT_INFO_UNK12__MASK               0x0000f000
3880 #define A6XX_RB_BLIT_INFO_UNK12__SHIFT              12
3881 static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val)
3882 {
3883     return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK;
3884 }
3885
3886 #define REG_A6XX_RB_UNKNOWN_88F0                0x000088f0
3887
3888 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE            0x000088f1
3889 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK          0xffffffff
3890 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT         0
3891 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
3892 {
3893     return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK;
3894 }
3895
3896 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH           0x000088f3
3897 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK       0x000007ff
3898 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT      0
3899 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3900 {
3901     return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
3902 }
3903 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK     0x00fff800
3904 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT    11
3905 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3906 {
3907     return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3908 }
3909
3910 #define REG_A6XX_RB_UNKNOWN_88F4                0x000088f4
3911
3912 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE          0x00008900
3913 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK            0xffffffff
3914 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT           0
3915 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
3916 {
3917     return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
3918 }
3919
3920 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH         0x00008902
3921 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK     0x0000007f
3922 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT        0
3923 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3924 {
3925     return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
3926 }
3927 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK      0x00000700
3928 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT     8
3929 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
3930 {
3931     return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK;
3932 }
3933 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK   0x0ffff800
3934 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT  11
3935 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3936 {
3937     return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3938 }
3939
3940 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3941
3942 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3943 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK          0xffffffff
3944 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT         0
3945 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
3946 {
3947     return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
3948 }
3949
3950 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
3951 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK       0x000007ff
3952 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT      0
3953 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3954 {
3955     return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
3956 }
3957 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK     0x1ffff800
3958 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT    11
3959 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3960 {
3961     return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3962 }
3963
3964 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR               0x00008927
3965 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK             0xffffffff
3966 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT            0
3967 static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
3968 {
3969     return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
3970 }
3971
3972 #define REG_A6XX_RB_UNKNOWN_8A00                0x00008a00
3973
3974 #define REG_A6XX_RB_UNKNOWN_8A10                0x00008a10
3975
3976 #define REG_A6XX_RB_UNKNOWN_8A20                0x00008a20
3977
3978 #define REG_A6XX_RB_UNKNOWN_8A30                0x00008a30
3979
3980 #define REG_A6XX_RB_2D_BLIT_CNTL                0x00008c00
3981 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK           0x00000007
3982 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT          0
3983 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
3984 {
3985     return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
3986 }
3987 #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN            0x00000008
3988 #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK             0x00000070
3989 #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT            4
3990 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val)
3991 {
3992     return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK;
3993 }
3994 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR            0x00000080
3995 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK         0x0000ff00
3996 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT        8
3997 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
3998 {
3999     return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
4000 }
4001 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR                0x00010000
4002 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK            0x00060000
4003 #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT           17
4004 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
4005 {
4006     return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK;
4007 }
4008 #define A6XX_RB_2D_BLIT_CNTL_D24S8              0x00080000
4009 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK             0x00f00000
4010 #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT            20
4011 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
4012 {
4013     return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
4014 }
4015 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK             0x1f000000
4016 #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT            24
4017 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
4018 {
4019     return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
4020 }
4021 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK          0x20000000
4022 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT         29
4023 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
4024 {
4025     return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK;
4026 }
4027
4028 #define REG_A6XX_RB_2D_UNKNOWN_8C01             0x00008c01
4029
4030 #define REG_A6XX_RB_2D_DST_INFO                 0x00008c17
4031 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK          0x000000ff
4032 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT         0
4033 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
4034 {
4035     return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
4036 }
4037 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK         0x00000300
4038 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT            8
4039 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
4040 {
4041     return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
4042 }
4043 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK            0x00000c00
4044 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT           10
4045 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4046 {
4047     return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
4048 }
4049 #define A6XX_RB_2D_DST_INFO_FLAGS               0x00001000
4050 #define A6XX_RB_2D_DST_INFO_SRGB                0x00002000
4051 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK           0x0000c000
4052 #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT          14
4053 static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
4054 {
4055     return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
4056 }
4057 #define A6XX_RB_2D_DST_INFO_FILTER              0x00010000
4058 #define A6XX_RB_2D_DST_INFO_UNK17               0x00020000
4059 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE         0x00040000
4060 #define A6XX_RB_2D_DST_INFO_UNK19               0x00080000
4061 #define A6XX_RB_2D_DST_INFO_UNK20               0x00100000
4062 #define A6XX_RB_2D_DST_INFO_UNK21               0x00200000
4063 #define A6XX_RB_2D_DST_INFO_UNK22               0x00400000
4064 #define A6XX_RB_2D_DST_INFO_UNK23__MASK             0x07800000
4065 #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT            23
4066 static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
4067 {
4068     return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
4069 }
4070 #define A6XX_RB_2D_DST_INFO_UNK28               0x10000000
4071
4072 #define REG_A6XX_RB_2D_DST                  0x00008c18
4073 #define A6XX_RB_2D_DST__MASK                    0xffffffff
4074 #define A6XX_RB_2D_DST__SHIFT                   0
4075 static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
4076 {
4077     return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
4078 }
4079
4080 #define REG_A6XX_RB_2D_DST_PITCH                0x00008c1a
4081 #define A6XX_RB_2D_DST_PITCH__MASK              0x0000ffff
4082 #define A6XX_RB_2D_DST_PITCH__SHIFT             0
4083 static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
4084 {
4085     return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
4086 }
4087
4088 #define REG_A6XX_RB_2D_DST_PLANE1               0x00008c1b
4089 #define A6XX_RB_2D_DST_PLANE1__MASK             0xffffffff
4090 #define A6XX_RB_2D_DST_PLANE1__SHIFT                0
4091 static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
4092 {
4093     return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK;
4094 }
4095
4096 #define REG_A6XX_RB_2D_DST_PLANE_PITCH              0x00008c1d
4097 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK            0x0000ffff
4098 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT           0
4099 static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
4100 {
4101     return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
4102 }
4103
4104 #define REG_A6XX_RB_2D_DST_PLANE2               0x00008c1e
4105 #define A6XX_RB_2D_DST_PLANE2__MASK             0xffffffff
4106 #define A6XX_RB_2D_DST_PLANE2__SHIFT                0
4107 static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
4108 {
4109     return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
4110 }
4111
4112 #define REG_A6XX_RB_2D_DST_FLAGS                0x00008c20
4113 #define A6XX_RB_2D_DST_FLAGS__MASK              0xffffffff
4114 #define A6XX_RB_2D_DST_FLAGS__SHIFT             0
4115 static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
4116 {
4117     return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
4118 }
4119
4120 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH              0x00008c22
4121 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK            0x000000ff
4122 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT           0
4123 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
4124 {
4125     return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
4126 }
4127
4128 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE              0x00008c23
4129 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK            0xffffffff
4130 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT           0
4131 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
4132 {
4133     return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK;
4134 }
4135
4136 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH            0x00008c25
4137 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK          0x000000ff
4138 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT         0
4139 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
4140 {
4141     return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
4142 }
4143
4144 #define REG_A6XX_RB_2D_SRC_SOLID_C0             0x00008c2c
4145
4146 #define REG_A6XX_RB_2D_SRC_SOLID_C1             0x00008c2d
4147
4148 #define REG_A6XX_RB_2D_SRC_SOLID_C2             0x00008c2e
4149
4150 #define REG_A6XX_RB_2D_SRC_SOLID_C3             0x00008c2f
4151
4152 #define REG_A6XX_RB_UNKNOWN_8E01                0x00008e01
4153
4154 #define REG_A6XX_RB_UNKNOWN_8E04                0x00008e04
4155
4156 #define REG_A6XX_RB_ADDR_MODE_CNTL              0x00008e05
4157
4158 #define REG_A6XX_RB_CCU_CNTL                    0x00008e07
4159 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK         0xff800000
4160 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT            23
4161 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)
4162 {
4163     return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK;
4164 }
4165 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK         0x001ff000
4166 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT            12
4167 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)
4168 {
4169     return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK;
4170 }
4171 #define A6XX_RB_CCU_CNTL_GMEM                   0x00400000
4172 #define A6XX_RB_CCU_CNTL_UNK2                   0x00000004
4173
4174 #define REG_A6XX_RB_NC_MODE_CNTL                0x00008e08
4175 #define A6XX_RB_NC_MODE_CNTL_MODE               0x00000001
4176 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK            0x00000006
4177 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT           1
4178 static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
4179 {
4180     return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK;
4181 }
4182 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH          0x00000008
4183 #define A6XX_RB_NC_MODE_CNTL_AMSBC              0x00000010
4184 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK            0x00000400
4185 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT           10
4186 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
4187 {
4188     return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK;
4189 }
4190 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR          0x00000800
4191 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK            0x00003000
4192 #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT           12
4193 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
4194 {
4195     return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4196 }
4197
4198 static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
4199
4200 static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
4201
4202 #define REG_A6XX_RB_UNKNOWN_8E28                0x00008e28
4203
4204 static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
4205
4206 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST          0x00008e3b
4207
4208 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD            0x00008e3d
4209
4210 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE        0x00008e50
4211
4212 #define REG_A6XX_RB_UNKNOWN_8E51                0x00008e51
4213 #define A6XX_RB_UNKNOWN_8E51__MASK              0xffffffff
4214 #define A6XX_RB_UNKNOWN_8E51__SHIFT             0
4215 static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
4216 {
4217     return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
4218 }
4219
4220 #define REG_A6XX_VPC_GS_PARAM                   0x00009100
4221 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK           0x000000ff
4222 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT          0
4223 static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val)
4224 {
4225     return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK;
4226 }
4227
4228 #define REG_A6XX_VPC_VS_CLIP_CNTL               0x00009101
4229 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK           0x000000ff
4230 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT          0
4231 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4232 {
4233     return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK;
4234 }
4235 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK        0x0000ff00
4236 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT       8
4237 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4238 {
4239     return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4240 }
4241 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK        0x00ff0000
4242 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT       16
4243 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4244 {
4245     return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4246 }
4247
4248 #define REG_A6XX_VPC_GS_CLIP_CNTL               0x00009102
4249 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK           0x000000ff
4250 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT          0
4251 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4252 {
4253     return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK;
4254 }
4255 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK        0x0000ff00
4256 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT       8
4257 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4258 {
4259     return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4260 }
4261 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK        0x00ff0000
4262 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT       16
4263 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4264 {
4265     return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4266 }
4267
4268 #define REG_A6XX_VPC_DS_CLIP_CNTL               0x00009103
4269 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK           0x000000ff
4270 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT          0
4271 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4272 {
4273     return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK;
4274 }
4275 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK        0x0000ff00
4276 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT       8
4277 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4278 {
4279     return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4280 }
4281 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK        0x00ff0000
4282 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT       16
4283 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4284 {
4285     return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4286 }
4287
4288 #define REG_A6XX_VPC_VS_LAYER_CNTL              0x00009104
4289 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK           0x000000ff
4290 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT          0
4291 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
4292 {
4293     return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK;
4294 }
4295 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK            0x0000ff00
4296 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT           8
4297 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
4298 {
4299     return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
4300 }
4301
4302 #define REG_A6XX_VPC_GS_LAYER_CNTL              0x00009105
4303 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK           0x000000ff
4304 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT          0
4305 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
4306 {
4307     return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK;
4308 }
4309 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK            0x0000ff00
4310 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT           8
4311 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
4312 {
4313     return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
4314 }
4315
4316 #define REG_A6XX_VPC_DS_LAYER_CNTL              0x00009106
4317 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK           0x000000ff
4318 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT          0
4319 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
4320 {
4321     return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK;
4322 }
4323 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK            0x0000ff00
4324 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT           8
4325 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
4326 {
4327     return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
4328 }
4329
4330 #define REG_A6XX_VPC_UNKNOWN_9107               0x00009107
4331 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD            0x00000001
4332 #define A6XX_VPC_UNKNOWN_9107_UNK2              0x00000004
4333
4334 #define REG_A6XX_VPC_POLYGON_MODE               0x00009108
4335 #define A6XX_VPC_POLYGON_MODE_MODE__MASK            0x00000003
4336 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT           0
4337 static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4338 {
4339     return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
4340 }
4341
4342 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4343
4344 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4345
4346 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4347
4348 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4349
4350 #define REG_A6XX_VPC_UNKNOWN_9210               0x00009210
4351
4352 #define REG_A6XX_VPC_UNKNOWN_9211               0x00009211
4353
4354 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4355
4356 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4357
4358 #define REG_A6XX_VPC_SO_CNTL                    0x00009216
4359 #define A6XX_VPC_SO_CNTL_ADDR__MASK             0x000000ff
4360 #define A6XX_VPC_SO_CNTL_ADDR__SHIFT                0
4361 static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
4362 {
4363     return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
4364 }
4365 #define A6XX_VPC_SO_CNTL_RESET                  0x00010000
4366
4367 #define REG_A6XX_VPC_SO_PROG                    0x00009217
4368 #define A6XX_VPC_SO_PROG_A_BUF__MASK                0x00000003
4369 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT               0
4370 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
4371 {
4372     return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
4373 }
4374 #define A6XX_VPC_SO_PROG_A_OFF__MASK                0x000007fc
4375 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT               2
4376 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
4377 {
4378     return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
4379 }
4380 #define A6XX_VPC_SO_PROG_A_EN                   0x00000800
4381 #define A6XX_VPC_SO_PROG_B_BUF__MASK                0x00003000
4382 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT               12
4383 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
4384 {
4385     return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
4386 }
4387 #define A6XX_VPC_SO_PROG_B_OFF__MASK                0x007fc000
4388 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT               14
4389 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
4390 {
4391     return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
4392 }
4393 #define A6XX_VPC_SO_PROG_B_EN                   0x00800000
4394
4395 #define REG_A6XX_VPC_SO_STREAM_COUNTS               0x00009218
4396 #define A6XX_VPC_SO_STREAM_COUNTS__MASK             0xffffffff
4397 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT            0
4398 static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
4399 {
4400     return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
4401 }
4402
4403 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4404
4405 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4406 #define A6XX_VPC_SO_BUFFER_BASE__MASK               0xffffffff
4407 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT              0
4408 static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
4409 {
4410     return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4411 }
4412
4413 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4414 #define A6XX_VPC_SO_BUFFER_SIZE__MASK               0xfffffffc
4415 #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT              2
4416 static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
4417 {
4418     return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
4419 }
4420
4421 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
4422
4423 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
4424 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK             0xfffffffc
4425 #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT            2
4426 static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
4427 {
4428     return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK;
4429 }
4430
4431 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
4432 #define A6XX_VPC_SO_FLUSH_BASE__MASK                0xffffffff
4433 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT               0
4434 static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
4435 {
4436     return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
4437 }
4438
4439 #define REG_A6XX_VPC_POINT_COORD_INVERT             0x00009236
4440 #define A6XX_VPC_POINT_COORD_INVERT_INVERT          0x00000001
4441
4442 #define REG_A6XX_VPC_UNKNOWN_9300               0x00009300
4443
4444 #define REG_A6XX_VPC_VS_PACK                    0x00009301
4445 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK            0x000000ff
4446 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT           0
4447 static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
4448 {
4449     return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK;
4450 }
4451 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK          0x0000ff00
4452 #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT         8
4453 static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
4454 {
4455     return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
4456 }
4457 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK             0x00ff0000
4458 #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT            16
4459 static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
4460 {
4461     return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
4462 }
4463 #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK             0x0f000000
4464 #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT            24
4465 static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
4466 {
4467     return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
4468 }
4469
4470 #define REG_A6XX_VPC_GS_PACK                    0x00009302
4471 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK            0x000000ff
4472 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT           0
4473 static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
4474 {
4475     return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;
4476 }
4477 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK          0x0000ff00
4478 #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT         8
4479 static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
4480 {
4481     return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
4482 }
4483 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK             0x00ff0000
4484 #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT            16
4485 static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
4486 {
4487     return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
4488 }
4489 #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK             0x0f000000
4490 #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT            24
4491 static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
4492 {
4493     return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
4494 }
4495
4496 #define REG_A6XX_VPC_DS_PACK                    0x00009303
4497 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK            0x000000ff
4498 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT           0
4499 static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
4500 {
4501     return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;
4502 }
4503 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK          0x0000ff00
4504 #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT         8
4505 static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
4506 {
4507     return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
4508 }
4509 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK             0x00ff0000
4510 #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT            16
4511 static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
4512 {
4513     return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
4514 }
4515 #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK             0x0f000000
4516 #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT            24
4517 static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
4518 {
4519     return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
4520 }
4521
4522 #define REG_A6XX_VPC_CNTL_0                 0x00009304
4523 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK          0x000000ff
4524 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT         0
4525 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
4526 {
4527     return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
4528 }
4529 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK             0x0000ff00
4530 #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT            8
4531 static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
4532 {
4533     return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
4534 }
4535 #define A6XX_VPC_CNTL_0_VARYING                 0x00010000
4536 #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK             0xff000000
4537 #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT            24
4538 static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
4539 {
4540     return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
4541 }
4542
4543 #define REG_A6XX_VPC_SO_STREAM_CNTL             0x00009305
4544 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK       0x00000007
4545 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT      0
4546 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
4547 {
4548     return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
4549 }
4550 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK       0x00000038
4551 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT      3
4552 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
4553 {
4554     return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
4555 }
4556 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK       0x000001c0
4557 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT      6
4558 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
4559 {
4560     return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
4561 }
4562 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK       0x00000e00
4563 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT      9
4564 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
4565 {
4566     return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
4567 }
4568 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK     0x00078000
4569 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT        15
4570 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
4571 {
4572     return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
4573 }
4574
4575 #define REG_A6XX_VPC_SO_DISABLE                 0x00009306
4576 #define A6XX_VPC_SO_DISABLE_DISABLE             0x00000001
4577
4578 #define REG_A6XX_VPC_UNKNOWN_9600               0x00009600
4579
4580 #define REG_A6XX_VPC_ADDR_MODE_CNTL             0x00009601
4581
4582 #define REG_A6XX_VPC_UNKNOWN_9602               0x00009602
4583
4584 #define REG_A6XX_VPC_UNKNOWN_9603               0x00009603
4585
4586 static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
4587
4588 #define REG_A6XX_PC_TESS_NUM_VERTEX             0x00009800
4589
4590 #define REG_A6XX_PC_HS_INPUT_SIZE               0x00009801
4591 #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK            0x000007ff
4592 #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT           0
4593 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
4594 {
4595     return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
4596 }
4597 #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK           0x00002000
4598 #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT          13
4599 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
4600 {
4601     return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
4602 }
4603
4604 #define REG_A6XX_PC_TESS_CNTL                   0x00009802
4605 #define A6XX_PC_TESS_CNTL_SPACING__MASK             0x00000003
4606 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT            0
4607 static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
4608 {
4609     return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
4610 }
4611 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK              0x0000000c
4612 #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT             2
4613 static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
4614 {
4615     return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
4616 }
4617
4618 #define REG_A6XX_PC_RESTART_INDEX               0x00009803
4619
4620 #define REG_A6XX_PC_MODE_CNTL                   0x00009804
4621
4622 #define REG_A6XX_PC_POWER_CNTL                  0x00009805
4623
4624 #define REG_A6XX_PC_PRIMID_PASSTHRU             0x00009806
4625
4626 #define REG_A6XX_PC_SO_STREAM_CNTL              0x00009808
4627 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE            0x00008000
4628
4629 #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL       0x0000980a
4630 #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
4631
4632 #define REG_A6XX_PC_DRAW_CMD                    0x00009840
4633 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK             0x000000ff
4634 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT            0
4635 static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
4636 {
4637     return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
4638 }
4639
4640 #define REG_A6XX_PC_DISPATCH_CMD                0x00009841
4641 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK         0x000000ff
4642 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT            0
4643 static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
4644 {
4645     return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
4646 }
4647
4648 #define REG_A6XX_PC_EVENT_CMD                   0x00009842
4649 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK            0x00ff0000
4650 #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT           16
4651 static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
4652 {
4653     return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
4654 }
4655 #define A6XX_PC_EVENT_CMD_EVENT__MASK               0x0000007f
4656 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT              0
4657 static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
4658 {
4659     return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
4660 }
4661
4662 #define REG_A6XX_PC_MARKER                  0x00009880
4663
4664 #define REG_A6XX_PC_POLYGON_MODE                0x00009981
4665 #define A6XX_PC_POLYGON_MODE_MODE__MASK             0x00000003
4666 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT            0
4667 static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4668 {
4669     return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
4670 }
4671
4672 #define REG_A6XX_PC_RASTER_CNTL                 0x00009980
4673 #define A6XX_PC_RASTER_CNTL_STREAM__MASK            0x00000003
4674 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT           0
4675 static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
4676 {
4677     return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
4678 }
4679 #define A6XX_PC_RASTER_CNTL_DISCARD             0x00000004
4680
4681 #define REG_A6XX_PC_PRIMITIVE_CNTL_0                0x00009b00
4682 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART      0x00000001
4683 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST     0x00000002
4684 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN  0x00000004
4685 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3               0x00000008
4686
4687 #define REG_A6XX_PC_VS_OUT_CNTL                 0x00009b01
4688 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK         0x000000ff
4689 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT        0
4690 static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4691 {
4692     return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4693 }
4694 #define A6XX_PC_VS_OUT_CNTL_PSIZE               0x00000100
4695 #define A6XX_PC_VS_OUT_CNTL_LAYER               0x00000200
4696 #define A6XX_PC_VS_OUT_CNTL_VIEW                0x00000400
4697 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID            0x00000800
4698 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK         0x00ff0000
4699 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT            16
4700 static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
4701 {
4702     return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
4703 }
4704
4705 #define REG_A6XX_PC_GS_OUT_CNTL                 0x00009b02
4706 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK         0x000000ff
4707 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT        0
4708 static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4709 {
4710     return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4711 }
4712 #define A6XX_PC_GS_OUT_CNTL_PSIZE               0x00000100
4713 #define A6XX_PC_GS_OUT_CNTL_LAYER               0x00000200
4714 #define A6XX_PC_GS_OUT_CNTL_VIEW                0x00000400
4715 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID            0x00000800
4716 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK         0x00ff0000
4717 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT            16
4718 static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
4719 {
4720     return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
4721 }
4722
4723 #define REG_A6XX_PC_HS_OUT_CNTL                 0x00009b03
4724 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK         0x000000ff
4725 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT        0
4726 static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4727 {
4728     return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4729 }
4730 #define A6XX_PC_HS_OUT_CNTL_PSIZE               0x00000100
4731 #define A6XX_PC_HS_OUT_CNTL_LAYER               0x00000200
4732 #define A6XX_PC_HS_OUT_CNTL_VIEW                0x00000400
4733 #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID            0x00000800
4734 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK         0x00ff0000
4735 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT            16
4736 static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val)
4737 {
4738     return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK;
4739 }
4740
4741 #define REG_A6XX_PC_DS_OUT_CNTL                 0x00009b04
4742 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK         0x000000ff
4743 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT        0
4744 static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4745 {
4746     return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4747 }
4748 #define A6XX_PC_DS_OUT_CNTL_PSIZE               0x00000100
4749 #define A6XX_PC_DS_OUT_CNTL_LAYER               0x00000200
4750 #define A6XX_PC_DS_OUT_CNTL_VIEW                0x00000400
4751 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID            0x00000800
4752 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK         0x00ff0000
4753 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT            16
4754 static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
4755 {
4756     return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
4757 }
4758
4759 #define REG_A6XX_PC_PRIMITIVE_CNTL_5                0x00009b05
4760 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK      0x000000ff
4761 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT     0
4762 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
4763 {
4764     return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
4765 }
4766 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK       0x00007c00
4767 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT      10
4768 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
4769 {
4770     return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
4771 }
4772 #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN           0x00008000
4773 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK        0x00030000
4774 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT       16
4775 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
4776 {
4777     return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
4778 }
4779 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK            0x00040000
4780 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT           18
4781 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
4782 {
4783     return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK;
4784 }
4785
4786 #define REG_A6XX_PC_PRIMITIVE_CNTL_6                0x00009b06
4787 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK        0x000007ff
4788 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT       0
4789 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
4790 {
4791     return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
4792 }
4793
4794 #define REG_A6XX_PC_MULTIVIEW_CNTL              0x00009b07
4795 #define A6XX_PC_MULTIVIEW_CNTL_ENABLE               0x00000001
4796 #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS          0x00000002
4797 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK          0x0000007c
4798 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT         2
4799 static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
4800 {
4801     return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
4802 }
4803
4804 #define REG_A6XX_PC_MULTIVIEW_MASK              0x00009b08
4805
4806 #define REG_A6XX_PC_2D_EVENT_CMD                0x00009c00
4807 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK            0x0000007f
4808 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT           0
4809 static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
4810 {
4811     return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
4812 }
4813 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK         0x0000ff00
4814 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT            8
4815 static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
4816 {
4817     return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
4818 }
4819
4820 #define REG_A6XX_PC_DBG_ECO_CNTL                0x00009e00
4821
4822 #define REG_A6XX_PC_ADDR_MODE_CNTL              0x00009e01
4823
4824 #define REG_A6XX_PC_DRAW_INDX_BASE              0x00009e04
4825
4826 #define REG_A6XX_PC_DRAW_FIRST_INDX             0x00009e06
4827
4828 #define REG_A6XX_PC_DRAW_MAX_INDICES                0x00009e07
4829
4830 #define REG_A6XX_PC_TESSFACTOR_ADDR             0x00009e08
4831 #define A6XX_PC_TESSFACTOR_ADDR__MASK               0xffffffff
4832 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT              0
4833 static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
4834 {
4835     return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
4836 }
4837
4838 #define REG_A6XX_PC_DRAW_INITIATOR              0x00009e0b
4839 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK          0x0000003f
4840 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT         0
4841 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
4842 {
4843     return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
4844 }
4845 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK      0x000000c0
4846 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT     6
4847 static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
4848 {
4849     return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
4850 }
4851 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK           0x00000300
4852 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT          8
4853 static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
4854 {
4855     return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
4856 }
4857 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK         0x00000c00
4858 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT        10
4859 static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
4860 {
4861     return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
4862 }
4863 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK         0x00003000
4864 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT        12
4865 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
4866 {
4867     return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
4868 }
4869 #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE            0x00010000
4870 #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE          0x00020000
4871
4872 #define REG_A6XX_PC_DRAW_NUM_INSTANCES              0x00009e0c
4873
4874 #define REG_A6XX_PC_DRAW_NUM_INDICES                0x00009e0d
4875
4876 #define REG_A6XX_PC_VSTREAM_CONTROL             0x00009e11
4877 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK          0x0000ffff
4878 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT         0
4879 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
4880 {
4881     return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
4882 }
4883 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK          0x003f0000
4884 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT         16
4885 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
4886 {
4887     return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
4888 }
4889 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK         0x07c00000
4890 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT            22
4891 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
4892 {
4893     return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
4894 }
4895
4896 #define REG_A6XX_PC_BIN_PRIM_STRM               0x00009e12
4897 #define A6XX_PC_BIN_PRIM_STRM__MASK             0xffffffff
4898 #define A6XX_PC_BIN_PRIM_STRM__SHIFT                0
4899 static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
4900 {
4901     return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK;
4902 }
4903
4904 #define REG_A6XX_PC_BIN_DRAW_STRM               0x00009e14
4905 #define A6XX_PC_BIN_DRAW_STRM__MASK             0xffffffff
4906 #define A6XX_PC_BIN_DRAW_STRM__SHIFT                0
4907 static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
4908 {
4909     return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
4910 }
4911
4912 #define REG_A6XX_PC_VISIBILITY_OVERRIDE             0x00009e1c
4913 #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE            0x00000001
4914
4915 static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
4916
4917 #define REG_A6XX_PC_UNKNOWN_9E72                0x00009e72
4918
4919 #define REG_A6XX_VFD_CONTROL_0                  0x0000a000
4920 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK          0x0000003f
4921 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT         0
4922 static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
4923 {
4924     return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
4925 }
4926 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK         0x00003f00
4927 #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT            8
4928 static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
4929 {
4930     return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
4931 }
4932
4933 #define REG_A6XX_VFD_CONTROL_1                  0x0000a001
4934 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK          0x000000ff
4935 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT         0
4936 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
4937 {
4938     return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
4939 }
4940 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK         0x0000ff00
4941 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT            8
4942 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
4943 {
4944     return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
4945 }
4946 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK           0x00ff0000
4947 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT          16
4948 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4949 {
4950     return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4951 }
4952 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK           0xff000000
4953 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT          24
4954 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
4955 {
4956     return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
4957 }
4958
4959 #define REG_A6XX_VFD_CONTROL_2                  0x0000a002
4960 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK     0x000000ff
4961 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT        0
4962 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val)
4963 {
4964     return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK;
4965 }
4966 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK     0x0000ff00
4967 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT        8
4968 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
4969 {
4970     return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
4971 }
4972
4973 #define REG_A6XX_VFD_CONTROL_3                  0x0000a003
4974 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK         0x000000ff
4975 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT        0
4976 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val)
4977 {
4978     return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK;
4979 }
4980 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK     0x0000ff00
4981 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT        8
4982 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val)
4983 {
4984     return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK;
4985 }
4986 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK            0x00ff0000
4987 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT           16
4988 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4989 {
4990     return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4991 }
4992 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK            0xff000000
4993 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT           24
4994 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4995 {
4996     return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4997 }
4998
4999 #define REG_A6XX_VFD_CONTROL_4                  0x0000a004
5000 #define A6XX_VFD_CONTROL_4_UNK0__MASK               0x000000ff
5001 #define A6XX_VFD_CONTROL_4_UNK0__SHIFT              0
5002 static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
5003 {
5004     return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
5005 }
5006
5007 #define REG_A6XX_VFD_CONTROL_5                  0x0000a005
5008 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK         0x000000ff
5009 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT        0
5010 static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
5011 {
5012     return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
5013 }
5014 #define A6XX_VFD_CONTROL_5_UNK8__MASK               0x0000ff00
5015 #define A6XX_VFD_CONTROL_5_UNK8__SHIFT              8
5016 static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
5017 {
5018     return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
5019 }
5020
5021 #define REG_A6XX_VFD_CONTROL_6                  0x0000a006
5022 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU          0x00000001
5023
5024 #define REG_A6XX_VFD_MODE_CNTL                  0x0000a007
5025 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK            0x00000007
5026 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT           0
5027 static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val)
5028 {
5029     return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK;
5030 }
5031
5032 #define REG_A6XX_VFD_MULTIVIEW_CNTL             0x0000a008
5033 #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE              0x00000001
5034 #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS         0x00000002
5035 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK         0x0000007c
5036 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT            2
5037 static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
5038 {
5039     return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
5040 }
5041
5042 #define REG_A6XX_VFD_ADD_OFFSET                 0x0000a009
5043 #define A6XX_VFD_ADD_OFFSET_VERTEX              0x00000001
5044 #define A6XX_VFD_ADD_OFFSET_INSTANCE                0x00000002
5045
5046 #define REG_A6XX_VFD_INDEX_OFFSET               0x0000a00e
5047
5048 #define REG_A6XX_VFD_INSTANCE_START_OFFSET          0x0000a00f
5049
5050 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5051
5052 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5053 #define A6XX_VFD_FETCH_BASE__MASK               0xffffffff
5054 #define A6XX_VFD_FETCH_BASE__SHIFT              0
5055 static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
5056 {
5057     return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
5058 }
5059
5060 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
5061
5062 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
5063
5064 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5065
5066 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5067 #define A6XX_VFD_DECODE_INSTR_IDX__MASK             0x0000001f
5068 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT            0
5069 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
5070 {
5071     return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
5072 }
5073 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK          0x0001ffe0
5074 #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT         5
5075 static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
5076 {
5077     return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
5078 }
5079 #define A6XX_VFD_DECODE_INSTR_INSTANCED             0x00020000
5080 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK          0x0ff00000
5081 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT         20
5082 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
5083 {
5084     return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
5085 }
5086 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK            0x30000000
5087 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT           28
5088 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
5089 {
5090     return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
5091 }
5092 #define A6XX_VFD_DECODE_INSTR_UNK30             0x40000000
5093 #define A6XX_VFD_DECODE_INSTR_FLOAT             0x80000000
5094
5095 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
5096
5097 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
5098
5099 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
5100 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK        0x0000000f
5101 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT       0
5102 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
5103 {
5104     return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
5105 }
5106 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK            0x00000ff0
5107 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT           4
5108 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
5109 {
5110     return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
5111 }
5112
5113 #define REG_A6XX_VFD_POWER_CNTL                 0x0000a0f8
5114
5115 #define REG_A6XX_VFD_ADDR_MODE_CNTL             0x0000a601
5116
5117 static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
5118
5119 #define REG_A6XX_SP_VS_CTRL_REG0                0x0000a800
5120 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS             0x00100000
5121 #define A6XX_SP_VS_CTRL_REG0_UNK21              0x00200000
5122 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK           0x00000001
5123 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT          0
5124 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5125 {
5126     return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
5127 }
5128 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x0000007e
5129 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        1
5130 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5131 {
5132     return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5133 }
5134 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x00001f80
5135 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        7
5136 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5137 {
5138     return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5139 }
5140 #define A6XX_SP_VS_CTRL_REG0_UNK13              0x00002000
5141 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK          0x000fc000
5142 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT         14
5143 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5144 {
5145     return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
5146 }
5147
5148 #define REG_A6XX_SP_VS_BRANCH_COND              0x0000a801
5149
5150 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL               0x0000a802
5151 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK         0x0000003f
5152 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT            0
5153 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
5154 {
5155     return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
5156 }
5157 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK     0x00003fc0
5158 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT        6
5159 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5160 {
5161     return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5162 }
5163
5164 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5165
5166 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5167 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK            0x000000ff
5168 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT           0
5169 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
5170 {
5171     return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
5172 }
5173 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK         0x00000f00
5174 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT            8
5175 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
5176 {
5177     return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
5178 }
5179 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK            0x00ff0000
5180 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT           16
5181 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
5182 {
5183     return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
5184 }
5185 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK         0x0f000000
5186 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT            24
5187 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
5188 {
5189     return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
5190 }
5191
5192 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
5193
5194 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
5195 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK            0x000000ff
5196 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT           0
5197 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
5198 {
5199     return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
5200 }
5201 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK            0x0000ff00
5202 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT           8
5203 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
5204 {
5205     return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
5206 }
5207 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK            0x00ff0000
5208 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT           16
5209 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
5210 {
5211     return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
5212 }
5213 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK            0xff000000
5214 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT           24
5215 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
5216 {
5217     return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5218 }
5219
5220 #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET            0x0000a81b
5221
5222 #define REG_A6XX_SP_VS_OBJ_START                0x0000a81c
5223 #define A6XX_SP_VS_OBJ_START__MASK              0xffffffff
5224 #define A6XX_SP_VS_OBJ_START__SHIFT             0
5225 static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
5226 {
5227     return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
5228 }
5229
5230 #define REG_A6XX_SP_VS_PVT_MEM_PARAM                0x0000a81e
5231 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK       0x000000ff
5232 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT      0
5233 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5234 {
5235     return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5236 }
5237 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5238 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT    24
5239 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5240 {
5241     return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5242 }
5243
5244 #define REG_A6XX_SP_VS_PVT_MEM_ADDR             0x0000a81f
5245 #define A6XX_SP_VS_PVT_MEM_ADDR__MASK               0xffffffff
5246 #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT              0
5247 static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
5248 {
5249     return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
5250 }
5251
5252 #define REG_A6XX_SP_VS_PVT_MEM_SIZE             0x0000a821
5253 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK       0x0003ffff
5254 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT      0
5255 static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5256 {
5257     return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5258 }
5259 #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT        0x80000000
5260
5261 #define REG_A6XX_SP_VS_TEX_COUNT                0x0000a822
5262
5263 #define REG_A6XX_SP_VS_CONFIG                   0x0000a823
5264 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX              0x00000001
5265 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP             0x00000002
5266 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO              0x00000004
5267 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO              0x00000008
5268 #define A6XX_SP_VS_CONFIG_ENABLED               0x00000100
5269 #define A6XX_SP_VS_CONFIG_NTEX__MASK                0x0001fe00
5270 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT               9
5271 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
5272 {
5273     return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
5274 }
5275 #define A6XX_SP_VS_CONFIG_NSAMP__MASK               0x003e0000
5276 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT              17
5277 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
5278 {
5279     return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5280 }
5281 #define A6XX_SP_VS_CONFIG_NIBO__MASK                0x1fc00000
5282 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT               22
5283 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5284 {
5285     return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
5286 }
5287
5288 #define REG_A6XX_SP_VS_INSTRLEN                 0x0000a824
5289
5290 #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET          0x0000a825
5291 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK     0x0007ffff
5292 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT    0
5293 static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5294 {
5295     return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5296 }
5297
5298 #define REG_A6XX_SP_HS_CTRL_REG0                0x0000a830
5299 #define A6XX_SP_HS_CTRL_REG0_UNK20              0x00100000
5300 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK           0x00000001
5301 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT          0
5302 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5303 {
5304     return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
5305 }
5306 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x0000007e
5307 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        1
5308 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5309 {
5310     return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5311 }
5312 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x00001f80
5313 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        7
5314 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5315 {
5316     return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5317 }
5318 #define A6XX_SP_HS_CTRL_REG0_UNK13              0x00002000
5319 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK          0x000fc000
5320 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT         14
5321 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5322 {
5323     return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5324 }
5325
5326 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE              0x0000a831
5327
5328 #define REG_A6XX_SP_HS_BRANCH_COND              0x0000a832
5329
5330 #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET            0x0000a833
5331
5332 #define REG_A6XX_SP_HS_OBJ_START                0x0000a834
5333 #define A6XX_SP_HS_OBJ_START__MASK              0xffffffff
5334 #define A6XX_SP_HS_OBJ_START__SHIFT             0
5335 static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
5336 {
5337     return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
5338 }
5339
5340 #define REG_A6XX_SP_HS_PVT_MEM_PARAM                0x0000a836
5341 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK       0x000000ff
5342 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT      0
5343 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5344 {
5345     return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5346 }
5347 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5348 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT    24
5349 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5350 {
5351     return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5352 }
5353
5354 #define REG_A6XX_SP_HS_PVT_MEM_ADDR             0x0000a837
5355 #define A6XX_SP_HS_PVT_MEM_ADDR__MASK               0xffffffff
5356 #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT              0
5357 static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
5358 {
5359     return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
5360 }
5361
5362 #define REG_A6XX_SP_HS_PVT_MEM_SIZE             0x0000a839
5363 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK       0x0003ffff
5364 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT      0
5365 static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5366 {
5367     return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5368 }
5369 #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT        0x80000000
5370
5371 #define REG_A6XX_SP_HS_TEX_COUNT                0x0000a83a
5372
5373 #define REG_A6XX_SP_HS_CONFIG                   0x0000a83b
5374 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX              0x00000001
5375 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP             0x00000002
5376 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO              0x00000004
5377 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO              0x00000008
5378 #define A6XX_SP_HS_CONFIG_ENABLED               0x00000100
5379 #define A6XX_SP_HS_CONFIG_NTEX__MASK                0x0001fe00
5380 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT               9
5381 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
5382 {
5383     return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
5384 }
5385 #define A6XX_SP_HS_CONFIG_NSAMP__MASK               0x003e0000
5386 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT              17
5387 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
5388 {
5389     return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5390 }
5391 #define A6XX_SP_HS_CONFIG_NIBO__MASK                0x1fc00000
5392 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT               22
5393 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5394 {
5395     return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
5396 }
5397
5398 #define REG_A6XX_SP_HS_INSTRLEN                 0x0000a83c
5399
5400 #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET          0x0000a83d
5401 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK     0x0007ffff
5402 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT    0
5403 static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5404 {
5405     return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5406 }
5407
5408 #define REG_A6XX_SP_DS_CTRL_REG0                0x0000a840
5409 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS             0x00100000
5410 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK           0x00000001
5411 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT          0
5412 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5413 {
5414     return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
5415 }
5416 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x0000007e
5417 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        1
5418 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5419 {
5420     return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5421 }
5422 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x00001f80
5423 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        7
5424 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5425 {
5426     return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5427 }
5428 #define A6XX_SP_DS_CTRL_REG0_UNK13              0x00002000
5429 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK          0x000fc000
5430 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT         14
5431 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5432 {
5433     return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5434 }
5435
5436 #define REG_A6XX_SP_DS_BRANCH_COND              0x0000a841
5437
5438 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL               0x0000a842
5439 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK         0x0000003f
5440 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT            0
5441 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5442 {
5443     return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5444 }
5445 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK     0x00003fc0
5446 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT        6
5447 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5448 {
5449     return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5450 }
5451
5452 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5453
5454 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5455 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK            0x000000ff
5456 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT           0
5457 static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
5458 {
5459     return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
5460 }
5461 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK         0x00000f00
5462 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT            8
5463 static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
5464 {
5465     return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
5466 }
5467 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK            0x00ff0000
5468 #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT           16
5469 static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
5470 {
5471     return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
5472 }
5473 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK         0x0f000000
5474 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT            24
5475 static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
5476 {
5477     return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
5478 }
5479
5480 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5481
5482 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5483 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK            0x000000ff
5484 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT           0
5485 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
5486 {
5487     return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
5488 }
5489 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK            0x0000ff00
5490 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT           8
5491 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
5492 {
5493     return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
5494 }
5495 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK            0x00ff0000
5496 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT           16
5497 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
5498 {
5499     return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
5500 }
5501 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK            0xff000000
5502 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT           24
5503 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
5504 {
5505     return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5506 }
5507
5508 #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET            0x0000a85b
5509
5510 #define REG_A6XX_SP_DS_OBJ_START                0x0000a85c
5511 #define A6XX_SP_DS_OBJ_START__MASK              0xffffffff
5512 #define A6XX_SP_DS_OBJ_START__SHIFT             0
5513 static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
5514 {
5515     return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
5516 }
5517
5518 #define REG_A6XX_SP_DS_PVT_MEM_PARAM                0x0000a85e
5519 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK       0x000000ff
5520 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT      0
5521 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5522 {
5523     return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5524 }
5525 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5526 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT    24
5527 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5528 {
5529     return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5530 }
5531
5532 #define REG_A6XX_SP_DS_PVT_MEM_ADDR             0x0000a85f
5533 #define A6XX_SP_DS_PVT_MEM_ADDR__MASK               0xffffffff
5534 #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT              0
5535 static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
5536 {
5537     return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
5538 }
5539
5540 #define REG_A6XX_SP_DS_PVT_MEM_SIZE             0x0000a861
5541 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK       0x0003ffff
5542 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT      0
5543 static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5544 {
5545     return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5546 }
5547 #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT        0x80000000
5548
5549 #define REG_A6XX_SP_DS_TEX_COUNT                0x0000a862
5550
5551 #define REG_A6XX_SP_DS_CONFIG                   0x0000a863
5552 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX              0x00000001
5553 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP             0x00000002
5554 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO              0x00000004
5555 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO              0x00000008
5556 #define A6XX_SP_DS_CONFIG_ENABLED               0x00000100
5557 #define A6XX_SP_DS_CONFIG_NTEX__MASK                0x0001fe00
5558 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT               9
5559 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
5560 {
5561     return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
5562 }
5563 #define A6XX_SP_DS_CONFIG_NSAMP__MASK               0x003e0000
5564 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT              17
5565 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
5566 {
5567     return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5568 }
5569 #define A6XX_SP_DS_CONFIG_NIBO__MASK                0x1fc00000
5570 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT               22
5571 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5572 {
5573     return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
5574 }
5575
5576 #define REG_A6XX_SP_DS_INSTRLEN                 0x0000a864
5577
5578 #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET          0x0000a865
5579 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK     0x0007ffff
5580 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT    0
5581 static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5582 {
5583     return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5584 }
5585
5586 #define REG_A6XX_SP_GS_CTRL_REG0                0x0000a870
5587 #define A6XX_SP_GS_CTRL_REG0_UNK20              0x00100000
5588 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK           0x00000001
5589 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT          0
5590 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5591 {
5592     return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
5593 }
5594 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x0000007e
5595 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        1
5596 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5597 {
5598     return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5599 }
5600 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x00001f80
5601 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        7
5602 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5603 {
5604     return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5605 }
5606 #define A6XX_SP_GS_CTRL_REG0_UNK13              0x00002000
5607 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK          0x000fc000
5608 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT         14
5609 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5610 {
5611     return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5612 }
5613
5614 #define REG_A6XX_SP_GS_PRIM_SIZE                0x0000a871
5615
5616 #define REG_A6XX_SP_GS_BRANCH_COND              0x0000a872
5617
5618 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL               0x0000a873
5619 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK         0x0000003f
5620 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT            0
5621 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
5622 {
5623     return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK;
5624 }
5625 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK     0x00003fc0
5626 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT        6
5627 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5628 {
5629     return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5630 }
5631
5632 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5633
5634 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5635 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK            0x000000ff
5636 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT           0
5637 static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
5638 {
5639     return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
5640 }
5641 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK         0x00000f00
5642 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT            8
5643 static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
5644 {
5645     return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
5646 }
5647 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK            0x00ff0000
5648 #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT           16
5649 static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
5650 {
5651     return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
5652 }
5653 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK         0x0f000000
5654 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT            24
5655 static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
5656 {
5657     return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
5658 }
5659
5660 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5661
5662 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5663 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK            0x000000ff
5664 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT           0
5665 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
5666 {
5667     return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
5668 }
5669 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK            0x0000ff00
5670 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT           8
5671 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
5672 {
5673     return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
5674 }
5675 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK            0x00ff0000
5676 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT           16
5677 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
5678 {
5679     return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
5680 }
5681 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK            0xff000000
5682 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT           24
5683 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
5684 {
5685     return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
5686 }
5687
5688 #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET            0x0000a88c
5689
5690 #define REG_A6XX_SP_GS_OBJ_START                0x0000a88d
5691 #define A6XX_SP_GS_OBJ_START__MASK              0xffffffff
5692 #define A6XX_SP_GS_OBJ_START__SHIFT             0
5693 static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
5694 {
5695     return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
5696 }
5697
5698 #define REG_A6XX_SP_GS_PVT_MEM_PARAM                0x0000a88f
5699 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK       0x000000ff
5700 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT      0
5701 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5702 {
5703     return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5704 }
5705 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5706 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT    24
5707 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5708 {
5709     return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5710 }
5711
5712 #define REG_A6XX_SP_GS_PVT_MEM_ADDR             0x0000a890
5713 #define A6XX_SP_GS_PVT_MEM_ADDR__MASK               0xffffffff
5714 #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT              0
5715 static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
5716 {
5717     return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
5718 }
5719
5720 #define REG_A6XX_SP_GS_PVT_MEM_SIZE             0x0000a892
5721 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK       0x0003ffff
5722 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT      0
5723 static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5724 {
5725     return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5726 }
5727 #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT        0x80000000
5728
5729 #define REG_A6XX_SP_GS_TEX_COUNT                0x0000a893
5730
5731 #define REG_A6XX_SP_GS_CONFIG                   0x0000a894
5732 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX              0x00000001
5733 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP             0x00000002
5734 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO              0x00000004
5735 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO              0x00000008
5736 #define A6XX_SP_GS_CONFIG_ENABLED               0x00000100
5737 #define A6XX_SP_GS_CONFIG_NTEX__MASK                0x0001fe00
5738 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT               9
5739 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
5740 {
5741     return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
5742 }
5743 #define A6XX_SP_GS_CONFIG_NSAMP__MASK               0x003e0000
5744 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT              17
5745 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
5746 {
5747     return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
5748 }
5749 #define A6XX_SP_GS_CONFIG_NIBO__MASK                0x1fc00000
5750 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT               22
5751 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
5752 {
5753     return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
5754 }
5755
5756 #define REG_A6XX_SP_GS_INSTRLEN                 0x0000a895
5757
5758 #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET          0x0000a896
5759 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK     0x0007ffff
5760 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT    0
5761 static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5762 {
5763     return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5764 }
5765
5766 #define REG_A6XX_SP_VS_TEX_SAMP                 0x0000a8a0
5767 #define A6XX_SP_VS_TEX_SAMP__MASK               0xffffffff
5768 #define A6XX_SP_VS_TEX_SAMP__SHIFT              0
5769 static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
5770 {
5771     return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
5772 }
5773
5774 #define REG_A6XX_SP_HS_TEX_SAMP                 0x0000a8a2
5775 #define A6XX_SP_HS_TEX_SAMP__MASK               0xffffffff
5776 #define A6XX_SP_HS_TEX_SAMP__SHIFT              0
5777 static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
5778 {
5779     return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
5780 }
5781
5782 #define REG_A6XX_SP_DS_TEX_SAMP                 0x0000a8a4
5783 #define A6XX_SP_DS_TEX_SAMP__MASK               0xffffffff
5784 #define A6XX_SP_DS_TEX_SAMP__SHIFT              0
5785 static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
5786 {
5787     return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
5788 }
5789
5790 #define REG_A6XX_SP_GS_TEX_SAMP                 0x0000a8a6
5791 #define A6XX_SP_GS_TEX_SAMP__MASK               0xffffffff
5792 #define A6XX_SP_GS_TEX_SAMP__SHIFT              0
5793 static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
5794 {
5795     return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
5796 }
5797
5798 #define REG_A6XX_SP_VS_TEX_CONST                0x0000a8a8
5799 #define A6XX_SP_VS_TEX_CONST__MASK              0xffffffff
5800 #define A6XX_SP_VS_TEX_CONST__SHIFT             0
5801 static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
5802 {
5803     return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
5804 }
5805
5806 #define REG_A6XX_SP_HS_TEX_CONST                0x0000a8aa
5807 #define A6XX_SP_HS_TEX_CONST__MASK              0xffffffff
5808 #define A6XX_SP_HS_TEX_CONST__SHIFT             0
5809 static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
5810 {
5811     return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
5812 }
5813
5814 #define REG_A6XX_SP_DS_TEX_CONST                0x0000a8ac
5815 #define A6XX_SP_DS_TEX_CONST__MASK              0xffffffff
5816 #define A6XX_SP_DS_TEX_CONST__SHIFT             0
5817 static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
5818 {
5819     return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
5820 }
5821
5822 #define REG_A6XX_SP_GS_TEX_CONST                0x0000a8ae
5823 #define A6XX_SP_GS_TEX_CONST__MASK              0xffffffff
5824 #define A6XX_SP_GS_TEX_CONST__SHIFT             0
5825 static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
5826 {
5827     return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
5828 }
5829
5830 #define REG_A6XX_SP_FS_CTRL_REG0                0x0000a980
5831 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK           0x00100000
5832 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT          20
5833 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
5834 {
5835     return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
5836 }
5837 #define A6XX_SP_FS_CTRL_REG0_UNK21              0x00200000
5838 #define A6XX_SP_FS_CTRL_REG0_VARYING                0x00400000
5839 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE              0x00800000
5840 #define A6XX_SP_FS_CTRL_REG0_UNK24              0x01000000
5841 #define A6XX_SP_FS_CTRL_REG0_UNK25              0x02000000
5842 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE           0x04000000
5843 #define A6XX_SP_FS_CTRL_REG0_UNK27__MASK            0x18000000
5844 #define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT           27
5845 static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val)
5846 {
5847     return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK;
5848 }
5849 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS             0x80000000
5850 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK           0x00000001
5851 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT          0
5852 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5853 {
5854     return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
5855 }
5856 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x0000007e
5857 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        1
5858 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5859 {
5860     return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5861 }
5862 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x00001f80
5863 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        7
5864 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5865 {
5866     return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5867 }
5868 #define A6XX_SP_FS_CTRL_REG0_UNK13              0x00002000
5869 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK          0x000fc000
5870 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT         14
5871 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5872 {
5873     return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
5874 }
5875
5876 #define REG_A6XX_SP_FS_BRANCH_COND              0x0000a981
5877
5878 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET            0x0000a982
5879
5880 #define REG_A6XX_SP_FS_OBJ_START                0x0000a983
5881 #define A6XX_SP_FS_OBJ_START__MASK              0xffffffff
5882 #define A6XX_SP_FS_OBJ_START__SHIFT             0
5883 static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
5884 {
5885     return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
5886 }
5887
5888 #define REG_A6XX_SP_FS_PVT_MEM_PARAM                0x0000a985
5889 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK       0x000000ff
5890 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT      0
5891 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5892 {
5893     return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5894 }
5895 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5896 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT    24
5897 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5898 {
5899     return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5900 }
5901
5902 #define REG_A6XX_SP_FS_PVT_MEM_ADDR             0x0000a986
5903 #define A6XX_SP_FS_PVT_MEM_ADDR__MASK               0xffffffff
5904 #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT              0
5905 static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
5906 {
5907     return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
5908 }
5909
5910 #define REG_A6XX_SP_FS_PVT_MEM_SIZE             0x0000a988
5911 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK       0x0003ffff
5912 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT      0
5913 static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5914 {
5915     return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5916 }
5917 #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT        0x80000000
5918
5919 #define REG_A6XX_SP_BLEND_CNTL                  0x0000a989
5920 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK           0x000000ff
5921 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT          0
5922 static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
5923 {
5924     return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
5925 }
5926 #define A6XX_SP_BLEND_CNTL_UNK8                 0x00000100
5927 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE         0x00000200
5928 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE            0x00000400
5929
5930 #define REG_A6XX_SP_SRGB_CNTL                   0x0000a98a
5931 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0             0x00000001
5932 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1             0x00000002
5933 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2             0x00000004
5934 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3             0x00000008
5935 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4             0x00000010
5936 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5             0x00000020
5937 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6             0x00000040
5938 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7             0x00000080
5939
5940 #define REG_A6XX_SP_FS_RENDER_COMPONENTS            0x0000a98b
5941 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK          0x0000000f
5942 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT         0
5943 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
5944 {
5945     return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
5946 }
5947 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK          0x000000f0
5948 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT         4
5949 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
5950 {
5951     return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
5952 }
5953 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK          0x00000f00
5954 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT         8
5955 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
5956 {
5957     return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
5958 }
5959 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK          0x0000f000
5960 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT         12
5961 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
5962 {
5963     return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
5964 }
5965 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK          0x000f0000
5966 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT         16
5967 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
5968 {
5969     return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
5970 }
5971 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK          0x00f00000
5972 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT         20
5973 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
5974 {
5975     return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
5976 }
5977 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK          0x0f000000
5978 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT         24
5979 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
5980 {
5981     return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
5982 }
5983 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK          0xf0000000
5984 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT         28
5985 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
5986 {
5987     return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
5988 }
5989
5990 #define REG_A6XX_SP_FS_OUTPUT_CNTL0             0x0000a98c
5991 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE        0x00000001
5992 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK       0x0000ff00
5993 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT      8
5994 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
5995 {
5996     return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
5997 }
5998 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK        0x00ff0000
5999 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT       16
6000 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
6001 {
6002     return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
6003 }
6004 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK      0xff000000
6005 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT     24
6006 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
6007 {
6008     return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK;
6009 }
6010
6011 #define REG_A6XX_SP_FS_OUTPUT_CNTL1             0x0000a98d
6012 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK           0x0000000f
6013 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT          0
6014 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
6015 {
6016     return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
6017 }
6018
6019 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6020
6021 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6022 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK           0x000000ff
6023 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT          0
6024 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
6025 {
6026     return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
6027 }
6028 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION            0x00000100
6029
6030 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6031
6032 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6033 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK           0x000000ff
6034 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT          0
6035 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
6036 {
6037     return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
6038 }
6039 #define A6XX_SP_FS_MRT_REG_COLOR_SINT               0x00000100
6040 #define A6XX_SP_FS_MRT_REG_COLOR_UINT               0x00000200
6041 #define A6XX_SP_FS_MRT_REG_UNK10                0x00000400
6042
6043 #define REG_A6XX_SP_FS_PREFETCH_CNTL                0x0000a99e
6044 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK            0x00000007
6045 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT           0
6046 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
6047 {
6048     return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
6049 }
6050 #define A6XX_SP_FS_PREFETCH_CNTL_UNK3               0x00000008
6051 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK         0x00000ff0
6052 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT            4
6053 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
6054 {
6055     return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
6056 }
6057 #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK            0x00007000
6058 #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT           12
6059 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val)
6060 {
6061     return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK;
6062 }
6063
6064 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6065
6066 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6067 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK           0x0000007f
6068 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT          0
6069 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
6070 {
6071     return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
6072 }
6073 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK           0x00000780
6074 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT          7
6075 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6076 {
6077     return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
6078 }
6079 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK            0x0000f800
6080 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT           11
6081 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
6082 {
6083     return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
6084 }
6085 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK           0x003f0000
6086 #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT          16
6087 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
6088 {
6089     return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
6090 }
6091 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK            0x03c00000
6092 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT           22
6093 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
6094 {
6095     return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
6096 }
6097 #define A6XX_SP_FS_PREFETCH_CMD_HALF                0x04000000
6098 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK           0xf8000000
6099 #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT          27
6100 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
6101 {
6102     return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
6103 }
6104
6105 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6106
6107 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6108 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK      0x0000ffff
6109 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT     0
6110 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6111 {
6112     return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
6113 }
6114 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK       0xffff0000
6115 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT      16
6116 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
6117 {
6118     return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
6119 }
6120
6121 #define REG_A6XX_SP_FS_TEX_COUNT                0x0000a9a7
6122
6123 #define REG_A6XX_SP_UNKNOWN_A9A8                0x0000a9a8
6124
6125 #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET          0x0000a9a9
6126 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK     0x0007ffff
6127 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT    0
6128 static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
6129 {
6130     return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
6131 }
6132
6133 #define REG_A6XX_SP_CS_CTRL_REG0                0x0000a9b0
6134 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK           0x00100000
6135 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT          20
6136 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
6137 {
6138     return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
6139 }
6140 #define A6XX_SP_CS_CTRL_REG0_UNK21              0x00200000
6141 #define A6XX_SP_CS_CTRL_REG0_UNK22              0x00400000
6142 #define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG         0x00800000
6143 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS             0x80000000
6144 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK           0x00000001
6145 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT          0
6146 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
6147 {
6148     return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
6149 }
6150 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x0000007e
6151 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        1
6152 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
6153 {
6154     return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
6155 }
6156 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x00001f80
6157 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        7
6158 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
6159 {
6160     return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6161 }
6162 #define A6XX_SP_CS_CTRL_REG0_UNK13              0x00002000
6163 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK          0x000fc000
6164 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT         14
6165 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6166 {
6167     return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
6168 }
6169
6170 #define REG_A6XX_SP_CS_UNKNOWN_A9B1             0x0000a9b1
6171 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK       0x0000001f
6172 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT      0
6173 static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
6174 {
6175     return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
6176 }
6177 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5                0x00000020
6178 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6                0x00000040
6179
6180 #define REG_A6XX_SP_CS_BRANCH_COND              0x0000a9b2
6181
6182 #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET            0x0000a9b3
6183
6184 #define REG_A6XX_SP_CS_OBJ_START                0x0000a9b4
6185 #define A6XX_SP_CS_OBJ_START__MASK              0xffffffff
6186 #define A6XX_SP_CS_OBJ_START__SHIFT             0
6187 static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
6188 {
6189     return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
6190 }
6191
6192 #define REG_A6XX_SP_CS_PVT_MEM_PARAM                0x0000a9b6
6193 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK       0x000000ff
6194 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT      0
6195 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
6196 {
6197     return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6198 }
6199 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6200 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT    24
6201 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6202 {
6203     return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6204 }
6205
6206 #define REG_A6XX_SP_CS_PVT_MEM_ADDR             0x0000a9b7
6207 #define A6XX_SP_CS_PVT_MEM_ADDR__MASK               0xffffffff
6208 #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT              0
6209 static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
6210 {
6211     return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
6212 }
6213
6214 #define REG_A6XX_SP_CS_PVT_MEM_SIZE             0x0000a9b9
6215 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK       0x0003ffff
6216 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT      0
6217 static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6218 {
6219     return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6220 }
6221 #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT        0x80000000
6222
6223 #define REG_A6XX_SP_CS_TEX_COUNT                0x0000a9ba
6224
6225 #define REG_A6XX_SP_CS_CONFIG                   0x0000a9bb
6226 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX              0x00000001
6227 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP             0x00000002
6228 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO              0x00000004
6229 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO              0x00000008
6230 #define A6XX_SP_CS_CONFIG_ENABLED               0x00000100
6231 #define A6XX_SP_CS_CONFIG_NTEX__MASK                0x0001fe00
6232 #define A6XX_SP_CS_CONFIG_NTEX__SHIFT               9
6233 static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
6234 {
6235     return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
6236 }
6237 #define A6XX_SP_CS_CONFIG_NSAMP__MASK               0x003e0000
6238 #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT              17
6239 static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
6240 {
6241     return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6242 }
6243 #define A6XX_SP_CS_CONFIG_NIBO__MASK                0x1fc00000
6244 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT               22
6245 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6246 {
6247     return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
6248 }
6249
6250 #define REG_A6XX_SP_CS_INSTRLEN                 0x0000a9bc
6251
6252 #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET          0x0000a9bd
6253 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK     0x0007ffff
6254 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT    0
6255 static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
6256 {
6257     return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
6258 }
6259
6260 #define REG_A6XX_SP_CS_CNTL_0                   0x0000a9c2
6261 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK         0x000000ff
6262 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT            0
6263 static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val)
6264 {
6265     return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK;
6266 }
6267 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK           0x0000ff00
6268 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT          8
6269 static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
6270 {
6271     return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK;
6272 }
6273 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK         0x00ff0000
6274 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT        16
6275 static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
6276 {
6277     return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK;
6278 }
6279 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK            0xff000000
6280 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT           24
6281 static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val)
6282 {
6283     return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK;
6284 }
6285
6286 #define REG_A6XX_SP_CS_CNTL_1                   0x0000a9c3
6287 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK      0x000000ff
6288 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT     0
6289 static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
6290 {
6291     return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
6292 }
6293 #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE            0x00000100
6294 #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK          0x00000200
6295 #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT         9
6296 static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
6297 {
6298     return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK;
6299 }
6300 #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR         0x00000400
6301
6302 #define REG_A6XX_SP_FS_TEX_SAMP                 0x0000a9e0
6303 #define A6XX_SP_FS_TEX_SAMP__MASK               0xffffffff
6304 #define A6XX_SP_FS_TEX_SAMP__SHIFT              0
6305 static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
6306 {
6307     return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
6308 }
6309
6310 #define REG_A6XX_SP_CS_TEX_SAMP                 0x0000a9e2
6311 #define A6XX_SP_CS_TEX_SAMP__MASK               0xffffffff
6312 #define A6XX_SP_CS_TEX_SAMP__SHIFT              0
6313 static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
6314 {
6315     return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
6316 }
6317
6318 #define REG_A6XX_SP_FS_TEX_CONST                0x0000a9e4
6319 #define A6XX_SP_FS_TEX_CONST__MASK              0xffffffff
6320 #define A6XX_SP_FS_TEX_CONST__SHIFT             0
6321 static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
6322 {
6323     return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
6324 }
6325
6326 #define REG_A6XX_SP_CS_TEX_CONST                0x0000a9e6
6327 #define A6XX_SP_CS_TEX_CONST__MASK              0xffffffff
6328 #define A6XX_SP_CS_TEX_CONST__SHIFT             0
6329 static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
6330 {
6331     return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
6332 }
6333
6334 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6335
6336 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6337
6338 #define REG_A6XX_SP_CS_IBO                  0x0000a9f2
6339 #define A6XX_SP_CS_IBO__MASK                    0xffffffff
6340 #define A6XX_SP_CS_IBO__SHIFT                   0
6341 static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
6342 {
6343     return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
6344 }
6345
6346 #define REG_A6XX_SP_CS_IBO_COUNT                0x0000aa00
6347
6348 #define REG_A6XX_SP_MODE_CONTROL                0x0000ab00
6349 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE       0x00000001
6350 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK         0x00000006
6351 #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT            1
6352 static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val)
6353 {
6354     return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK;
6355 }
6356 #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE       0x00000008
6357
6358 #define REG_A6XX_SP_FS_CONFIG                   0x0000ab04
6359 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX              0x00000001
6360 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP             0x00000002
6361 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO              0x00000004
6362 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO              0x00000008
6363 #define A6XX_SP_FS_CONFIG_ENABLED               0x00000100
6364 #define A6XX_SP_FS_CONFIG_NTEX__MASK                0x0001fe00
6365 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT               9
6366 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
6367 {
6368     return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
6369 }
6370 #define A6XX_SP_FS_CONFIG_NSAMP__MASK               0x003e0000
6371 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT              17
6372 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
6373 {
6374     return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6375 }
6376 #define A6XX_SP_FS_CONFIG_NIBO__MASK                0x1fc00000
6377 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT               22
6378 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6379 {
6380     return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
6381 }
6382
6383 #define REG_A6XX_SP_FS_INSTRLEN                 0x0000ab05
6384
6385 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6386
6387 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6388
6389 #define REG_A6XX_SP_IBO                     0x0000ab1a
6390 #define A6XX_SP_IBO__MASK                   0xffffffff
6391 #define A6XX_SP_IBO__SHIFT                  0
6392 static inline uint32_t A6XX_SP_IBO(uint32_t val)
6393 {
6394     return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
6395 }
6396
6397 #define REG_A6XX_SP_IBO_COUNT                   0x0000ab20
6398
6399 #define REG_A6XX_SP_2D_DST_FORMAT               0x0000acc0
6400 #define A6XX_SP_2D_DST_FORMAT_NORM              0x00000001
6401 #define A6XX_SP_2D_DST_FORMAT_SINT              0x00000002
6402 #define A6XX_SP_2D_DST_FORMAT_UINT              0x00000004
6403 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK        0x000007f8
6404 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT       3
6405 static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
6406 {
6407     return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
6408 }
6409 #define A6XX_SP_2D_DST_FORMAT_SRGB              0x00000800
6410 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK            0x0000f000
6411 #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT           12
6412 static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
6413 {
6414     return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
6415 }
6416
6417 #define REG_A6XX_SP_UNKNOWN_AE00                0x0000ae00
6418
6419 #define REG_A6XX_SP_ADDR_MODE_CNTL              0x0000ae01
6420
6421 #define REG_A6XX_SP_NC_MODE_CNTL                0x0000ae02
6422
6423 #define REG_A6XX_SP_CHICKEN_BITS                0x0000ae03
6424
6425 #define REG_A6XX_SP_FLOAT_CNTL                  0x0000ae04
6426 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF               0x00000008
6427
6428 #define REG_A6XX_SP_PERFCTR_ENABLE              0x0000ae0f
6429 #define A6XX_SP_PERFCTR_ENABLE_VS               0x00000001
6430 #define A6XX_SP_PERFCTR_ENABLE_HS               0x00000002
6431 #define A6XX_SP_PERFCTR_ENABLE_DS               0x00000004
6432 #define A6XX_SP_PERFCTR_ENABLE_GS               0x00000008
6433 #define A6XX_SP_PERFCTR_ENABLE_FS               0x00000010
6434 #define A6XX_SP_PERFCTR_ENABLE_CS               0x00000020
6435
6436 static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
6437
6438 #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
6439
6440 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR        0x0000b180
6441 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK      0xffffffff
6442 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT     0
6443 static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6444 {
6445     return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
6446 }
6447
6448 #define REG_A6XX_SP_UNKNOWN_B182                0x0000b182
6449
6450 #define REG_A6XX_SP_UNKNOWN_B183                0x0000b183
6451
6452 #define REG_A6XX_SP_UNKNOWN_B190                0x0000b190
6453
6454 #define REG_A6XX_SP_UNKNOWN_B191                0x0000b191
6455
6456 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL                0x0000b300
6457 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK          0x00000003
6458 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT         0
6459 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6460 {
6461     return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6462 }
6463 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK         0x0000000c
6464 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT            2
6465 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
6466 {
6467     return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
6468 }
6469
6470 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL               0x0000b301
6471 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK         0x00000003
6472 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT        0
6473 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6474 {
6475     return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
6476 }
6477 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE          0x00000004
6478
6479 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR           0x0000b302
6480 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK         0xffffffff
6481 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT        0
6482 static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6483 {
6484     return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
6485 }
6486
6487 #define REG_A6XX_SP_TP_SAMPLE_CONFIG                0x0000b304
6488 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0               0x00000001
6489 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE        0x00000002
6490
6491 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0            0x0000b305
6492 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK       0x0000000f
6493 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT      0
6494 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
6495 {
6496     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
6497 }
6498 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK       0x000000f0
6499 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT      4
6500 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
6501 {
6502     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
6503 }
6504 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK       0x00000f00
6505 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT      8
6506 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
6507 {
6508     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
6509 }
6510 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK       0x0000f000
6511 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT      12
6512 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
6513 {
6514     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
6515 }
6516 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK       0x000f0000
6517 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT      16
6518 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
6519 {
6520     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
6521 }
6522 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK       0x00f00000
6523 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT      20
6524 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
6525 {
6526     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
6527 }
6528 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK       0x0f000000
6529 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT      24
6530 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
6531 {
6532     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
6533 }
6534 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK       0xf0000000
6535 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT      28
6536 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
6537 {
6538     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
6539 }
6540
6541 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1            0x0000b306
6542 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK       0x0000000f
6543 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT      0
6544 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
6545 {
6546     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
6547 }
6548 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK       0x000000f0
6549 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT      4
6550 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
6551 {
6552     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
6553 }
6554 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK       0x00000f00
6555 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT      8
6556 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
6557 {
6558     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
6559 }
6560 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK       0x0000f000
6561 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT      12
6562 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
6563 {
6564     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
6565 }
6566 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK       0x000f0000
6567 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT      16
6568 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
6569 {
6570     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
6571 }
6572 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK       0x00f00000
6573 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT      20
6574 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
6575 {
6576     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
6577 }
6578 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK       0x0f000000
6579 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT      24
6580 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
6581 {
6582     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
6583 }
6584 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK       0xf0000000
6585 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT      28
6586 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
6587 {
6588     return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6589 }
6590
6591 #define REG_A6XX_SP_TP_WINDOW_OFFSET                0x0000b307
6592 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK            0x00003fff
6593 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT           0
6594 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
6595 {
6596     return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
6597 }
6598 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK            0x3fff0000
6599 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT           16
6600 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
6601 {
6602     return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
6603 }
6604
6605 #define REG_A6XX_SP_TP_MODE_CNTL                0x0000b309
6606 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK         0x00000003
6607 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT            0
6608 static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val)
6609 {
6610     return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK;
6611 }
6612 #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK             0x000000fc
6613 #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT            2
6614 static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val)
6615 {
6616     return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK;
6617 }
6618
6619 #define REG_A6XX_SP_PS_2D_SRC_INFO              0x0000b4c0
6620 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK       0x000000ff
6621 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT      0
6622 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
6623 {
6624     return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
6625 }
6626 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK          0x00000300
6627 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT         8
6628 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
6629 {
6630     return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
6631 }
6632 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK         0x00000c00
6633 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT        10
6634 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
6635 {
6636     return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
6637 }
6638 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS                0x00001000
6639 #define A6XX_SP_PS_2D_SRC_INFO_SRGB             0x00002000
6640 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK            0x0000c000
6641 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT           14
6642 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
6643 {
6644     return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6645 }
6646 #define A6XX_SP_PS_2D_SRC_INFO_FILTER               0x00010000
6647 #define A6XX_SP_PS_2D_SRC_INFO_UNK17                0x00020000
6648 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE          0x00040000
6649 #define A6XX_SP_PS_2D_SRC_INFO_UNK19                0x00080000
6650 #define A6XX_SP_PS_2D_SRC_INFO_UNK20                0x00100000
6651 #define A6XX_SP_PS_2D_SRC_INFO_UNK21                0x00200000
6652 #define A6XX_SP_PS_2D_SRC_INFO_UNK22                0x00400000
6653 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK          0x07800000
6654 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT         23
6655 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
6656 {
6657     return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
6658 }
6659 #define A6XX_SP_PS_2D_SRC_INFO_UNK28                0x10000000
6660
6661 #define REG_A6XX_SP_PS_2D_SRC_SIZE              0x0000b4c1
6662 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK          0x00007fff
6663 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT         0
6664 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
6665 {
6666     return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
6667 }
6668 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK         0x3fff8000
6669 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT            15
6670 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
6671 {
6672     return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6673 }
6674
6675 #define REG_A6XX_SP_PS_2D_SRC                   0x0000b4c2
6676 #define A6XX_SP_PS_2D_SRC__MASK                 0xffffffff
6677 #define A6XX_SP_PS_2D_SRC__SHIFT                0
6678 static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
6679 {
6680     return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
6681 }
6682
6683 #define REG_A6XX_SP_PS_2D_SRC_PITCH             0x0000b4c4
6684 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK          0x000001ff
6685 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT         0
6686 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
6687 {
6688     return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
6689 }
6690 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK         0x00fffe00
6691 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT            9
6692 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6693 {
6694     return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6695 }
6696
6697 #define REG_A6XX_SP_PS_2D_SRC_PLANE1                0x0000b4c5
6698 #define A6XX_SP_PS_2D_SRC_PLANE1__MASK              0xffffffff
6699 #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT             0
6700 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
6701 {
6702     return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
6703 }
6704
6705 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH           0x0000b4c7
6706 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK         0x00000fff
6707 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT            0
6708 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
6709 {
6710     return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
6711 }
6712
6713 #define REG_A6XX_SP_PS_2D_SRC_PLANE2                0x0000b4c8
6714 #define A6XX_SP_PS_2D_SRC_PLANE2__MASK              0xffffffff
6715 #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT             0
6716 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
6717 {
6718     return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
6719 }
6720
6721 #define REG_A6XX_SP_PS_2D_SRC_FLAGS             0x0000b4ca
6722 #define A6XX_SP_PS_2D_SRC_FLAGS__MASK               0xffffffff
6723 #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT              0
6724 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
6725 {
6726     return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
6727 }
6728
6729 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH           0x0000b4cc
6730 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK         0x000000ff
6731 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT            0
6732 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
6733 {
6734     return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
6735 }
6736
6737 #define REG_A6XX_SP_PS_UNKNOWN_B4CD             0x0000b4cd
6738
6739 #define REG_A6XX_SP_PS_UNKNOWN_B4CE             0x0000b4ce
6740
6741 #define REG_A6XX_SP_PS_UNKNOWN_B4CF             0x0000b4cf
6742
6743 #define REG_A6XX_SP_PS_UNKNOWN_B4D0             0x0000b4d0
6744
6745 #define REG_A6XX_SP_WINDOW_OFFSET               0x0000b4d1
6746 #define A6XX_SP_WINDOW_OFFSET_X__MASK               0x00003fff
6747 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT              0
6748 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
6749 {
6750     return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
6751 }
6752 #define A6XX_SP_WINDOW_OFFSET_Y__MASK               0x3fff0000
6753 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT              16
6754 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
6755 {
6756     return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
6757 }
6758
6759 #define REG_A6XX_TPL1_DBG_ECO_CNTL              0x0000b600
6760
6761 #define REG_A6XX_TPL1_ADDR_MODE_CNTL                0x0000b601
6762
6763 #define REG_A6XX_TPL1_UNKNOWN_B602              0x0000b602
6764
6765 #define REG_A6XX_TPL1_NC_MODE_CNTL              0x0000b604
6766 #define A6XX_TPL1_NC_MODE_CNTL_MODE             0x00000001
6767 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK          0x00000006
6768 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT         1
6769 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
6770 {
6771     return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
6772 }
6773 #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH        0x00000008
6774 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK          0x00000010
6775 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT         4
6776 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
6777 {
6778     return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
6779 }
6780 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK           0x000000c0
6781 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT          6
6782 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
6783 {
6784     return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
6785 }
6786
6787 #define REG_A6XX_TPL1_UNKNOWN_B605              0x0000b605
6788
6789 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0           0x0000b608
6790
6791 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1           0x0000b609
6792
6793 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2           0x0000b60a
6794
6795 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3           0x0000b60b
6796
6797 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4           0x0000b60c
6798
6799 static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
6800
6801 #define REG_A6XX_HLSQ_VS_CNTL                   0x0000b800
6802 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK            0x000000ff
6803 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT           0
6804 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
6805 {
6806     return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
6807 }
6808 #define A6XX_HLSQ_VS_CNTL_ENABLED               0x00000100
6809
6810 #define REG_A6XX_HLSQ_HS_CNTL                   0x0000b801
6811 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK            0x000000ff
6812 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT           0
6813 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
6814 {
6815     return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
6816 }
6817 #define A6XX_HLSQ_HS_CNTL_ENABLED               0x00000100
6818
6819 #define REG_A6XX_HLSQ_DS_CNTL                   0x0000b802
6820 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK            0x000000ff
6821 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT           0
6822 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
6823 {
6824     return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
6825 }
6826 #define A6XX_HLSQ_DS_CNTL_ENABLED               0x00000100
6827
6828 #define REG_A6XX_HLSQ_GS_CNTL                   0x0000b803
6829 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK            0x000000ff
6830 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT           0
6831 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
6832 {
6833     return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
6834 }
6835 #define A6XX_HLSQ_GS_CNTL_ENABLED               0x00000100
6836
6837 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD           0x0000b820
6838
6839 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR      0x0000b821
6840 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK        0xffffffff
6841 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT       0
6842 static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
6843 {
6844     return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
6845 }
6846
6847 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA          0x0000b823
6848
6849 #define REG_A6XX_HLSQ_FS_CNTL_0                 0x0000b980
6850 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK            0x00000001
6851 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT           0
6852 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
6853 {
6854     return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
6855 }
6856 #define A6XX_HLSQ_FS_CNTL_0_VARYINGS                0x00000002
6857 #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK              0x00000ffc
6858 #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT             2
6859 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
6860 {
6861     return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
6862 }
6863
6864 #define REG_A6XX_HLSQ_UNKNOWN_B981              0x0000b981
6865
6866 #define REG_A6XX_HLSQ_CONTROL_1_REG             0x0000b982
6867
6868 #define REG_A6XX_HLSQ_CONTROL_2_REG             0x0000b983
6869 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK         0x000000ff
6870 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT        0
6871 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
6872 {
6873     return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
6874 }
6875 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK          0x0000ff00
6876 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT         8
6877 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
6878 {
6879     return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
6880 }
6881 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK        0x00ff0000
6882 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT       16
6883 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
6884 {
6885     return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
6886 }
6887 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK          0xff000000
6888 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT         24
6889 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
6890 {
6891     return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
6892 }
6893
6894 #define REG_A6XX_HLSQ_CONTROL_3_REG             0x0000b984
6895 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK        0x000000ff
6896 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT       0
6897 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
6898 {
6899     return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
6900 }
6901 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK       0x0000ff00
6902 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT      8
6903 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
6904 {
6905     return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
6906 }
6907 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK     0x00ff0000
6908 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT    16
6909 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
6910 {
6911     return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
6912 }
6913 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK    0xff000000
6914 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT   24
6915 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
6916 {
6917     return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
6918 }
6919
6920 #define REG_A6XX_HLSQ_CONTROL_4_REG             0x0000b985
6921 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK       0x000000ff
6922 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT      0
6923 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
6924 {
6925     return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
6926 }
6927 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK      0x0000ff00
6928 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT     8
6929 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
6930 {
6931     return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
6932 }
6933 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK      0x00ff0000
6934 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT     16
6935 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
6936 {
6937     return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
6938 }
6939 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK      0xff000000
6940 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT     24
6941 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
6942 {
6943     return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
6944 }
6945
6946 #define REG_A6XX_HLSQ_CONTROL_5_REG             0x0000b986
6947 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK       0x000000ff
6948 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT      0
6949 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
6950 {
6951     return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
6952 }
6953 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
6954 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT    8
6955 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
6956 {
6957     return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
6958 }
6959
6960 #define REG_A6XX_HLSQ_CS_CNTL                   0x0000b987
6961 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK            0x000000ff
6962 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT           0
6963 static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
6964 {
6965     return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
6966 }
6967 #define A6XX_HLSQ_CS_CNTL_ENABLED               0x00000100
6968
6969 #define REG_A6XX_HLSQ_CS_NDRANGE_0              0x0000b990
6970 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK          0x00000003
6971 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT         0
6972 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
6973 {
6974     return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
6975 }
6976 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK         0x00000ffc
6977 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT        2
6978 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
6979 {
6980     return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
6981 }
6982 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK         0x003ff000
6983 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT        12
6984 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
6985 {
6986     return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
6987 }
6988 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK         0xffc00000
6989 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT        22
6990 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
6991 {
6992     return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
6993 }
6994
6995 #define REG_A6XX_HLSQ_CS_NDRANGE_1              0x0000b991
6996 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK       0xffffffff
6997 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT      0
6998 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
6999 {
7000     return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
7001 }
7002
7003 #define REG_A6XX_HLSQ_CS_NDRANGE_2              0x0000b992
7004 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK        0xffffffff
7005 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT       0
7006 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
7007 {
7008     return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
7009 }
7010
7011 #define REG_A6XX_HLSQ_CS_NDRANGE_3              0x0000b993
7012 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK       0xffffffff
7013 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT      0
7014 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
7015 {
7016     return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
7017 }
7018
7019 #define REG_A6XX_HLSQ_CS_NDRANGE_4              0x0000b994
7020 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK        0xffffffff
7021 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT       0
7022 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
7023 {
7024     return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
7025 }
7026
7027 #define REG_A6XX_HLSQ_CS_NDRANGE_5              0x0000b995
7028 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK       0xffffffff
7029 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT      0
7030 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
7031 {
7032     return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
7033 }
7034
7035 #define REG_A6XX_HLSQ_CS_NDRANGE_6              0x0000b996
7036 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK        0xffffffff
7037 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT       0
7038 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
7039 {
7040     return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
7041 }
7042
7043 #define REG_A6XX_HLSQ_CS_CNTL_0                 0x0000b997
7044 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK           0x000000ff
7045 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT          0
7046 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
7047 {
7048     return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
7049 }
7050 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK         0x0000ff00
7051 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT        8
7052 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
7053 {
7054     return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
7055 }
7056 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK       0x00ff0000
7057 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT      16
7058 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
7059 {
7060     return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
7061 }
7062 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK          0xff000000
7063 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT         24
7064 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
7065 {
7066     return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
7067 }
7068
7069 #define REG_A6XX_HLSQ_CS_CNTL_1                 0x0000b998
7070 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK        0x000000ff
7071 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT       0
7072 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
7073 {
7074     return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
7075 }
7076 #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE          0x00000100
7077 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK            0x00000200
7078 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT           9
7079 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
7080 {
7081     return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
7082 }
7083 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR           0x00000400
7084
7085 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X             0x0000b999
7086
7087 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y             0x0000b99a
7088
7089 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z             0x0000b99b
7090
7091 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD           0x0000b9a0
7092
7093 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR      0x0000b9a1
7094 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK        0xffffffff
7095 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT       0
7096 static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
7097 {
7098     return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
7099 }
7100
7101 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA          0x0000b9a3
7102
7103 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
7104
7105 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
7106
7107 #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0               0x0000b9d0
7108 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK     0x0000001f
7109 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT        0
7110 static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val)
7111 {
7112     return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK;
7113 }
7114 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5              0x00000020
7115 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6              0x00000040
7116
7117 #define REG_A6XX_HLSQ_DRAW_CMD                  0x0000bb00
7118 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK           0x000000ff
7119 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT          0
7120 static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
7121 {
7122     return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
7123 }
7124
7125 #define REG_A6XX_HLSQ_DISPATCH_CMD              0x0000bb01
7126 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK           0x000000ff
7127 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT          0
7128 static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
7129 {
7130     return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
7131 }
7132
7133 #define REG_A6XX_HLSQ_EVENT_CMD                 0x0000bb02
7134 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK          0x00ff0000
7135 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT         16
7136 static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
7137 {
7138     return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
7139 }
7140 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK             0x0000007f
7141 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT            0
7142 static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
7143 {
7144     return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
7145 }
7146
7147 #define REG_A6XX_HLSQ_INVALIDATE_CMD                0x0000bb08
7148 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE           0x00000001
7149 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE           0x00000002
7150 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE           0x00000004
7151 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE           0x00000008
7152 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE           0x00000010
7153 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE           0x00000020
7154 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO             0x00000040
7155 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO            0x00000080
7156 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST        0x00080000
7157 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST       0x00000100
7158 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK      0x00003e00
7159 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT     9
7160 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
7161 {
7162     return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
7163 }
7164 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK     0x0007c000
7165 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT        14
7166 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
7167 {
7168     return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
7169 }
7170
7171 #define REG_A6XX_HLSQ_FS_CNTL                   0x0000bb10
7172 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK            0x000000ff
7173 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT           0
7174 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
7175 {
7176     return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
7177 }
7178 #define A6XX_HLSQ_FS_CNTL_ENABLED               0x00000100
7179
7180 #define REG_A6XX_HLSQ_SHARED_CONSTS             0x0000bb11
7181 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE              0x00000001
7182
7183 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7184
7185 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7186
7187 #define REG_A6XX_HLSQ_2D_EVENT_CMD              0x0000bd80
7188 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK           0x0000ff00
7189 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT          8
7190 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
7191 {
7192     return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
7193 }
7194 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK          0x0000007f
7195 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT         0
7196 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
7197 {
7198     return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
7199 }
7200
7201 #define REG_A6XX_HLSQ_UNKNOWN_BE00              0x0000be00
7202
7203 #define REG_A6XX_HLSQ_UNKNOWN_BE01              0x0000be01
7204
7205 #define REG_A6XX_HLSQ_UNKNOWN_BE04              0x0000be04
7206
7207 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL                0x0000be05
7208
7209 #define REG_A6XX_HLSQ_UNKNOWN_BE08              0x0000be08
7210
7211 static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
7212
7213 #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE   0x0000be22
7214
7215 #define REG_A6XX_CP_EVENT_START                 0x0000d600
7216 #define A6XX_CP_EVENT_START_STATE_ID__MASK          0x000000ff
7217 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT         0
7218 static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
7219 {
7220     return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
7221 }
7222
7223 #define REG_A6XX_CP_EVENT_END                   0x0000d601
7224 #define A6XX_CP_EVENT_END_STATE_ID__MASK            0x000000ff
7225 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT           0
7226 static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
7227 {
7228     return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
7229 }
7230
7231 #define REG_A6XX_CP_2D_EVENT_START              0x0000d700
7232 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK           0x000000ff
7233 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT          0
7234 static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
7235 {
7236     return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
7237 }
7238
7239 #define REG_A6XX_CP_2D_EVENT_END                0x0000d701
7240 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK         0x000000ff
7241 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT            0
7242 static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
7243 {
7244     return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
7245 }
7246
7247 #define REG_A6XX_TEX_SAMP_0                 0x00000000
7248 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR           0x00000001
7249 #define A6XX_TEX_SAMP_0_XY_MAG__MASK                0x00000006
7250 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT               1
7251 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
7252 {
7253     return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
7254 }
7255 #define A6XX_TEX_SAMP_0_XY_MIN__MASK                0x00000018
7256 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT               3
7257 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
7258 {
7259     return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
7260 }
7261 #define A6XX_TEX_SAMP_0_WRAP_S__MASK                0x000000e0
7262 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT               5
7263 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
7264 {
7265     return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
7266 }
7267 #define A6XX_TEX_SAMP_0_WRAP_T__MASK                0x00000700
7268 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT               8
7269 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
7270 {
7271     return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
7272 }
7273 #define A6XX_TEX_SAMP_0_WRAP_R__MASK                0x00003800
7274 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT               11
7275 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
7276 {
7277     return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
7278 }
7279 #define A6XX_TEX_SAMP_0_ANISO__MASK             0x0001c000
7280 #define A6XX_TEX_SAMP_0_ANISO__SHIFT                14
7281 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
7282 {
7283     return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
7284 }
7285 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK              0xfff80000
7286 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT             19
7287 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
7288 {
7289     return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
7290 }
7291
7292 #define REG_A6XX_TEX_SAMP_1                 0x00000001
7293 #define A6XX_TEX_SAMP_1_CLAMPENABLE             0x00000001
7294 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK          0x0000000e
7295 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT         1
7296 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
7297 {
7298     return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
7299 }
7300 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF          0x00000010
7301 #define A6XX_TEX_SAMP_1_UNNORM_COORDS               0x00000020
7302 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR            0x00000040
7303 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK               0x000fff00
7304 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT              8
7305 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
7306 {
7307     return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
7308 }
7309 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK               0xfff00000
7310 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT              20
7311 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
7312 {
7313     return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
7314 }
7315
7316 #define REG_A6XX_TEX_SAMP_2                 0x00000002
7317 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK            0x00000003
7318 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT           0
7319 static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
7320 {
7321     return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7322 }
7323 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR               0x00000020
7324 #define A6XX_TEX_SAMP_2_BCOLOR__MASK                0xffffff80
7325 #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT               7
7326 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
7327 {
7328     return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
7329 }
7330
7331 #define REG_A6XX_TEX_SAMP_3                 0x00000003
7332
7333 #define REG_A6XX_TEX_CONST_0                    0x00000000
7334 #define A6XX_TEX_CONST_0_TILE_MODE__MASK            0x00000003
7335 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT           0
7336 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
7337 {
7338     return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
7339 }
7340 #define A6XX_TEX_CONST_0_SRGB                   0x00000004
7341 #define A6XX_TEX_CONST_0_SWIZ_X__MASK               0x00000070
7342 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT              4
7343 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
7344 {
7345     return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
7346 }
7347 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK               0x00000380
7348 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT              7
7349 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
7350 {
7351     return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
7352 }
7353 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK               0x00001c00
7354 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT              10
7355 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
7356 {
7357     return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
7358 }
7359 #define A6XX_TEX_CONST_0_SWIZ_W__MASK               0x0000e000
7360 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT              13
7361 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
7362 {
7363     return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
7364 }
7365 #define A6XX_TEX_CONST_0_MIPLVLS__MASK              0x000f0000
7366 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT             16
7367 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
7368 {
7369     return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
7370 }
7371 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X          0x00010000
7372 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y          0x00040000
7373 #define A6XX_TEX_CONST_0_SAMPLES__MASK              0x00300000
7374 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT             20
7375 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
7376 {
7377     return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
7378 }
7379 #define A6XX_TEX_CONST_0_FMT__MASK              0x3fc00000
7380 #define A6XX_TEX_CONST_0_FMT__SHIFT             22
7381 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
7382 {
7383     return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
7384 }
7385 #define A6XX_TEX_CONST_0_SWAP__MASK             0xc0000000
7386 #define A6XX_TEX_CONST_0_SWAP__SHIFT                30
7387 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
7388 {
7389     return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
7390 }
7391
7392 #define REG_A6XX_TEX_CONST_1                    0x00000001
7393 #define A6XX_TEX_CONST_1_WIDTH__MASK                0x00007fff
7394 #define A6XX_TEX_CONST_1_WIDTH__SHIFT               0
7395 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
7396 {
7397     return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
7398 }
7399 #define A6XX_TEX_CONST_1_HEIGHT__MASK               0x3fff8000
7400 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT              15
7401 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
7402 {
7403     return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
7404 }
7405
7406 #define REG_A6XX_TEX_CONST_2                    0x00000002
7407 #define A6XX_TEX_CONST_2_BUFFER                 0x00000010
7408 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK           0x0000000f
7409 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT          0
7410 static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
7411 {
7412     return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
7413 }
7414 #define A6XX_TEX_CONST_2_PITCH__MASK                0x1fffff80
7415 #define A6XX_TEX_CONST_2_PITCH__SHIFT               7
7416 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
7417 {
7418     return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
7419 }
7420 #define A6XX_TEX_CONST_2_TYPE__MASK             0xe0000000
7421 #define A6XX_TEX_CONST_2_TYPE__SHIFT                29
7422 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
7423 {
7424     return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
7425 }
7426
7427 #define REG_A6XX_TEX_CONST_3                    0x00000003
7428 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK          0x00003fff
7429 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT         0
7430 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
7431 {
7432     return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
7433 }
7434 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK          0x07800000
7435 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT         23
7436 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
7437 {
7438     return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
7439 }
7440 #define A6XX_TEX_CONST_3_TILE_ALL               0x08000000
7441 #define A6XX_TEX_CONST_3_FLAG                   0x10000000
7442
7443 #define REG_A6XX_TEX_CONST_4                    0x00000004
7444 #define A6XX_TEX_CONST_4_BASE_LO__MASK              0xffffffe0
7445 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT             5
7446 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
7447 {
7448     return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
7449 }
7450
7451 #define REG_A6XX_TEX_CONST_5                    0x00000005
7452 #define A6XX_TEX_CONST_5_BASE_HI__MASK              0x0001ffff
7453 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT             0
7454 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
7455 {
7456     return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
7457 }
7458 #define A6XX_TEX_CONST_5_DEPTH__MASK                0x3ffe0000
7459 #define A6XX_TEX_CONST_5_DEPTH__SHIFT               17
7460 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
7461 {
7462     return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
7463 }
7464
7465 #define REG_A6XX_TEX_CONST_6                    0x00000006
7466 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK          0xffffff00
7467 #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT         8
7468 static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
7469 {
7470     return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
7471 }
7472
7473 #define REG_A6XX_TEX_CONST_7                    0x00000007
7474 #define A6XX_TEX_CONST_7_FLAG_LO__MASK              0xffffffe0
7475 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT             5
7476 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
7477 {
7478     return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
7479 }
7480
7481 #define REG_A6XX_TEX_CONST_8                    0x00000008
7482 #define A6XX_TEX_CONST_8_FLAG_HI__MASK              0x0001ffff
7483 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT             0
7484 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
7485 {
7486     return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
7487 }
7488
7489 #define REG_A6XX_TEX_CONST_9                    0x00000009
7490 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK      0x0001ffff
7491 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT     0
7492 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7493 {
7494     return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7495 }
7496
7497 #define REG_A6XX_TEX_CONST_10                   0x0000000a
7498 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK       0x0000007f
7499 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT      0
7500 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
7501 {
7502     return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
7503 }
7504 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK        0x00000f00
7505 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT       8
7506 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
7507 {
7508     return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
7509 }
7510 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK        0x0000f000
7511 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT       12
7512 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
7513 {
7514     return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
7515 }
7516
7517 #define REG_A6XX_TEX_CONST_11                   0x0000000b
7518
7519 #define REG_A6XX_TEX_CONST_12                   0x0000000c
7520
7521 #define REG_A6XX_TEX_CONST_13                   0x0000000d
7522
7523 #define REG_A6XX_TEX_CONST_14                   0x0000000e
7524
7525 #define REG_A6XX_TEX_CONST_15                   0x0000000f
7526
7527 #define REG_A6XX_UBO_0                      0x00000000
7528 #define A6XX_UBO_0_BASE_LO__MASK                0xffffffff
7529 #define A6XX_UBO_0_BASE_LO__SHIFT               0
7530 static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
7531 {
7532     return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
7533 }
7534
7535 #define REG_A6XX_UBO_1                      0x00000001
7536 #define A6XX_UBO_1_BASE_HI__MASK                0x0001ffff
7537 #define A6XX_UBO_1_BASE_HI__SHIFT               0
7538 static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
7539 {
7540     return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
7541 }
7542 #define A6XX_UBO_1_SIZE__MASK                   0xfffe0000
7543 #define A6XX_UBO_1_SIZE__SHIFT                  17
7544 static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
7545 {
7546     return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
7547 }
7548
7549 #define REG_A6XX_PDC_GPU_ENABLE_PDC             0x00001140
7550
7551 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR             0x00001148
7552
7553 #define REG_A6XX_PDC_GPU_TCS0_CONTROL               0x00001540
7554
7555 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK           0x00001541
7556
7557 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK        0x00001542
7558
7559 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID            0x00001543
7560
7561 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR             0x00001544
7562
7563 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA             0x00001545
7564
7565 #define REG_A6XX_PDC_GPU_TCS1_CONTROL               0x00001572
7566
7567 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK           0x00001573
7568
7569 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK        0x00001574
7570
7571 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID            0x00001575
7572
7573 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR             0x00001576
7574
7575 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA             0x00001577
7576
7577 #define REG_A6XX_PDC_GPU_TCS2_CONTROL               0x000015a4
7578
7579 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK           0x000015a5
7580
7581 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK        0x000015a6
7582
7583 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID            0x000015a7
7584
7585 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR             0x000015a8
7586
7587 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA             0x000015a9
7588
7589 #define REG_A6XX_PDC_GPU_TCS3_CONTROL               0x000015d6
7590
7591 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK           0x000015d7
7592
7593 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK        0x000015d8
7594
7595 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID            0x000015d9
7596
7597 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR             0x000015da
7598
7599 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA             0x000015db
7600
7601 #define REG_A6XX_PDC_GPU_SEQ_MEM_0              0x00000000
7602
7603 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A           0x00000000
7604 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK      0x000000ff
7605 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT     0
7606 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
7607 {
7608     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
7609 }
7610 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK    0x0000ff00
7611 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT   8
7612 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
7613 {
7614     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
7615 }
7616
7617 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B           0x00000001
7618
7619 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C           0x00000002
7620
7621 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D           0x00000003
7622
7623 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT           0x00000004
7624 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK     0x0000003f
7625 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT        0
7626 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
7627 {
7628     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
7629 }
7630 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK       0x00007000
7631 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT      12
7632 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
7633 {
7634     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
7635 }
7636 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK        0xf0000000
7637 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT       28
7638 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
7639 {
7640     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
7641 }
7642
7643 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM           0x00000005
7644 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK      0x0f000000
7645 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT     24
7646 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
7647 {
7648     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
7649 }
7650
7651 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0          0x00000008
7652
7653 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1          0x00000009
7654
7655 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2          0x0000000a
7656
7657 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3          0x0000000b
7658
7659 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0         0x0000000c
7660
7661 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1         0x0000000d
7662
7663 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2         0x0000000e
7664
7665 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3         0x0000000f
7666
7667 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0         0x00000010
7668 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK        0x0000000f
7669 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT       0
7670 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
7671 {
7672     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
7673 }
7674 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK        0x000000f0
7675 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT       4
7676 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
7677 {
7678     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
7679 }
7680 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK        0x00000f00
7681 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT       8
7682 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
7683 {
7684     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
7685 }
7686 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK        0x0000f000
7687 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT       12
7688 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
7689 {
7690     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
7691 }
7692 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK        0x000f0000
7693 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT       16
7694 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
7695 {
7696     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
7697 }
7698 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK        0x00f00000
7699 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT       20
7700 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
7701 {
7702     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
7703 }
7704 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK        0x0f000000
7705 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT       24
7706 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
7707 {
7708     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
7709 }
7710 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK        0xf0000000
7711 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT       28
7712 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
7713 {
7714     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
7715 }
7716
7717 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1         0x00000011
7718 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK        0x0000000f
7719 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT       0
7720 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
7721 {
7722     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
7723 }
7724 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK        0x000000f0
7725 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT       4
7726 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
7727 {
7728     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
7729 }
7730 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK       0x00000f00
7731 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT      8
7732 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
7733 {
7734     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
7735 }
7736 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK       0x0000f000
7737 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT      12
7738 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
7739 {
7740     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
7741 }
7742 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK       0x000f0000
7743 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT      16
7744 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
7745 {
7746     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
7747 }
7748 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK       0x00f00000
7749 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT      20
7750 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
7751 {
7752     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
7753 }
7754 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK       0x0f000000
7755 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT      24
7756 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
7757 {
7758     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
7759 }
7760 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK       0xf0000000
7761 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT      28
7762 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
7763 {
7764     return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
7765 }
7766
7767 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1          0x0000002f
7768
7769 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2          0x00000030
7770
7771 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0            0x00000001
7772
7773 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1            0x00000002
7774
7775
7776 #endif /* A6XX_XML */