msm/adreno/a5xx.xml.h

0001 #ifndef A5XX_XML
0002 #define A5XX_XML
0003
0004 /* Autogenerated file, DO NOT EDIT manually!
0005
0006 This file was generated by the rules-ng-ng headergen tool in this git repository:
0007 http://github.com/freedreno/envytools/
0008 git clone https://github.com/freedreno/envytools.git
0009
0010 The rules-ng-ng source files this header was generated from are:
0011 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-01-30 18:25:22)
0012 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2020-12-31 19:26:32)
0013 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-06-21 15:24:24)
0014 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14609 bytes, from 2021-11-24 23:05:10)
0015 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  69086 bytes, from 2022-03-03 16:41:33)
0016 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2021-11-24 23:05:10)
0017 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113358 bytes, from 2022-01-31 23:06:21)
0018 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149512 bytes, from 2022-01-31 23:06:21)
0019 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 184954 bytes, from 2022-03-03 16:41:33)
0020 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-07-22 15:21:56)
0021 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-01-30 18:25:22)
0022 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-07-22 15:21:56)
0023 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-07-22 15:21:56)
0024
0025 Copyright (C) 2013-2022 by the following authors:
0026 - Rob Clark <robdclark@gmail.com> (robclark)
0027 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
0028
0029 Permission is hereby granted, free of charge, to any person obtaining
0030 a copy of this software and associated documentation files (the
0031 "Software"), to deal in the Software without restriction, including
0032 without limitation the rights to use, copy, modify, merge, publish,
0033 distribute, sublicense, and/or sell copies of the Software, and to
0034 permit persons to whom the Software is furnished to do so, subject to
0035 the following conditions:
0036
0037 The above copyright notice and this permission notice (including the
0038 next paragraph) shall be included in all copies or substantial
0039 portions of the Software.
0040
0041 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0042 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0043 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0044 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0045 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0046 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0047 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0048 */
0049
0050
0051 enum a5xx_color_fmt {
0052     RB5_A8_UNORM = 2,
0053     RB5_R8_UNORM = 3,
0054     RB5_R8_SNORM = 4,
0055     RB5_R8_UINT = 5,
0056     RB5_R8_SINT = 6,
0057     RB5_R4G4B4A4_UNORM = 8,
0058     RB5_R5G5B5A1_UNORM = 10,
0059     RB5_R5G6B5_UNORM = 14,
0060     RB5_R8G8_UNORM = 15,
0061     RB5_R8G8_SNORM = 16,
0062     RB5_R8G8_UINT = 17,
0063     RB5_R8G8_SINT = 18,
0064     RB5_R16_UNORM = 21,
0065     RB5_R16_SNORM = 22,
0066     RB5_R16_FLOAT = 23,
0067     RB5_R16_UINT = 24,
0068     RB5_R16_SINT = 25,
0069     RB5_R8G8B8A8_UNORM = 48,
0070     RB5_R8G8B8_UNORM = 49,
0071     RB5_R8G8B8A8_SNORM = 50,
0072     RB5_R8G8B8A8_UINT = 51,
0073     RB5_R8G8B8A8_SINT = 52,
0074     RB5_R10G10B10A2_UNORM = 55,
0075     RB5_R10G10B10A2_UINT = 58,
0076     RB5_R11G11B10_FLOAT = 66,
0077     RB5_R16G16_UNORM = 67,
0078     RB5_R16G16_SNORM = 68,
0079     RB5_R16G16_FLOAT = 69,
0080     RB5_R16G16_UINT = 70,
0081     RB5_R16G16_SINT = 71,
0082     RB5_R32_FLOAT = 74,
0083     RB5_R32_UINT = 75,
0084     RB5_R32_SINT = 76,
0085     RB5_R16G16B16A16_UNORM = 96,
0086     RB5_R16G16B16A16_SNORM = 97,
0087     RB5_R16G16B16A16_FLOAT = 98,
0088     RB5_R16G16B16A16_UINT = 99,
0089     RB5_R16G16B16A16_SINT = 100,
0090     RB5_R32G32_FLOAT = 103,
0091     RB5_R32G32_UINT = 104,
0092     RB5_R32G32_SINT = 105,
0093     RB5_R32G32B32A32_FLOAT = 130,
0094     RB5_R32G32B32A32_UINT = 131,
0095     RB5_R32G32B32A32_SINT = 132,
0096     RB5_NONE = 255,
0097 };
0098
0099 enum a5xx_tile_mode {
0100     TILE5_LINEAR = 0,
0101     TILE5_2 = 2,
0102     TILE5_3 = 3,
0103 };
0104
0105 enum a5xx_vtx_fmt {
0106     VFMT5_8_UNORM = 3,
0107     VFMT5_8_SNORM = 4,
0108     VFMT5_8_UINT = 5,
0109     VFMT5_8_SINT = 6,
0110     VFMT5_8_8_UNORM = 15,
0111     VFMT5_8_8_SNORM = 16,
0112     VFMT5_8_8_UINT = 17,
0113     VFMT5_8_8_SINT = 18,
0114     VFMT5_16_UNORM = 21,
0115     VFMT5_16_SNORM = 22,
0116     VFMT5_16_FLOAT = 23,
0117     VFMT5_16_UINT = 24,
0118     VFMT5_16_SINT = 25,
0119     VFMT5_8_8_8_UNORM = 33,
0120     VFMT5_8_8_8_SNORM = 34,
0121     VFMT5_8_8_8_UINT = 35,
0122     VFMT5_8_8_8_SINT = 36,
0123     VFMT5_8_8_8_8_UNORM = 48,
0124     VFMT5_8_8_8_8_SNORM = 50,
0125     VFMT5_8_8_8_8_UINT = 51,
0126     VFMT5_8_8_8_8_SINT = 52,
0127     VFMT5_10_10_10_2_UNORM = 54,
0128     VFMT5_10_10_10_2_SNORM = 57,
0129     VFMT5_10_10_10_2_UINT = 58,
0130     VFMT5_10_10_10_2_SINT = 59,
0131     VFMT5_11_11_10_FLOAT = 66,
0132     VFMT5_16_16_UNORM = 67,
0133     VFMT5_16_16_SNORM = 68,
0134     VFMT5_16_16_FLOAT = 69,
0135     VFMT5_16_16_UINT = 70,
0136     VFMT5_16_16_SINT = 71,
0137     VFMT5_32_UNORM = 72,
0138     VFMT5_32_SNORM = 73,
0139     VFMT5_32_FLOAT = 74,
0140     VFMT5_32_UINT = 75,
0141     VFMT5_32_SINT = 76,
0142     VFMT5_32_FIXED = 77,
0143     VFMT5_16_16_16_UNORM = 88,
0144     VFMT5_16_16_16_SNORM = 89,
0145     VFMT5_16_16_16_FLOAT = 90,
0146     VFMT5_16_16_16_UINT = 91,
0147     VFMT5_16_16_16_SINT = 92,
0148     VFMT5_16_16_16_16_UNORM = 96,
0149     VFMT5_16_16_16_16_SNORM = 97,
0150     VFMT5_16_16_16_16_FLOAT = 98,
0151     VFMT5_16_16_16_16_UINT = 99,
0152     VFMT5_16_16_16_16_SINT = 100,
0153     VFMT5_32_32_UNORM = 101,
0154     VFMT5_32_32_SNORM = 102,
0155     VFMT5_32_32_FLOAT = 103,
0156     VFMT5_32_32_UINT = 104,
0157     VFMT5_32_32_SINT = 105,
0158     VFMT5_32_32_FIXED = 106,
0159     VFMT5_32_32_32_UNORM = 112,
0160     VFMT5_32_32_32_SNORM = 113,
0161     VFMT5_32_32_32_UINT = 114,
0162     VFMT5_32_32_32_SINT = 115,
0163     VFMT5_32_32_32_FLOAT = 116,
0164     VFMT5_32_32_32_FIXED = 117,
0165     VFMT5_32_32_32_32_UNORM = 128,
0166     VFMT5_32_32_32_32_SNORM = 129,
0167     VFMT5_32_32_32_32_FLOAT = 130,
0168     VFMT5_32_32_32_32_UINT = 131,
0169     VFMT5_32_32_32_32_SINT = 132,
0170     VFMT5_32_32_32_32_FIXED = 133,
0171     VFMT5_NONE = 255,
0172 };
0173
0174 enum a5xx_tex_fmt {
0175     TFMT5_A8_UNORM = 2,
0176     TFMT5_8_UNORM = 3,
0177     TFMT5_8_SNORM = 4,
0178     TFMT5_8_UINT = 5,
0179     TFMT5_8_SINT = 6,
0180     TFMT5_4_4_4_4_UNORM = 8,
0181     TFMT5_5_5_5_1_UNORM = 10,
0182     TFMT5_5_6_5_UNORM = 14,
0183     TFMT5_8_8_UNORM = 15,
0184     TFMT5_8_8_SNORM = 16,
0185     TFMT5_8_8_UINT = 17,
0186     TFMT5_8_8_SINT = 18,
0187     TFMT5_L8_A8_UNORM = 19,
0188     TFMT5_16_UNORM = 21,
0189     TFMT5_16_SNORM = 22,
0190     TFMT5_16_FLOAT = 23,
0191     TFMT5_16_UINT = 24,
0192     TFMT5_16_SINT = 25,
0193     TFMT5_8_8_8_8_UNORM = 48,
0194     TFMT5_8_8_8_UNORM = 49,
0195     TFMT5_8_8_8_8_SNORM = 50,
0196     TFMT5_8_8_8_8_UINT = 51,
0197     TFMT5_8_8_8_8_SINT = 52,
0198     TFMT5_9_9_9_E5_FLOAT = 53,
0199     TFMT5_10_10_10_2_UNORM = 54,
0200     TFMT5_10_10_10_2_UINT = 58,
0201     TFMT5_11_11_10_FLOAT = 66,
0202     TFMT5_16_16_UNORM = 67,
0203     TFMT5_16_16_SNORM = 68,
0204     TFMT5_16_16_FLOAT = 69,
0205     TFMT5_16_16_UINT = 70,
0206     TFMT5_16_16_SINT = 71,
0207     TFMT5_32_FLOAT = 74,
0208     TFMT5_32_UINT = 75,
0209     TFMT5_32_SINT = 76,
0210     TFMT5_16_16_16_16_UNORM = 96,
0211     TFMT5_16_16_16_16_SNORM = 97,
0212     TFMT5_16_16_16_16_FLOAT = 98,
0213     TFMT5_16_16_16_16_UINT = 99,
0214     TFMT5_16_16_16_16_SINT = 100,
0215     TFMT5_32_32_FLOAT = 103,
0216     TFMT5_32_32_UINT = 104,
0217     TFMT5_32_32_SINT = 105,
0218     TFMT5_32_32_32_UINT = 114,
0219     TFMT5_32_32_32_SINT = 115,
0220     TFMT5_32_32_32_FLOAT = 116,
0221     TFMT5_32_32_32_32_FLOAT = 130,
0222     TFMT5_32_32_32_32_UINT = 131,
0223     TFMT5_32_32_32_32_SINT = 132,
0224     TFMT5_X8Z24_UNORM = 160,
0225     TFMT5_ETC2_RG11_UNORM = 171,
0226     TFMT5_ETC2_RG11_SNORM = 172,
0227     TFMT5_ETC2_R11_UNORM = 173,
0228     TFMT5_ETC2_R11_SNORM = 174,
0229     TFMT5_ETC1 = 175,
0230     TFMT5_ETC2_RGB8 = 176,
0231     TFMT5_ETC2_RGBA8 = 177,
0232     TFMT5_ETC2_RGB8A1 = 178,
0233     TFMT5_DXT1 = 179,
0234     TFMT5_DXT3 = 180,
0235     TFMT5_DXT5 = 181,
0236     TFMT5_RGTC1_UNORM = 183,
0237     TFMT5_RGTC1_SNORM = 184,
0238     TFMT5_RGTC2_UNORM = 187,
0239     TFMT5_RGTC2_SNORM = 188,
0240     TFMT5_BPTC_UFLOAT = 190,
0241     TFMT5_BPTC_FLOAT = 191,
0242     TFMT5_BPTC = 192,
0243     TFMT5_ASTC_4x4 = 193,
0244     TFMT5_ASTC_5x4 = 194,
0245     TFMT5_ASTC_5x5 = 195,
0246     TFMT5_ASTC_6x5 = 196,
0247     TFMT5_ASTC_6x6 = 197,
0248     TFMT5_ASTC_8x5 = 198,
0249     TFMT5_ASTC_8x6 = 199,
0250     TFMT5_ASTC_8x8 = 200,
0251     TFMT5_ASTC_10x5 = 201,
0252     TFMT5_ASTC_10x6 = 202,
0253     TFMT5_ASTC_10x8 = 203,
0254     TFMT5_ASTC_10x10 = 204,
0255     TFMT5_ASTC_12x10 = 205,
0256     TFMT5_ASTC_12x12 = 206,
0257     TFMT5_NONE = 255,
0258 };
0259
0260 enum a5xx_depth_format {
0261     DEPTH5_NONE = 0,
0262     DEPTH5_16 = 1,
0263     DEPTH5_24_8 = 2,
0264     DEPTH5_32 = 4,
0265 };
0266
0267 enum a5xx_blit_buf {
0268     BLIT_MRT0 = 0,
0269     BLIT_MRT1 = 1,
0270     BLIT_MRT2 = 2,
0271     BLIT_MRT3 = 3,
0272     BLIT_MRT4 = 4,
0273     BLIT_MRT5 = 5,
0274     BLIT_MRT6 = 6,
0275     BLIT_MRT7 = 7,
0276     BLIT_ZS = 8,
0277     BLIT_S = 9,
0278 };
0279
0280 enum a5xx_cp_perfcounter_select {
0281     PERF_CP_ALWAYS_COUNT = 0,
0282     PERF_CP_BUSY_GFX_CORE_IDLE = 1,
0283     PERF_CP_BUSY_CYCLES = 2,
0284     PERF_CP_PFP_IDLE = 3,
0285     PERF_CP_PFP_BUSY_WORKING = 4,
0286     PERF_CP_PFP_STALL_CYCLES_ANY = 5,
0287     PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
0288     PERF_CP_PFP_ICACHE_MISS = 7,
0289     PERF_CP_PFP_ICACHE_HIT = 8,
0290     PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
0291     PERF_CP_ME_BUSY_WORKING = 10,
0292     PERF_CP_ME_IDLE = 11,
0293     PERF_CP_ME_STARVE_CYCLES_ANY = 12,
0294     PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
0295     PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
0296     PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
0297     PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
0298     PERF_CP_ME_STALL_CYCLES_ANY = 17,
0299     PERF_CP_ME_ICACHE_MISS = 18,
0300     PERF_CP_ME_ICACHE_HIT = 19,
0301     PERF_CP_NUM_PREEMPTIONS = 20,
0302     PERF_CP_PREEMPTION_REACTION_DELAY = 21,
0303     PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
0304     PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
0305     PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
0306     PERF_CP_PREDICATED_DRAWS_KILLED = 25,
0307     PERF_CP_MODE_SWITCH = 26,
0308     PERF_CP_ZPASS_DONE = 27,
0309     PERF_CP_CONTEXT_DONE = 28,
0310     PERF_CP_CACHE_FLUSH = 29,
0311     PERF_CP_LONG_PREEMPTIONS = 30,
0312 };
0313
0314 enum a5xx_rbbm_perfcounter_select {
0315     PERF_RBBM_ALWAYS_COUNT = 0,
0316     PERF_RBBM_ALWAYS_ON = 1,
0317     PERF_RBBM_TSE_BUSY = 2,
0318     PERF_RBBM_RAS_BUSY = 3,
0319     PERF_RBBM_PC_DCALL_BUSY = 4,
0320     PERF_RBBM_PC_VSD_BUSY = 5,
0321     PERF_RBBM_STATUS_MASKED = 6,
0322     PERF_RBBM_COM_BUSY = 7,
0323     PERF_RBBM_DCOM_BUSY = 8,
0324     PERF_RBBM_VBIF_BUSY = 9,
0325     PERF_RBBM_VSC_BUSY = 10,
0326     PERF_RBBM_TESS_BUSY = 11,
0327     PERF_RBBM_UCHE_BUSY = 12,
0328     PERF_RBBM_HLSQ_BUSY = 13,
0329 };
0330
0331 enum a5xx_pc_perfcounter_select {
0332     PERF_PC_BUSY_CYCLES = 0,
0333     PERF_PC_WORKING_CYCLES = 1,
0334     PERF_PC_STALL_CYCLES_VFD = 2,
0335     PERF_PC_STALL_CYCLES_TSE = 3,
0336     PERF_PC_STALL_CYCLES_VPC = 4,
0337     PERF_PC_STALL_CYCLES_UCHE = 5,
0338     PERF_PC_STALL_CYCLES_TESS = 6,
0339     PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
0340     PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
0341     PERF_PC_PASS1_TF_STALL_CYCLES = 9,
0342     PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
0343     PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
0344     PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
0345     PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
0346     PERF_PC_STARVE_CYCLES_DI = 14,
0347     PERF_PC_VIS_STREAMS_LOADED = 15,
0348     PERF_PC_INSTANCES = 16,
0349     PERF_PC_VPC_PRIMITIVES = 17,
0350     PERF_PC_DEAD_PRIM = 18,
0351     PERF_PC_LIVE_PRIM = 19,
0352     PERF_PC_VERTEX_HITS = 20,
0353     PERF_PC_IA_VERTICES = 21,
0354     PERF_PC_IA_PRIMITIVES = 22,
0355     PERF_PC_GS_PRIMITIVES = 23,
0356     PERF_PC_HS_INVOCATIONS = 24,
0357     PERF_PC_DS_INVOCATIONS = 25,
0358     PERF_PC_VS_INVOCATIONS = 26,
0359     PERF_PC_GS_INVOCATIONS = 27,
0360     PERF_PC_DS_PRIMITIVES = 28,
0361     PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
0362     PERF_PC_3D_DRAWCALLS = 30,
0363     PERF_PC_2D_DRAWCALLS = 31,
0364     PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
0365     PERF_TESS_BUSY_CYCLES = 33,
0366     PERF_TESS_WORKING_CYCLES = 34,
0367     PERF_TESS_STALL_CYCLES_PC = 35,
0368     PERF_TESS_STARVE_CYCLES_PC = 36,
0369 };
0370
0371 enum a5xx_vfd_perfcounter_select {
0372     PERF_VFD_BUSY_CYCLES = 0,
0373     PERF_VFD_STALL_CYCLES_UCHE = 1,
0374     PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
0375     PERF_VFD_STALL_CYCLES_MISS_VB = 3,
0376     PERF_VFD_STALL_CYCLES_MISS_Q = 4,
0377     PERF_VFD_STALL_CYCLES_SP_INFO = 5,
0378     PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
0379     PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
0380     PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
0381     PERF_VFD_DECODER_PACKER_STALL = 9,
0382     PERF_VFD_STARVE_CYCLES_UCHE = 10,
0383     PERF_VFD_RBUFFER_FULL = 11,
0384     PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
0385     PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
0386     PERF_VFD_NUM_ATTRIBUTES = 14,
0387     PERF_VFD_INSTRUCTIONS = 15,
0388     PERF_VFD_UPPER_SHADER_FIBERS = 16,
0389     PERF_VFD_LOWER_SHADER_FIBERS = 17,
0390     PERF_VFD_MODE_0_FIBERS = 18,
0391     PERF_VFD_MODE_1_FIBERS = 19,
0392     PERF_VFD_MODE_2_FIBERS = 20,
0393     PERF_VFD_MODE_3_FIBERS = 21,
0394     PERF_VFD_MODE_4_FIBERS = 22,
0395     PERF_VFD_TOTAL_VERTICES = 23,
0396     PERF_VFD_NUM_ATTR_MISS = 24,
0397     PERF_VFD_1_BURST_REQ = 25,
0398     PERF_VFDP_STALL_CYCLES_VFD = 26,
0399     PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
0400     PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
0401     PERF_VFDP_STARVE_CYCLES_PC = 29,
0402     PERF_VFDP_VS_STAGE_32_WAVES = 30,
0403 };
0404
0405 enum a5xx_hlsq_perfcounter_select {
0406     PERF_HLSQ_BUSY_CYCLES = 0,
0407     PERF_HLSQ_STALL_CYCLES_UCHE = 1,
0408     PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
0409     PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
0410     PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
0411     PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
0412     PERF_HLSQ_FS_STAGE_32_WAVES = 6,
0413     PERF_HLSQ_FS_STAGE_64_WAVES = 7,
0414     PERF_HLSQ_QUADS = 8,
0415     PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
0416     PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
0417     PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
0418     PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
0419     PERF_HLSQ_CS_INVOCATIONS = 13,
0420     PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
0421 };
0422
0423 enum a5xx_vpc_perfcounter_select {
0424     PERF_VPC_BUSY_CYCLES = 0,
0425     PERF_VPC_WORKING_CYCLES = 1,
0426     PERF_VPC_STALL_CYCLES_UCHE = 2,
0427     PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
0428     PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
0429     PERF_VPC_STALL_CYCLES_PC = 5,
0430     PERF_VPC_STALL_CYCLES_SP_LM = 6,
0431     PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
0432     PERF_VPC_STARVE_CYCLES_SP = 8,
0433     PERF_VPC_STARVE_CYCLES_LRZ = 9,
0434     PERF_VPC_PC_PRIMITIVES = 10,
0435     PERF_VPC_SP_COMPONENTS = 11,
0436     PERF_VPC_SP_LM_PRIMITIVES = 12,
0437     PERF_VPC_SP_LM_COMPONENTS = 13,
0438     PERF_VPC_SP_LM_DWORDS = 14,
0439     PERF_VPC_STREAMOUT_COMPONENTS = 15,
0440     PERF_VPC_GRANT_PHASES = 16,
0441 };
0442
0443 enum a5xx_tse_perfcounter_select {
0444     PERF_TSE_BUSY_CYCLES = 0,
0445     PERF_TSE_CLIPPING_CYCLES = 1,
0446     PERF_TSE_STALL_CYCLES_RAS = 2,
0447     PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
0448     PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
0449     PERF_TSE_STARVE_CYCLES_PC = 5,
0450     PERF_TSE_INPUT_PRIM = 6,
0451     PERF_TSE_INPUT_NULL_PRIM = 7,
0452     PERF_TSE_TRIVAL_REJ_PRIM = 8,
0453     PERF_TSE_CLIPPED_PRIM = 9,
0454     PERF_TSE_ZERO_AREA_PRIM = 10,
0455     PERF_TSE_FACENESS_CULLED_PRIM = 11,
0456     PERF_TSE_ZERO_PIXEL_PRIM = 12,
0457     PERF_TSE_OUTPUT_NULL_PRIM = 13,
0458     PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
0459     PERF_TSE_CINVOCATION = 15,
0460     PERF_TSE_CPRIMITIVES = 16,
0461     PERF_TSE_2D_INPUT_PRIM = 17,
0462     PERF_TSE_2D_ALIVE_CLCLES = 18,
0463 };
0464
0465 enum a5xx_ras_perfcounter_select {
0466     PERF_RAS_BUSY_CYCLES = 0,
0467     PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
0468     PERF_RAS_STALL_CYCLES_LRZ = 2,
0469     PERF_RAS_STARVE_CYCLES_TSE = 3,
0470     PERF_RAS_SUPER_TILES = 4,
0471     PERF_RAS_8X4_TILES = 5,
0472     PERF_RAS_MASKGEN_ACTIVE = 6,
0473     PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
0474     PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
0475     PERF_RAS_PRIM_KILLED_INVISILBE = 9,
0476 };
0477
0478 enum a5xx_lrz_perfcounter_select {
0479     PERF_LRZ_BUSY_CYCLES = 0,
0480     PERF_LRZ_STARVE_CYCLES_RAS = 1,
0481     PERF_LRZ_STALL_CYCLES_RB = 2,
0482     PERF_LRZ_STALL_CYCLES_VSC = 3,
0483     PERF_LRZ_STALL_CYCLES_VPC = 4,
0484     PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
0485     PERF_LRZ_STALL_CYCLES_UCHE = 6,
0486     PERF_LRZ_LRZ_READ = 7,
0487     PERF_LRZ_LRZ_WRITE = 8,
0488     PERF_LRZ_READ_LATENCY = 9,
0489     PERF_LRZ_MERGE_CACHE_UPDATING = 10,
0490     PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
0491     PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
0492     PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
0493     PERF_LRZ_FULL_8X8_TILES = 14,
0494     PERF_LRZ_PARTIAL_8X8_TILES = 15,
0495     PERF_LRZ_TILE_KILLED = 16,
0496     PERF_LRZ_TOTAL_PIXEL = 17,
0497     PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
0498 };
0499
0500 enum a5xx_uche_perfcounter_select {
0501     PERF_UCHE_BUSY_CYCLES = 0,
0502     PERF_UCHE_STALL_CYCLES_VBIF = 1,
0503     PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
0504     PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
0505     PERF_UCHE_VBIF_READ_BEATS_TP = 4,
0506     PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
0507     PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
0508     PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
0509     PERF_UCHE_VBIF_READ_BEATS_SP = 8,
0510     PERF_UCHE_READ_REQUESTS_TP = 9,
0511     PERF_UCHE_READ_REQUESTS_VFD = 10,
0512     PERF_UCHE_READ_REQUESTS_HLSQ = 11,
0513     PERF_UCHE_READ_REQUESTS_LRZ = 12,
0514     PERF_UCHE_READ_REQUESTS_SP = 13,
0515     PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
0516     PERF_UCHE_WRITE_REQUESTS_SP = 15,
0517     PERF_UCHE_WRITE_REQUESTS_VPC = 16,
0518     PERF_UCHE_WRITE_REQUESTS_VSC = 17,
0519     PERF_UCHE_EVICTS = 18,
0520     PERF_UCHE_BANK_REQ0 = 19,
0521     PERF_UCHE_BANK_REQ1 = 20,
0522     PERF_UCHE_BANK_REQ2 = 21,
0523     PERF_UCHE_BANK_REQ3 = 22,
0524     PERF_UCHE_BANK_REQ4 = 23,
0525     PERF_UCHE_BANK_REQ5 = 24,
0526     PERF_UCHE_BANK_REQ6 = 25,
0527     PERF_UCHE_BANK_REQ7 = 26,
0528     PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
0529     PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
0530     PERF_UCHE_GMEM_READ_BEATS = 29,
0531     PERF_UCHE_FLAG_COUNT = 30,
0532 };
0533
0534 enum a5xx_tp_perfcounter_select {
0535     PERF_TP_BUSY_CYCLES = 0,
0536     PERF_TP_STALL_CYCLES_UCHE = 1,
0537     PERF_TP_LATENCY_CYCLES = 2,
0538     PERF_TP_LATENCY_TRANS = 3,
0539     PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
0540     PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
0541     PERF_TP_L1_CACHELINE_REQUESTS = 6,
0542     PERF_TP_L1_CACHELINE_MISSES = 7,
0543     PERF_TP_SP_TP_TRANS = 8,
0544     PERF_TP_TP_SP_TRANS = 9,
0545     PERF_TP_OUTPUT_PIXELS = 10,
0546     PERF_TP_FILTER_WORKLOAD_16BIT = 11,
0547     PERF_TP_FILTER_WORKLOAD_32BIT = 12,
0548     PERF_TP_QUADS_RECEIVED = 13,
0549     PERF_TP_QUADS_OFFSET = 14,
0550     PERF_TP_QUADS_SHADOW = 15,
0551     PERF_TP_QUADS_ARRAY = 16,
0552     PERF_TP_QUADS_GRADIENT = 17,
0553     PERF_TP_QUADS_1D = 18,
0554     PERF_TP_QUADS_2D = 19,
0555     PERF_TP_QUADS_BUFFER = 20,
0556     PERF_TP_QUADS_3D = 21,
0557     PERF_TP_QUADS_CUBE = 22,
0558     PERF_TP_STATE_CACHE_REQUESTS = 23,
0559     PERF_TP_STATE_CACHE_MISSES = 24,
0560     PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
0561     PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
0562     PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
0563     PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
0564     PERF_TP_OUTPUT_PIXELS_POINT = 29,
0565     PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
0566     PERF_TP_OUTPUT_PIXELS_MIP = 31,
0567     PERF_TP_OUTPUT_PIXELS_ANISO = 32,
0568     PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
0569     PERF_TP_FLAG_CACHE_REQUESTS = 34,
0570     PERF_TP_FLAG_CACHE_MISSES = 35,
0571     PERF_TP_L1_5_L2_REQUESTS = 36,
0572     PERF_TP_2D_OUTPUT_PIXELS = 37,
0573     PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
0574     PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
0575     PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
0576     PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
0577 };
0578
0579 enum a5xx_sp_perfcounter_select {
0580     PERF_SP_BUSY_CYCLES = 0,
0581     PERF_SP_ALU_WORKING_CYCLES = 1,
0582     PERF_SP_EFU_WORKING_CYCLES = 2,
0583     PERF_SP_STALL_CYCLES_VPC = 3,
0584     PERF_SP_STALL_CYCLES_TP = 4,
0585     PERF_SP_STALL_CYCLES_UCHE = 5,
0586     PERF_SP_STALL_CYCLES_RB = 6,
0587     PERF_SP_SCHEDULER_NON_WORKING = 7,
0588     PERF_SP_WAVE_CONTEXTS = 8,
0589     PERF_SP_WAVE_CONTEXT_CYCLES = 9,
0590     PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
0591     PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
0592     PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
0593     PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
0594     PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
0595     PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
0596     PERF_SP_WAVE_CTRL_CYCLES = 16,
0597     PERF_SP_WAVE_LOAD_CYCLES = 17,
0598     PERF_SP_WAVE_EMIT_CYCLES = 18,
0599     PERF_SP_WAVE_NOP_CYCLES = 19,
0600     PERF_SP_WAVE_WAIT_CYCLES = 20,
0601     PERF_SP_WAVE_FETCH_CYCLES = 21,
0602     PERF_SP_WAVE_IDLE_CYCLES = 22,
0603     PERF_SP_WAVE_END_CYCLES = 23,
0604     PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
0605     PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
0606     PERF_SP_WAVE_JOIN_CYCLES = 26,
0607     PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
0608     PERF_SP_LM_STORE_INSTRUCTIONS = 28,
0609     PERF_SP_LM_ATOMICS = 29,
0610     PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
0611     PERF_SP_GM_STORE_INSTRUCTIONS = 31,
0612     PERF_SP_GM_ATOMICS = 32,
0613     PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
0614     PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
0615     PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
0616     PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
0617     PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
0618     PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
0619     PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
0620     PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
0621     PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
0622     PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
0623     PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
0624     PERF_SP_VS_INSTRUCTIONS = 44,
0625     PERF_SP_FS_INSTRUCTIONS = 45,
0626     PERF_SP_ADDR_LOCK_COUNT = 46,
0627     PERF_SP_UCHE_READ_TRANS = 47,
0628     PERF_SP_UCHE_WRITE_TRANS = 48,
0629     PERF_SP_EXPORT_VPC_TRANS = 49,
0630     PERF_SP_EXPORT_RB_TRANS = 50,
0631     PERF_SP_PIXELS_KILLED = 51,
0632     PERF_SP_ICL1_REQUESTS = 52,
0633     PERF_SP_ICL1_MISSES = 53,
0634     PERF_SP_ICL0_REQUESTS = 54,
0635     PERF_SP_ICL0_MISSES = 55,
0636     PERF_SP_HS_INSTRUCTIONS = 56,
0637     PERF_SP_DS_INSTRUCTIONS = 57,
0638     PERF_SP_GS_INSTRUCTIONS = 58,
0639     PERF_SP_CS_INSTRUCTIONS = 59,
0640     PERF_SP_GPR_READ = 60,
0641     PERF_SP_GPR_WRITE = 61,
0642     PERF_SP_LM_CH0_REQUESTS = 62,
0643     PERF_SP_LM_CH1_REQUESTS = 63,
0644     PERF_SP_LM_BANK_CONFLICTS = 64,
0645 };
0646
0647 enum a5xx_rb_perfcounter_select {
0648     PERF_RB_BUSY_CYCLES = 0,
0649     PERF_RB_STALL_CYCLES_CCU = 1,
0650     PERF_RB_STALL_CYCLES_HLSQ = 2,
0651     PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
0652     PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
0653     PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
0654     PERF_RB_STARVE_CYCLES_SP = 6,
0655     PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
0656     PERF_RB_STARVE_CYCLES_CCU = 8,
0657     PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
0658     PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
0659     PERF_RB_Z_WORKLOAD = 11,
0660     PERF_RB_HLSQ_ACTIVE = 12,
0661     PERF_RB_Z_READ = 13,
0662     PERF_RB_Z_WRITE = 14,
0663     PERF_RB_C_READ = 15,
0664     PERF_RB_C_WRITE = 16,
0665     PERF_RB_TOTAL_PASS = 17,
0666     PERF_RB_Z_PASS = 18,
0667     PERF_RB_Z_FAIL = 19,
0668     PERF_RB_S_FAIL = 20,
0669     PERF_RB_BLENDED_FXP_COMPONENTS = 21,
0670     PERF_RB_BLENDED_FP16_COMPONENTS = 22,
0671     RB_RESERVED = 23,
0672     PERF_RB_2D_ALIVE_CYCLES = 24,
0673     PERF_RB_2D_STALL_CYCLES_A2D = 25,
0674     PERF_RB_2D_STARVE_CYCLES_SRC = 26,
0675     PERF_RB_2D_STARVE_CYCLES_SP = 27,
0676     PERF_RB_2D_STARVE_CYCLES_DST = 28,
0677     PERF_RB_2D_VALID_PIXELS = 29,
0678 };
0679
0680 enum a5xx_rb_samples_perfcounter_select {
0681     TOTAL_SAMPLES = 0,
0682     ZPASS_SAMPLES = 1,
0683     ZFAIL_SAMPLES = 2,
0684     SFAIL_SAMPLES = 3,
0685 };
0686
0687 enum a5xx_vsc_perfcounter_select {
0688     PERF_VSC_BUSY_CYCLES = 0,
0689     PERF_VSC_WORKING_CYCLES = 1,
0690     PERF_VSC_STALL_CYCLES_UCHE = 2,
0691     PERF_VSC_EOT_NUM = 3,
0692 };
0693
0694 enum a5xx_ccu_perfcounter_select {
0695     PERF_CCU_BUSY_CYCLES = 0,
0696     PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
0697     PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
0698     PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
0699     PERF_CCU_DEPTH_BLOCKS = 4,
0700     PERF_CCU_COLOR_BLOCKS = 5,
0701     PERF_CCU_DEPTH_BLOCK_HIT = 6,
0702     PERF_CCU_COLOR_BLOCK_HIT = 7,
0703     PERF_CCU_PARTIAL_BLOCK_READ = 8,
0704     PERF_CCU_GMEM_READ = 9,
0705     PERF_CCU_GMEM_WRITE = 10,
0706     PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
0707     PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
0708     PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
0709     PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
0710     PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
0711     PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
0712     PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
0713     PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
0714     PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
0715     PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
0716     PERF_CCU_2D_BUSY_CYCLES = 21,
0717     PERF_CCU_2D_RD_REQ = 22,
0718     PERF_CCU_2D_WR_REQ = 23,
0719     PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
0720     PERF_CCU_2D_PIXELS = 25,
0721 };
0722
0723 enum a5xx_cmp_perfcounter_select {
0724     PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
0725     PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
0726     PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
0727     PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
0728     PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
0729     PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
0730     PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
0731     PERF_CMPDECMP_VBIF_READ_DATA = 7,
0732     PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
0733     PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
0734     PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
0735     PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
0736     PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
0737     PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
0738     PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
0739     PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
0740     PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
0741     PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
0742     PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
0743     PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
0744     PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
0745     PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
0746     PERF_CMPDECMP_2D_RD_DATA = 22,
0747     PERF_CMPDECMP_2D_WR_DATA = 23,
0748 };
0749
0750 enum a5xx_vbif_perfcounter_select {
0751     AXI_READ_REQUESTS_ID_0 = 0,
0752     AXI_READ_REQUESTS_ID_1 = 1,
0753     AXI_READ_REQUESTS_ID_2 = 2,
0754     AXI_READ_REQUESTS_ID_3 = 3,
0755     AXI_READ_REQUESTS_ID_4 = 4,
0756     AXI_READ_REQUESTS_ID_5 = 5,
0757     AXI_READ_REQUESTS_ID_6 = 6,
0758     AXI_READ_REQUESTS_ID_7 = 7,
0759     AXI_READ_REQUESTS_ID_8 = 8,
0760     AXI_READ_REQUESTS_ID_9 = 9,
0761     AXI_READ_REQUESTS_ID_10 = 10,
0762     AXI_READ_REQUESTS_ID_11 = 11,
0763     AXI_READ_REQUESTS_ID_12 = 12,
0764     AXI_READ_REQUESTS_ID_13 = 13,
0765     AXI_READ_REQUESTS_ID_14 = 14,
0766     AXI_READ_REQUESTS_ID_15 = 15,
0767     AXI0_READ_REQUESTS_TOTAL = 16,
0768     AXI1_READ_REQUESTS_TOTAL = 17,
0769     AXI2_READ_REQUESTS_TOTAL = 18,
0770     AXI3_READ_REQUESTS_TOTAL = 19,
0771     AXI_READ_REQUESTS_TOTAL = 20,
0772     AXI_WRITE_REQUESTS_ID_0 = 21,
0773     AXI_WRITE_REQUESTS_ID_1 = 22,
0774     AXI_WRITE_REQUESTS_ID_2 = 23,
0775     AXI_WRITE_REQUESTS_ID_3 = 24,
0776     AXI_WRITE_REQUESTS_ID_4 = 25,
0777     AXI_WRITE_REQUESTS_ID_5 = 26,
0778     AXI_WRITE_REQUESTS_ID_6 = 27,
0779     AXI_WRITE_REQUESTS_ID_7 = 28,
0780     AXI_WRITE_REQUESTS_ID_8 = 29,
0781     AXI_WRITE_REQUESTS_ID_9 = 30,
0782     AXI_WRITE_REQUESTS_ID_10 = 31,
0783     AXI_WRITE_REQUESTS_ID_11 = 32,
0784     AXI_WRITE_REQUESTS_ID_12 = 33,
0785     AXI_WRITE_REQUESTS_ID_13 = 34,
0786     AXI_WRITE_REQUESTS_ID_14 = 35,
0787     AXI_WRITE_REQUESTS_ID_15 = 36,
0788     AXI0_WRITE_REQUESTS_TOTAL = 37,
0789     AXI1_WRITE_REQUESTS_TOTAL = 38,
0790     AXI2_WRITE_REQUESTS_TOTAL = 39,
0791     AXI3_WRITE_REQUESTS_TOTAL = 40,
0792     AXI_WRITE_REQUESTS_TOTAL = 41,
0793     AXI_TOTAL_REQUESTS = 42,
0794     AXI_READ_DATA_BEATS_ID_0 = 43,
0795     AXI_READ_DATA_BEATS_ID_1 = 44,
0796     AXI_READ_DATA_BEATS_ID_2 = 45,
0797     AXI_READ_DATA_BEATS_ID_3 = 46,
0798     AXI_READ_DATA_BEATS_ID_4 = 47,
0799     AXI_READ_DATA_BEATS_ID_5 = 48,
0800     AXI_READ_DATA_BEATS_ID_6 = 49,
0801     AXI_READ_DATA_BEATS_ID_7 = 50,
0802     AXI_READ_DATA_BEATS_ID_8 = 51,
0803     AXI_READ_DATA_BEATS_ID_9 = 52,
0804     AXI_READ_DATA_BEATS_ID_10 = 53,
0805     AXI_READ_DATA_BEATS_ID_11 = 54,
0806     AXI_READ_DATA_BEATS_ID_12 = 55,
0807     AXI_READ_DATA_BEATS_ID_13 = 56,
0808     AXI_READ_DATA_BEATS_ID_14 = 57,
0809     AXI_READ_DATA_BEATS_ID_15 = 58,
0810     AXI0_READ_DATA_BEATS_TOTAL = 59,
0811     AXI1_READ_DATA_BEATS_TOTAL = 60,
0812     AXI2_READ_DATA_BEATS_TOTAL = 61,
0813     AXI3_READ_DATA_BEATS_TOTAL = 62,
0814     AXI_READ_DATA_BEATS_TOTAL = 63,
0815     AXI_WRITE_DATA_BEATS_ID_0 = 64,
0816     AXI_WRITE_DATA_BEATS_ID_1 = 65,
0817     AXI_WRITE_DATA_BEATS_ID_2 = 66,
0818     AXI_WRITE_DATA_BEATS_ID_3 = 67,
0819     AXI_WRITE_DATA_BEATS_ID_4 = 68,
0820     AXI_WRITE_DATA_BEATS_ID_5 = 69,
0821     AXI_WRITE_DATA_BEATS_ID_6 = 70,
0822     AXI_WRITE_DATA_BEATS_ID_7 = 71,
0823     AXI_WRITE_DATA_BEATS_ID_8 = 72,
0824     AXI_WRITE_DATA_BEATS_ID_9 = 73,
0825     AXI_WRITE_DATA_BEATS_ID_10 = 74,
0826     AXI_WRITE_DATA_BEATS_ID_11 = 75,
0827     AXI_WRITE_DATA_BEATS_ID_12 = 76,
0828     AXI_WRITE_DATA_BEATS_ID_13 = 77,
0829     AXI_WRITE_DATA_BEATS_ID_14 = 78,
0830     AXI_WRITE_DATA_BEATS_ID_15 = 79,
0831     AXI0_WRITE_DATA_BEATS_TOTAL = 80,
0832     AXI1_WRITE_DATA_BEATS_TOTAL = 81,
0833     AXI2_WRITE_DATA_BEATS_TOTAL = 82,
0834     AXI3_WRITE_DATA_BEATS_TOTAL = 83,
0835     AXI_WRITE_DATA_BEATS_TOTAL = 84,
0836     AXI_DATA_BEATS_TOTAL = 85,
0837 };
0838
0839 enum a5xx_tex_filter {
0840     A5XX_TEX_NEAREST = 0,
0841     A5XX_TEX_LINEAR = 1,
0842     A5XX_TEX_ANISO = 2,
0843 };
0844
0845 enum a5xx_tex_clamp {
0846     A5XX_TEX_REPEAT = 0,
0847     A5XX_TEX_CLAMP_TO_EDGE = 1,
0848     A5XX_TEX_MIRROR_REPEAT = 2,
0849     A5XX_TEX_CLAMP_TO_BORDER = 3,
0850     A5XX_TEX_MIRROR_CLAMP = 4,
0851 };
0852
0853 enum a5xx_tex_aniso {
0854     A5XX_TEX_ANISO_1 = 0,
0855     A5XX_TEX_ANISO_2 = 1,
0856     A5XX_TEX_ANISO_4 = 2,
0857     A5XX_TEX_ANISO_8 = 3,
0858     A5XX_TEX_ANISO_16 = 4,
0859 };
0860
0861 enum a5xx_tex_swiz {
0862     A5XX_TEX_X = 0,
0863     A5XX_TEX_Y = 1,
0864     A5XX_TEX_Z = 2,
0865     A5XX_TEX_W = 3,
0866     A5XX_TEX_ZERO = 4,
0867     A5XX_TEX_ONE = 5,
0868 };
0869
0870 enum a5xx_tex_type {
0871     A5XX_TEX_1D = 0,
0872     A5XX_TEX_2D = 1,
0873     A5XX_TEX_CUBE = 2,
0874     A5XX_TEX_3D = 3,
0875     A5XX_TEX_BUFFER = 4,
0876 };
0877
0878 #define A5XX_INT0_RBBM_GPU_IDLE                 0x00000001
0879 #define A5XX_INT0_RBBM_AHB_ERROR                0x00000002
0880 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT             0x00000004
0881 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT                0x00000008
0882 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT               0x00000010
0883 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT               0x00000020
0884 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW           0x00000040
0885 #define A5XX_INT0_RBBM_GPC_ERROR                0x00000080
0886 #define A5XX_INT0_CP_SW                     0x00000100
0887 #define A5XX_INT0_CP_HW_ERROR                   0x00000200
0888 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS             0x00000400
0889 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS             0x00000800
0890 #define A5XX_INT0_CP_CCU_RESOLVE_TS             0x00001000
0891 #define A5XX_INT0_CP_IB2                    0x00002000
0892 #define A5XX_INT0_CP_IB1                    0x00004000
0893 #define A5XX_INT0_CP_RB                     0x00008000
0894 #define A5XX_INT0_CP_UNUSED_1                   0x00010000
0895 #define A5XX_INT0_CP_RB_DONE_TS                 0x00020000
0896 #define A5XX_INT0_CP_WT_DONE_TS                 0x00040000
0897 #define A5XX_INT0_UNKNOWN_1                 0x00080000
0898 #define A5XX_INT0_CP_CACHE_FLUSH_TS             0x00100000
0899 #define A5XX_INT0_UNUSED_2                  0x00200000
0900 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW             0x00400000
0901 #define A5XX_INT0_MISC_HANG_DETECT              0x00800000
0902 #define A5XX_INT0_UCHE_OOB_ACCESS               0x01000000
0903 #define A5XX_INT0_UCHE_TRAP_INTR                0x02000000
0904 #define A5XX_INT0_DEBBUS_INTR_0                 0x04000000
0905 #define A5XX_INT0_DEBBUS_INTR_1                 0x08000000
0906 #define A5XX_INT0_GPMU_VOLTAGE_DROOP                0x10000000
0907 #define A5XX_INT0_GPMU_FIRMWARE                 0x20000000
0908 #define A5XX_INT0_ISDB_CPU_IRQ                  0x40000000
0909 #define A5XX_INT0_ISDB_UNDER_DEBUG              0x80000000
0910 #define A5XX_CP_INT_CP_OPCODE_ERROR             0x00000001
0911 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR           0x00000002
0912 #define A5XX_CP_INT_CP_HW_FAULT_ERROR               0x00000004
0913 #define A5XX_CP_INT_CP_DMA_ERROR                0x00000008
0914 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR        0x00000010
0915 #define A5XX_CP_INT_CP_AHB_ERROR                0x00000020
0916 #define REG_A5XX_CP_RB_BASE                 0x00000800
0917
0918 #define REG_A5XX_CP_RB_BASE_HI                  0x00000801
0919
0920 #define REG_A5XX_CP_RB_CNTL                 0x00000802
0921
0922 #define REG_A5XX_CP_RB_RPTR_ADDR                0x00000804
0923
0924 #define REG_A5XX_CP_RB_RPTR_ADDR_HI             0x00000805
0925
0926 #define REG_A5XX_CP_RB_RPTR                 0x00000806
0927
0928 #define REG_A5XX_CP_RB_WPTR                 0x00000807
0929
0930 #define REG_A5XX_CP_PFP_STAT_ADDR               0x00000808
0931
0932 #define REG_A5XX_CP_PFP_STAT_DATA               0x00000809
0933
0934 #define REG_A5XX_CP_DRAW_STATE_ADDR             0x0000080b
0935
0936 #define REG_A5XX_CP_DRAW_STATE_DATA             0x0000080c
0937
0938 #define REG_A5XX_CP_ME_NRT_ADDR_LO              0x0000080d
0939
0940 #define REG_A5XX_CP_ME_NRT_ADDR_HI              0x0000080e
0941
0942 #define REG_A5XX_CP_ME_NRT_DATA                 0x00000810
0943
0944 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO            0x00000817
0945
0946 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI            0x00000818
0947
0948 #define REG_A5XX_CP_CRASH_DUMP_CNTL             0x00000819
0949
0950 #define REG_A5XX_CP_ME_STAT_ADDR                0x0000081a
0951
0952 #define REG_A5XX_CP_ROQ_THRESHOLDS_1                0x0000081f
0953
0954 #define REG_A5XX_CP_ROQ_THRESHOLDS_2                0x00000820
0955
0956 #define REG_A5XX_CP_ROQ_DBG_ADDR                0x00000821
0957
0958 #define REG_A5XX_CP_ROQ_DBG_DATA                0x00000822
0959
0960 #define REG_A5XX_CP_MEQ_DBG_ADDR                0x00000823
0961
0962 #define REG_A5XX_CP_MEQ_DBG_DATA                0x00000824
0963
0964 #define REG_A5XX_CP_MEQ_THRESHOLDS              0x00000825
0965
0966 #define REG_A5XX_CP_MERCIU_SIZE                 0x00000826
0967
0968 #define REG_A5XX_CP_MERCIU_DBG_ADDR             0x00000827
0969
0970 #define REG_A5XX_CP_MERCIU_DBG_DATA_1               0x00000828
0971
0972 #define REG_A5XX_CP_MERCIU_DBG_DATA_2               0x00000829
0973
0974 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR              0x0000082a
0975
0976 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA              0x0000082b
0977
0978 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR               0x0000082f
0979
0980 #define REG_A5XX_CP_ME_UCODE_DBG_DATA               0x00000830
0981
0982 #define REG_A5XX_CP_CNTL                    0x00000831
0983
0984 #define REG_A5XX_CP_PFP_ME_CNTL                 0x00000832
0985
0986 #define REG_A5XX_CP_CHICKEN_DBG                 0x00000833
0987
0988 #define REG_A5XX_CP_PFP_INSTR_BASE_LO               0x00000835
0989
0990 #define REG_A5XX_CP_PFP_INSTR_BASE_HI               0x00000836
0991
0992 #define REG_A5XX_CP_ME_INSTR_BASE_LO                0x00000838
0993
0994 #define REG_A5XX_CP_ME_INSTR_BASE_HI                0x00000839
0995
0996 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL             0x0000083b
0997
0998 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO      0x0000083c
0999
1000 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI      0x0000083d
1001
1002 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO         0x0000083e
1003
1004 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI         0x0000083f
1005
1006 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO         0x00000840
1007
1008 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI         0x00000841
1009
1010 #define REG_A5XX_CP_ADDR_MODE_CNTL              0x00000860
1011
1012 #define REG_A5XX_CP_ME_STAT_DATA                0x00000b14
1013
1014 #define REG_A5XX_CP_WFI_PEND_CTR                0x00000b15
1015
1016 #define REG_A5XX_CP_INTERRUPT_STATUS                0x00000b18
1017
1018 #define REG_A5XX_CP_HW_FAULT                    0x00000b1a
1019
1020 #define REG_A5XX_CP_PROTECT_STATUS              0x00000b1c
1021
1022 #define REG_A5XX_CP_IB1_BASE                    0x00000b1f
1023
1024 #define REG_A5XX_CP_IB1_BASE_HI                 0x00000b20
1025
1026 #define REG_A5XX_CP_IB1_BUFSZ                   0x00000b21
1027
1028 #define REG_A5XX_CP_IB2_BASE                    0x00000b22
1029
1030 #define REG_A5XX_CP_IB2_BASE_HI                 0x00000b23
1031
1032 #define REG_A5XX_CP_IB2_BUFSZ                   0x00000b24
1033
1034 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1035
1036 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1037
1038 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1039
1040 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1041 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK         0x0001ffff
1042 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT            0
1043 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1044 {
1045     return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1046 }
1047 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK          0x1f000000
1048 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT         24
1049 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1050 {
1051     return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
1052 }
1053 #define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK            0x20000000
1054 #define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT           29
1055 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
1056 {
1057     return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
1058 }
1059 #define A5XX_CP_PROTECT_REG_TRAP_READ__MASK         0x40000000
1060 #define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT            30
1061 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
1062 {
1063     return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK;
1064 }
1065
1066 #define REG_A5XX_CP_PROTECT_CNTL                0x000008a0
1067
1068 #define REG_A5XX_CP_AHB_FAULT                   0x00000b1b
1069
1070 #define REG_A5XX_CP_PERFCTR_CP_SEL_0                0x00000bb0
1071
1072 #define REG_A5XX_CP_PERFCTR_CP_SEL_1                0x00000bb1
1073
1074 #define REG_A5XX_CP_PERFCTR_CP_SEL_2                0x00000bb2
1075
1076 #define REG_A5XX_CP_PERFCTR_CP_SEL_3                0x00000bb3
1077
1078 #define REG_A5XX_CP_PERFCTR_CP_SEL_4                0x00000bb4
1079
1080 #define REG_A5XX_CP_PERFCTR_CP_SEL_5                0x00000bb5
1081
1082 #define REG_A5XX_CP_PERFCTR_CP_SEL_6                0x00000bb6
1083
1084 #define REG_A5XX_CP_PERFCTR_CP_SEL_7                0x00000bb7
1085
1086 #define REG_A5XX_VSC_ADDR_MODE_CNTL             0x00000bc1
1087
1088 #define REG_A5XX_CP_POWERCTR_CP_SEL_0               0x00000bba
1089
1090 #define REG_A5XX_CP_POWERCTR_CP_SEL_1               0x00000bbb
1091
1092 #define REG_A5XX_CP_POWERCTR_CP_SEL_2               0x00000bbc
1093
1094 #define REG_A5XX_CP_POWERCTR_CP_SEL_3               0x00000bbd
1095
1096 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A              0x00000004
1097
1098 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B              0x00000005
1099
1100 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C              0x00000006
1101
1102 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D              0x00000007
1103
1104 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT              0x00000008
1105
1106 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM              0x00000009
1107
1108 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT     0x00000018
1109
1110 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL                0x0000000a
1111
1112 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE                0x0000000b
1113
1114 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0             0x0000000c
1115
1116 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1             0x0000000d
1117
1118 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2             0x0000000e
1119
1120 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3             0x0000000f
1121
1122 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0            0x00000010
1123
1124 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1            0x00000011
1125
1126 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2            0x00000012
1127
1128 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3            0x00000013
1129
1130 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0            0x00000014
1131
1132 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1            0x00000015
1133
1134 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0             0x00000016
1135
1136 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1             0x00000017
1137
1138 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2             0x00000018
1139
1140 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3             0x00000019
1141
1142 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0            0x0000001a
1143
1144 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1            0x0000001b
1145
1146 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2            0x0000001c
1147
1148 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3            0x0000001d
1149
1150 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE            0x0000001e
1151
1152 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0              0x0000001f
1153
1154 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1              0x00000020
1155
1156 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG            0x00000021
1157
1158 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX                0x00000022
1159
1160 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC               0x00000023
1161
1162 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT            0x00000024
1163
1164 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL           0x0000002f
1165
1166 #define REG_A5XX_RBBM_INT_CLEAR_CMD             0x00000037
1167
1168 #define REG_A5XX_RBBM_INT_0_MASK                0x00000038
1169 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE          0x00000001
1170 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR         0x00000002
1171 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT      0x00000004
1172 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT         0x00000008
1173 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT        0x00000010
1174 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT        0x00000020
1175 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW        0x00000040
1176 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR         0x00000080
1177 #define A5XX_RBBM_INT_0_MASK_CP_SW              0x00000100
1178 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR            0x00000200
1179 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS      0x00000400
1180 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS      0x00000800
1181 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS          0x00001000
1182 #define A5XX_RBBM_INT_0_MASK_CP_IB2             0x00002000
1183 #define A5XX_RBBM_INT_0_MASK_CP_IB1             0x00004000
1184 #define A5XX_RBBM_INT_0_MASK_CP_RB              0x00008000
1185 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS          0x00020000
1186 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS          0x00040000
1187 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS          0x00100000
1188 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW      0x00400000
1189 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT           0x00800000
1190 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS            0x01000000
1191 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR         0x02000000
1192 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0          0x04000000
1193 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1          0x08000000
1194 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP         0x10000000
1195 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE          0x20000000
1196 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ           0x40000000
1197 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG           0x80000000
1198
1199 #define REG_A5XX_RBBM_AHB_DBG_CNTL              0x0000003f
1200
1201 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL             0x00000041
1202
1203 #define REG_A5XX_RBBM_SW_RESET_CMD              0x00000043
1204
1205 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD            0x00000045
1206
1207 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2           0x00000046
1208
1209 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO                0x00000048
1210
1211 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL            0x00000049
1212
1213 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0                0x0000004a
1214
1215 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1                0x0000004b
1216
1217 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2                0x0000004c
1218
1219 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3                0x0000004d
1220
1221 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0               0x0000004e
1222
1223 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1               0x0000004f
1224
1225 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2               0x00000050
1226
1227 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3               0x00000051
1228
1229 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0               0x00000052
1230
1231 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1               0x00000053
1232
1233 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2               0x00000054
1234
1235 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3               0x00000055
1236
1237 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG          0x00000059
1238
1239 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE               0x0000005a
1240
1241 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE              0x0000005b
1242
1243 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE              0x0000005c
1244
1245 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE              0x0000005d
1246
1247 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE               0x0000005e
1248
1249 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE              0x0000005f
1250
1251 #define REG_A5XX_RBBM_CLOCK_MODE_GPC                0x00000060
1252
1253 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC               0x00000061
1254
1255 #define REG_A5XX_RBBM_CLOCK_HYST_GPC                0x00000062
1256
1257 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM           0x00000063
1258
1259 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM           0x00000064
1260
1261 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM          0x00000065
1262
1263 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ              0x00000066
1264
1265 #define REG_A5XX_RBBM_CLOCK_CNTL                0x00000067
1266
1267 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0                0x00000068
1268
1269 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1                0x00000069
1270
1271 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2                0x0000006a
1272
1273 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3                0x0000006b
1274
1275 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0               0x0000006c
1276
1277 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1               0x0000006d
1278
1279 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2               0x0000006e
1280
1281 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3               0x0000006f
1282
1283 #define REG_A5XX_RBBM_CLOCK_HYST_SP0                0x00000070
1284
1285 #define REG_A5XX_RBBM_CLOCK_HYST_SP1                0x00000071
1286
1287 #define REG_A5XX_RBBM_CLOCK_HYST_SP2                0x00000072
1288
1289 #define REG_A5XX_RBBM_CLOCK_HYST_SP3                0x00000073
1290
1291 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0               0x00000074
1292
1293 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1               0x00000075
1294
1295 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2               0x00000076
1296
1297 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3               0x00000077
1298
1299 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0                0x00000078
1300
1301 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1                0x00000079
1302
1303 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2                0x0000007a
1304
1305 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3                0x0000007b
1306
1307 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0               0x0000007c
1308
1309 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1               0x0000007d
1310
1311 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2               0x0000007e
1312
1313 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3               0x0000007f
1314
1315 #define REG_A5XX_RBBM_CLOCK_HYST_RAC                0x00000080
1316
1317 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC               0x00000081
1318
1319 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0               0x00000082
1320
1321 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1               0x00000083
1322
1323 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2               0x00000084
1324
1325 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3               0x00000085
1326
1327 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0            0x00000086
1328
1329 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1            0x00000087
1330
1331 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2            0x00000088
1332
1333 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3            0x00000089
1334
1335 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC                0x0000008a
1336
1337 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC               0x0000008b
1338
1339 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0           0x0000008c
1340
1341 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1           0x0000008d
1342
1343 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2           0x0000008e
1344
1345 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3           0x0000008f
1346
1347 #define REG_A5XX_RBBM_CLOCK_HYST_VFD                0x00000090
1348
1349 #define REG_A5XX_RBBM_CLOCK_MODE_VFD                0x00000091
1350
1351 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD               0x00000092
1352
1353 #define REG_A5XX_RBBM_AHB_CNTL0                 0x00000093
1354
1355 #define REG_A5XX_RBBM_AHB_CNTL1                 0x00000094
1356
1357 #define REG_A5XX_RBBM_AHB_CNTL2                 0x00000095
1358
1359 #define REG_A5XX_RBBM_AHB_CMD                   0x00000096
1360
1361 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11        0x0000009c
1362
1363 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12        0x0000009d
1364
1365 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13        0x0000009e
1366
1367 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14        0x0000009f
1368
1369 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15        0x000000a0
1370
1371 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16        0x000000a1
1372
1373 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17        0x000000a2
1374
1375 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18        0x000000a3
1376
1377 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0               0x000000a4
1378
1379 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1               0x000000a5
1380
1381 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2               0x000000a6
1382
1383 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3               0x000000a7
1384
1385 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0              0x000000a8
1386
1387 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1              0x000000a9
1388
1389 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2              0x000000aa
1390
1391 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3              0x000000ab
1392
1393 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0              0x000000ac
1394
1395 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1              0x000000ad
1396
1397 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2              0x000000ae
1398
1399 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3              0x000000af
1400
1401 #define REG_A5XX_RBBM_CLOCK_HYST_TP0                0x000000b0
1402
1403 #define REG_A5XX_RBBM_CLOCK_HYST_TP1                0x000000b1
1404
1405 #define REG_A5XX_RBBM_CLOCK_HYST_TP2                0x000000b2
1406
1407 #define REG_A5XX_RBBM_CLOCK_HYST_TP3                0x000000b3
1408
1409 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0               0x000000b4
1410
1411 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1               0x000000b5
1412
1413 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2               0x000000b6
1414
1415 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3               0x000000b7
1416
1417 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0               0x000000b8
1418
1419 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1               0x000000b9
1420
1421 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2               0x000000ba
1422
1423 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3               0x000000bb
1424
1425 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU               0x000000c8
1426
1427 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU              0x000000c9
1428
1429 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU               0x000000ca
1430
1431 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO               0x000003a0
1432
1433 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI               0x000003a1
1434
1435 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO               0x000003a2
1436
1437 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI               0x000003a3
1438
1439 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO               0x000003a4
1440
1441 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI               0x000003a5
1442
1443 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO               0x000003a6
1444
1445 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI               0x000003a7
1446
1447 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO               0x000003a8
1448
1449 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI               0x000003a9
1450
1451 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO               0x000003aa
1452
1453 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI               0x000003ab
1454
1455 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO               0x000003ac
1456
1457 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI               0x000003ad
1458
1459 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO               0x000003ae
1460
1461 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI               0x000003af
1462
1463 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO             0x000003b0
1464
1465 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI             0x000003b1
1466
1467 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO             0x000003b2
1468
1469 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI             0x000003b3
1470
1471 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO             0x000003b4
1472
1473 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI             0x000003b5
1474
1475 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO             0x000003b6
1476
1477 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI             0x000003b7
1478
1479 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO               0x000003b8
1480
1481 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI               0x000003b9
1482
1483 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO               0x000003ba
1484
1485 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI               0x000003bb
1486
1487 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO               0x000003bc
1488
1489 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI               0x000003bd
1490
1491 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO               0x000003be
1492
1493 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI               0x000003bf
1494
1495 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO               0x000003c0
1496
1497 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI               0x000003c1
1498
1499 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO               0x000003c2
1500
1501 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI               0x000003c3
1502
1503 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO               0x000003c4
1504
1505 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI               0x000003c5
1506
1507 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO               0x000003c6
1508
1509 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI               0x000003c7
1510
1511 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO              0x000003c8
1512
1513 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI              0x000003c9
1514
1515 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO              0x000003ca
1516
1517 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI              0x000003cb
1518
1519 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO              0x000003cc
1520
1521 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI              0x000003cd
1522
1523 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO              0x000003ce
1524
1525 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI              0x000003cf
1526
1527 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO              0x000003d0
1528
1529 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI              0x000003d1
1530
1531 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO              0x000003d2
1532
1533 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI              0x000003d3
1534
1535 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO              0x000003d4
1536
1537 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI              0x000003d5
1538
1539 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO              0x000003d6
1540
1541 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI              0x000003d7
1542
1543 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO             0x000003d8
1544
1545 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI             0x000003d9
1546
1547 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO             0x000003da
1548
1549 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI             0x000003db
1550
1551 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO             0x000003dc
1552
1553 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI             0x000003dd
1554
1555 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO             0x000003de
1556
1557 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI             0x000003df
1558
1559 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO             0x000003e0
1560
1561 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI             0x000003e1
1562
1563 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO             0x000003e2
1564
1565 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI             0x000003e3
1566
1567 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO             0x000003e4
1568
1569 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI             0x000003e5
1570
1571 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO             0x000003e6
1572
1573 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI             0x000003e7
1574
1575 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO              0x000003e8
1576
1577 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI              0x000003e9
1578
1579 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO              0x000003ea
1580
1581 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI              0x000003eb
1582
1583 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO              0x000003ec
1584
1585 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI              0x000003ed
1586
1587 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO              0x000003ee
1588
1589 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI              0x000003ef
1590
1591 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO              0x000003f0
1592
1593 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI              0x000003f1
1594
1595 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO              0x000003f2
1596
1597 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI              0x000003f3
1598
1599 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO              0x000003f4
1600
1601 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI              0x000003f5
1602
1603 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO              0x000003f6
1604
1605 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI              0x000003f7
1606
1607 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO              0x000003f8
1608
1609 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI              0x000003f9
1610
1611 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO              0x000003fa
1612
1613 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI              0x000003fb
1614
1615 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO              0x000003fc
1616
1617 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI              0x000003fd
1618
1619 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO              0x000003fe
1620
1621 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI              0x000003ff
1622
1623 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO              0x00000400
1624
1625 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI              0x00000401
1626
1627 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO              0x00000402
1628
1629 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI              0x00000403
1630
1631 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO              0x00000404
1632
1633 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI              0x00000405
1634
1635 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO              0x00000406
1636
1637 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI              0x00000407
1638
1639 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO             0x00000408
1640
1641 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI             0x00000409
1642
1643 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO             0x0000040a
1644
1645 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI             0x0000040b
1646
1647 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO             0x0000040c
1648
1649 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI             0x0000040d
1650
1651 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO             0x0000040e
1652
1653 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI             0x0000040f
1654
1655 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO             0x00000410
1656
1657 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI             0x00000411
1658
1659 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO             0x00000412
1660
1661 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI             0x00000413
1662
1663 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO             0x00000414
1664
1665 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI             0x00000415
1666
1667 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO             0x00000416
1668
1669 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI             0x00000417
1670
1671 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO               0x00000418
1672
1673 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI               0x00000419
1674
1675 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO               0x0000041a
1676
1677 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI               0x0000041b
1678
1679 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO               0x0000041c
1680
1681 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI               0x0000041d
1682
1683 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO               0x0000041e
1684
1685 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI               0x0000041f
1686
1687 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO               0x00000420
1688
1689 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI               0x00000421
1690
1691 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO               0x00000422
1692
1693 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI               0x00000423
1694
1695 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO               0x00000424
1696
1697 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI               0x00000425
1698
1699 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO               0x00000426
1700
1701 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI               0x00000427
1702
1703 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO               0x00000428
1704
1705 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI               0x00000429
1706
1707 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO               0x0000042a
1708
1709 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI               0x0000042b
1710
1711 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO               0x0000042c
1712
1713 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI               0x0000042d
1714
1715 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO               0x0000042e
1716
1717 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI               0x0000042f
1718
1719 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO               0x00000430
1720
1721 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI               0x00000431
1722
1723 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO               0x00000432
1724
1725 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI               0x00000433
1726
1727 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO               0x00000434
1728
1729 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI               0x00000435
1730
1731 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO               0x00000436
1732
1733 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI               0x00000437
1734
1735 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO               0x00000438
1736
1737 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI               0x00000439
1738
1739 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO               0x0000043a
1740
1741 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI               0x0000043b
1742
1743 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO              0x0000043c
1744
1745 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI              0x0000043d
1746
1747 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO              0x0000043e
1748
1749 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI              0x0000043f
1750
1751 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO               0x00000440
1752
1753 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI               0x00000441
1754
1755 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO               0x00000442
1756
1757 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI               0x00000443
1758
1759 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO               0x00000444
1760
1761 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI               0x00000445
1762
1763 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO               0x00000446
1764
1765 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI               0x00000447
1766
1767 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO               0x00000448
1768
1769 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI               0x00000449
1770
1771 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO               0x0000044a
1772
1773 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI               0x0000044b
1774
1775 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO               0x0000044c
1776
1777 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI               0x0000044d
1778
1779 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO               0x0000044e
1780
1781 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI               0x0000044f
1782
1783 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO              0x00000450
1784
1785 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI              0x00000451
1786
1787 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO              0x00000452
1788
1789 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI              0x00000453
1790
1791 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO              0x00000454
1792
1793 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI              0x00000455
1794
1795 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO              0x00000456
1796
1797 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI              0x00000457
1798
1799 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO              0x00000458
1800
1801 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI              0x00000459
1802
1803 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO              0x0000045a
1804
1805 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI              0x0000045b
1806
1807 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO              0x0000045c
1808
1809 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI              0x0000045d
1810
1811 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO              0x0000045e
1812
1813 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI              0x0000045f
1814
1815 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO              0x00000460
1816
1817 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI              0x00000461
1818
1819 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO              0x00000462
1820
1821 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI              0x00000463
1822
1823 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0            0x0000046b
1824
1825 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1            0x0000046c
1826
1827 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2            0x0000046d
1828
1829 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3            0x0000046e
1830
1831 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO           0x000004d2
1832
1833 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI           0x000004d3
1834
1835 #define REG_A5XX_RBBM_STATUS                    0x000004f5
1836 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK         0x80000000
1837 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT        31
1838 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)
1839 {
1840     return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK;
1841 }
1842 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK      0x40000000
1843 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT     30
1844 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)
1845 {
1846     return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK;
1847 }
1848 #define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK            0x20000000
1849 #define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT           29
1850 static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)
1851 {
1852     return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK;
1853 }
1854 #define A5XX_RBBM_STATUS_VSC_BUSY__MASK             0x10000000
1855 #define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT            28
1856 static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)
1857 {
1858     return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK;
1859 }
1860 #define A5XX_RBBM_STATUS_TPL1_BUSY__MASK            0x08000000
1861 #define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT           27
1862 static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)
1863 {
1864     return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK;
1865 }
1866 #define A5XX_RBBM_STATUS_SP_BUSY__MASK              0x04000000
1867 #define A5XX_RBBM_STATUS_SP_BUSY__SHIFT             26
1868 static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)
1869 {
1870     return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK;
1871 }
1872 #define A5XX_RBBM_STATUS_UCHE_BUSY__MASK            0x02000000
1873 #define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT           25
1874 static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)
1875 {
1876     return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK;
1877 }
1878 #define A5XX_RBBM_STATUS_VPC_BUSY__MASK             0x01000000
1879 #define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT            24
1880 static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)
1881 {
1882     return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK;
1883 }
1884 #define A5XX_RBBM_STATUS_VFDP_BUSY__MASK            0x00800000
1885 #define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT           23
1886 static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)
1887 {
1888     return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK;
1889 }
1890 #define A5XX_RBBM_STATUS_VFD_BUSY__MASK             0x00400000
1891 #define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT            22
1892 static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)
1893 {
1894     return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK;
1895 }
1896 #define A5XX_RBBM_STATUS_TESS_BUSY__MASK            0x00200000
1897 #define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT           21
1898 static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)
1899 {
1900     return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK;
1901 }
1902 #define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK          0x00100000
1903 #define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT         20
1904 static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)
1905 {
1906     return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK;
1907 }
1908 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK            0x00080000
1909 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT           19
1910 static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)
1911 {
1912     return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK;
1913 }
1914 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK          0x00040000
1915 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT         18
1916 static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)
1917 {
1918     return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK;
1919 }
1920 #define A5XX_RBBM_STATUS_DCOM_BUSY__MASK            0x00020000
1921 #define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT           17
1922 static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)
1923 {
1924     return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK;
1925 }
1926 #define A5XX_RBBM_STATUS_COM_BUSY__MASK             0x00010000
1927 #define A5XX_RBBM_STATUS_COM_BUSY__SHIFT            16
1928 static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)
1929 {
1930     return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK;
1931 }
1932 #define A5XX_RBBM_STATUS_LRZ_BUZY__MASK             0x00008000
1933 #define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT            15
1934 static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)
1935 {
1936     return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK;
1937 }
1938 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK         0x00004000
1939 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT            14
1940 static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)
1941 {
1942     return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK;
1943 }
1944 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK         0x00002000
1945 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT            13
1946 static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)
1947 {
1948     return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK;
1949 }
1950 #define A5XX_RBBM_STATUS_RB_BUSY__MASK              0x00001000
1951 #define A5XX_RBBM_STATUS_RB_BUSY__SHIFT             12
1952 static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)
1953 {
1954     return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK;
1955 }
1956 #define A5XX_RBBM_STATUS_RAS_BUSY__MASK             0x00000800
1957 #define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT            11
1958 static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)
1959 {
1960     return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK;
1961 }
1962 #define A5XX_RBBM_STATUS_TSE_BUSY__MASK             0x00000400
1963 #define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT            10
1964 static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)
1965 {
1966     return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK;
1967 }
1968 #define A5XX_RBBM_STATUS_VBIF_BUSY__MASK            0x00000200
1969 #define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT           9
1970 static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)
1971 {
1972     return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK;
1973 }
1974 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK        0x00000100
1975 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT       8
1976 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)
1977 {
1978     return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK;
1979 }
1980 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK         0x00000080
1981 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT        7
1982 static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)
1983 {
1984     return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK;
1985 }
1986 #define A5XX_RBBM_STATUS_CP_BUSY__MASK              0x00000040
1987 #define A5XX_RBBM_STATUS_CP_BUSY__SHIFT             6
1988 static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)
1989 {
1990     return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK;
1991 }
1992 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK         0x00000020
1993 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT        5
1994 static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)
1995 {
1996     return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK;
1997 }
1998 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK            0x00000010
1999 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT           4
2000 static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)
2001 {
2002     return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK;
2003 }
2004 #define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK          0x00000008
2005 #define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT         3
2006 static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)
2007 {
2008     return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK;
2009 }
2010 #define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK          0x00000004
2011 #define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT         2
2012 static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)
2013 {
2014     return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK;
2015 }
2016 #define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK           0x00000002
2017 #define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT          1
2018 static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
2019 {
2020     return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
2021 }
2022 #define A5XX_RBBM_STATUS_HI_BUSY                0x00000001
2023
2024 #define REG_A5XX_RBBM_STATUS3                   0x00000530
2025 #define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT         0x01000000
2026
2027 #define REG_A5XX_RBBM_INT_0_STATUS              0x000004e1
2028
2029 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS           0x000004f0
2030
2031 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS          0x000004f1
2032
2033 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS          0x000004f3
2034
2035 #define REG_A5XX_RBBM_AHB_ERROR_STATUS              0x000004f4
2036
2037 #define REG_A5XX_RBBM_PERFCTR_CNTL              0x00000464
2038
2039 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0             0x00000465
2040
2041 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1             0x00000466
2042
2043 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2             0x00000467
2044
2045 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3             0x00000468
2046
2047 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO         0x00000469
2048
2049 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI         0x0000046a
2050
2051 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED           0x0000046f
2052
2053 #define REG_A5XX_RBBM_AHB_ERROR                 0x000004ed
2054
2055 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC            0x00000504
2056
2057 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER               0x00000505
2058
2059 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0             0x00000506
2060
2061 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1             0x00000507
2062
2063 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2             0x00000508
2064
2065 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3             0x00000509
2066
2067 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4             0x0000050a
2068
2069 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5             0x0000050b
2070
2071 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR         0x0000050c
2072
2073 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0         0x0000050d
2074
2075 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1         0x0000050e
2076
2077 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2         0x0000050f
2078
2079 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3         0x00000510
2080
2081 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4         0x00000511
2082
2083 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0              0x00000512
2084
2085 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1              0x00000513
2086
2087 #define REG_A5XX_RBBM_ISDB_CNT                  0x00000533
2088
2089 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG           0x0000f000
2090
2091 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL             0x0000f400
2092
2093 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO        0x0000f800
2094
2095 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI        0x0000f801
2096
2097 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE           0x0000f802
2098
2099 #define REG_A5XX_RBBM_SECVID_TSB_CNTL               0x0000f803
2100
2101 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO         0x0000f804
2102
2103 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI         0x0000f805
2104
2105 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO         0x0000f806
2106
2107 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI         0x0000f807
2108
2109 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL         0x0000f810
2110
2111 #define REG_A5XX_VSC_BIN_SIZE                   0x00000bc2
2112 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK               0x000000ff
2113 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT              0
2114 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2115 {
2116     return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
2117 }
2118 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK              0x0001fe00
2119 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT             9
2120 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2121 {
2122     return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
2123 }
2124
2125 #define REG_A5XX_VSC_SIZE_ADDRESS_LO                0x00000bc3
2126
2127 #define REG_A5XX_VSC_SIZE_ADDRESS_HI                0x00000bc4
2128
2129 #define REG_A5XX_UNKNOWN_0BC5                   0x00000bc5
2130
2131 #define REG_A5XX_UNKNOWN_0BC6                   0x00000bc6
2132
2133 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
2134
2135 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
2136 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK            0x000003ff
2137 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT           0
2138 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2139 {
2140     return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
2141 }
2142 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK            0x000ffc00
2143 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT           10
2144 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2145 {
2146     return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2147 }
2148 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK            0x00f00000
2149 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT           20
2150 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2151 {
2152     return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
2153 }
2154 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK            0x0f000000
2155 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT           24
2156 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2157 {
2158     return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
2159 }
2160
2161 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2162
2163 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2164
2165 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
2166
2167 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2168
2169 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2170
2171 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0              0x00000c60
2172
2173 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1              0x00000c61
2174
2175 #define REG_A5XX_VSC_RESOLVE_CNTL               0x00000cdd
2176 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE     0x80000000
2177 #define A5XX_VSC_RESOLVE_CNTL_X__MASK               0x00007fff
2178 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT              0
2179 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
2180 {
2181     return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
2182 }
2183 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK               0x7fff0000
2184 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT              16
2185 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
2186 {
2187     return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
2188 }
2189
2190 #define REG_A5XX_GRAS_ADDR_MODE_CNTL                0x00000c81
2191
2192 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0             0x00000c90
2193
2194 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1             0x00000c91
2195
2196 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2             0x00000c92
2197
2198 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3             0x00000c93
2199
2200 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0             0x00000c94
2201
2202 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1             0x00000c95
2203
2204 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2             0x00000c96
2205
2206 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3             0x00000c97
2207
2208 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0             0x00000c98
2209
2210 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1             0x00000c99
2211
2212 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2             0x00000c9a
2213
2214 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3             0x00000c9b
2215
2216 #define REG_A5XX_RB_DBG_ECO_CNTL                0x00000cc4
2217
2218 #define REG_A5XX_RB_ADDR_MODE_CNTL              0x00000cc5
2219
2220 #define REG_A5XX_RB_MODE_CNTL                   0x00000cc6
2221
2222 #define REG_A5XX_RB_CCU_CNTL                    0x00000cc7
2223
2224 #define REG_A5XX_RB_PERFCTR_RB_SEL_0                0x00000cd0
2225
2226 #define REG_A5XX_RB_PERFCTR_RB_SEL_1                0x00000cd1
2227
2228 #define REG_A5XX_RB_PERFCTR_RB_SEL_2                0x00000cd2
2229
2230 #define REG_A5XX_RB_PERFCTR_RB_SEL_3                0x00000cd3
2231
2232 #define REG_A5XX_RB_PERFCTR_RB_SEL_4                0x00000cd4
2233
2234 #define REG_A5XX_RB_PERFCTR_RB_SEL_5                0x00000cd5
2235
2236 #define REG_A5XX_RB_PERFCTR_RB_SEL_6                0x00000cd6
2237
2238 #define REG_A5XX_RB_PERFCTR_RB_SEL_7                0x00000cd7
2239
2240 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0               0x00000cd8
2241
2242 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1               0x00000cd9
2243
2244 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2               0x00000cda
2245
2246 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3               0x00000cdb
2247
2248 #define REG_A5XX_RB_POWERCTR_RB_SEL_0               0x00000ce0
2249
2250 #define REG_A5XX_RB_POWERCTR_RB_SEL_1               0x00000ce1
2251
2252 #define REG_A5XX_RB_POWERCTR_RB_SEL_2               0x00000ce2
2253
2254 #define REG_A5XX_RB_POWERCTR_RB_SEL_3               0x00000ce3
2255
2256 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0              0x00000ce4
2257
2258 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1              0x00000ce5
2259
2260 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0               0x00000cec
2261
2262 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1               0x00000ced
2263
2264 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2               0x00000cee
2265
2266 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3               0x00000cef
2267
2268 #define REG_A5XX_PC_DBG_ECO_CNTL                0x00000d00
2269 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI          0x00000100
2270
2271 #define REG_A5XX_PC_ADDR_MODE_CNTL              0x00000d01
2272
2273 #define REG_A5XX_PC_MODE_CNTL                   0x00000d02
2274
2275 #define REG_A5XX_PC_INDEX_BUF_LO                0x00000d04
2276
2277 #define REG_A5XX_PC_INDEX_BUF_HI                0x00000d05
2278
2279 #define REG_A5XX_PC_START_INDEX                 0x00000d06
2280
2281 #define REG_A5XX_PC_MAX_INDEX                   0x00000d07
2282
2283 #define REG_A5XX_PC_TESSFACTOR_ADDR_LO              0x00000d08
2284
2285 #define REG_A5XX_PC_TESSFACTOR_ADDR_HI              0x00000d09
2286
2287 #define REG_A5XX_PC_PERFCTR_PC_SEL_0                0x00000d10
2288
2289 #define REG_A5XX_PC_PERFCTR_PC_SEL_1                0x00000d11
2290
2291 #define REG_A5XX_PC_PERFCTR_PC_SEL_2                0x00000d12
2292
2293 #define REG_A5XX_PC_PERFCTR_PC_SEL_3                0x00000d13
2294
2295 #define REG_A5XX_PC_PERFCTR_PC_SEL_4                0x00000d14
2296
2297 #define REG_A5XX_PC_PERFCTR_PC_SEL_5                0x00000d15
2298
2299 #define REG_A5XX_PC_PERFCTR_PC_SEL_6                0x00000d16
2300
2301 #define REG_A5XX_PC_PERFCTR_PC_SEL_7                0x00000d17
2302
2303 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0           0x00000e00
2304
2305 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1           0x00000e01
2306
2307 #define REG_A5XX_HLSQ_DBG_ECO_CNTL              0x00000e04
2308
2309 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL                0x00000e05
2310
2311 #define REG_A5XX_HLSQ_MODE_CNTL                 0x00000e06
2312
2313 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0            0x00000e10
2314
2315 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1            0x00000e11
2316
2317 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2            0x00000e12
2318
2319 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3            0x00000e13
2320
2321 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4            0x00000e14
2322
2323 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5            0x00000e15
2324
2325 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6            0x00000e16
2326
2327 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7            0x00000e17
2328
2329 #define REG_A5XX_HLSQ_SPTP_RDSEL                0x00000f08
2330
2331 #define REG_A5XX_HLSQ_DBG_READ_SEL              0x0000bc00
2332
2333 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE         0x0000a000
2334
2335 #define REG_A5XX_VFD_ADDR_MODE_CNTL             0x00000e41
2336
2337 #define REG_A5XX_VFD_MODE_CNTL                  0x00000e42
2338
2339 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0              0x00000e50
2340
2341 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1              0x00000e51
2342
2343 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2              0x00000e52
2344
2345 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3              0x00000e53
2346
2347 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4              0x00000e54
2348
2349 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5              0x00000e55
2350
2351 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6              0x00000e56
2352
2353 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7              0x00000e57
2354
2355 #define REG_A5XX_VPC_DBG_ECO_CNTL               0x00000e60
2356 #define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS         0x00000400
2357
2358 #define REG_A5XX_VPC_ADDR_MODE_CNTL             0x00000e61
2359
2360 #define REG_A5XX_VPC_MODE_CNTL                  0x00000e62
2361 #define A5XX_VPC_MODE_CNTL_BINNING_PASS             0x00000001
2362
2363 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0              0x00000e64
2364
2365 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1              0x00000e65
2366
2367 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2              0x00000e66
2368
2369 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3              0x00000e67
2370
2371 #define REG_A5XX_UCHE_ADDR_MODE_CNTL                0x00000e80
2372
2373 #define REG_A5XX_UCHE_MODE_CNTL                 0x00000e81
2374
2375 #define REG_A5XX_UCHE_SVM_CNTL                  0x00000e82
2376
2377 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO            0x00000e87
2378
2379 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI            0x00000e88
2380
2381 #define REG_A5XX_UCHE_TRAP_BASE_LO              0x00000e89
2382
2383 #define REG_A5XX_UCHE_TRAP_BASE_HI              0x00000e8a
2384
2385 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO             0x00000e8b
2386
2387 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI             0x00000e8c
2388
2389 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO             0x00000e8d
2390
2391 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI             0x00000e8e
2392
2393 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2                0x00000e8f
2394
2395 #define REG_A5XX_UCHE_DBG_ECO_CNTL              0x00000e90
2396
2397 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO           0x00000e91
2398
2399 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI           0x00000e92
2400
2401 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO           0x00000e93
2402
2403 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI           0x00000e94
2404
2405 #define REG_A5XX_UCHE_CACHE_INVALIDATE              0x00000e95
2406
2407 #define REG_A5XX_UCHE_CACHE_WAYS                0x00000e96
2408
2409 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0            0x00000ea0
2410
2411 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1            0x00000ea1
2412
2413 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2            0x00000ea2
2414
2415 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3            0x00000ea3
2416
2417 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4            0x00000ea4
2418
2419 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5            0x00000ea5
2420
2421 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6            0x00000ea6
2422
2423 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7            0x00000ea7
2424
2425 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0           0x00000ea8
2426
2427 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1           0x00000ea9
2428
2429 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2           0x00000eaa
2430
2431 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3           0x00000eab
2432
2433 #define REG_A5XX_UCHE_TRAP_LOG_LO               0x00000eb1
2434
2435 #define REG_A5XX_UCHE_TRAP_LOG_HI               0x00000eb2
2436
2437 #define REG_A5XX_SP_DBG_ECO_CNTL                0x00000ec0
2438
2439 #define REG_A5XX_SP_ADDR_MODE_CNTL              0x00000ec1
2440
2441 #define REG_A5XX_SP_MODE_CNTL                   0x00000ec2
2442
2443 #define REG_A5XX_SP_PERFCTR_SP_SEL_0                0x00000ed0
2444
2445 #define REG_A5XX_SP_PERFCTR_SP_SEL_1                0x00000ed1
2446
2447 #define REG_A5XX_SP_PERFCTR_SP_SEL_2                0x00000ed2
2448
2449 #define REG_A5XX_SP_PERFCTR_SP_SEL_3                0x00000ed3
2450
2451 #define REG_A5XX_SP_PERFCTR_SP_SEL_4                0x00000ed4
2452
2453 #define REG_A5XX_SP_PERFCTR_SP_SEL_5                0x00000ed5
2454
2455 #define REG_A5XX_SP_PERFCTR_SP_SEL_6                0x00000ed6
2456
2457 #define REG_A5XX_SP_PERFCTR_SP_SEL_7                0x00000ed7
2458
2459 #define REG_A5XX_SP_PERFCTR_SP_SEL_8                0x00000ed8
2460
2461 #define REG_A5XX_SP_PERFCTR_SP_SEL_9                0x00000ed9
2462
2463 #define REG_A5XX_SP_PERFCTR_SP_SEL_10               0x00000eda
2464
2465 #define REG_A5XX_SP_PERFCTR_SP_SEL_11               0x00000edb
2466
2467 #define REG_A5XX_SP_POWERCTR_SP_SEL_0               0x00000edc
2468
2469 #define REG_A5XX_SP_POWERCTR_SP_SEL_1               0x00000edd
2470
2471 #define REG_A5XX_SP_POWERCTR_SP_SEL_2               0x00000ede
2472
2473 #define REG_A5XX_SP_POWERCTR_SP_SEL_3               0x00000edf
2474
2475 #define REG_A5XX_TPL1_ADDR_MODE_CNTL                0x00000f01
2476
2477 #define REG_A5XX_TPL1_MODE_CNTL                 0x00000f02
2478
2479 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0              0x00000f10
2480
2481 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1              0x00000f11
2482
2483 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2              0x00000f12
2484
2485 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3              0x00000f13
2486
2487 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4              0x00000f14
2488
2489 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5              0x00000f15
2490
2491 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6              0x00000f16
2492
2493 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7              0x00000f17
2494
2495 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0             0x00000f18
2496
2497 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1             0x00000f19
2498
2499 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2             0x00000f1a
2500
2501 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3             0x00000f1b
2502
2503 #define REG_A5XX_VBIF_VERSION                   0x00003000
2504
2505 #define REG_A5XX_VBIF_CLKON                 0x00003001
2506
2507 #define REG_A5XX_VBIF_ABIT_SORT                 0x00003028
2508
2509 #define REG_A5XX_VBIF_ABIT_SORT_CONF                0x00003029
2510
2511 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB           0x00003049
2512
2513 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN             0x0000302a
2514
2515 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0               0x0000302c
2516
2517 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1               0x0000302d
2518
2519 #define REG_A5XX_VBIF_XIN_HALT_CTRL0                0x00003080
2520
2521 #define REG_A5XX_VBIF_XIN_HALT_CTRL1                0x00003081
2522
2523 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL             0x00003084
2524
2525 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0               0x00003085
2526
2527 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1               0x00003086
2528
2529 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0               0x00003087
2530
2531 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1               0x00003088
2532
2533 #define REG_A5XX_VBIF_TEST_BUS_OUT              0x0000308c
2534
2535 #define REG_A5XX_VBIF_PERF_CNT_EN0              0x000030c0
2536
2537 #define REG_A5XX_VBIF_PERF_CNT_EN1              0x000030c1
2538
2539 #define REG_A5XX_VBIF_PERF_CNT_EN2              0x000030c2
2540
2541 #define REG_A5XX_VBIF_PERF_CNT_EN3              0x000030c3
2542
2543 #define REG_A5XX_VBIF_PERF_CNT_CLR0             0x000030c8
2544
2545 #define REG_A5XX_VBIF_PERF_CNT_CLR1             0x000030c9
2546
2547 #define REG_A5XX_VBIF_PERF_CNT_CLR2             0x000030ca
2548
2549 #define REG_A5XX_VBIF_PERF_CNT_CLR3             0x000030cb
2550
2551 #define REG_A5XX_VBIF_PERF_CNT_SEL0             0x000030d0
2552
2553 #define REG_A5XX_VBIF_PERF_CNT_SEL1             0x000030d1
2554
2555 #define REG_A5XX_VBIF_PERF_CNT_SEL2             0x000030d2
2556
2557 #define REG_A5XX_VBIF_PERF_CNT_SEL3             0x000030d3
2558
2559 #define REG_A5XX_VBIF_PERF_CNT_LOW0             0x000030d8
2560
2561 #define REG_A5XX_VBIF_PERF_CNT_LOW1             0x000030d9
2562
2563 #define REG_A5XX_VBIF_PERF_CNT_LOW2             0x000030da
2564
2565 #define REG_A5XX_VBIF_PERF_CNT_LOW3             0x000030db
2566
2567 #define REG_A5XX_VBIF_PERF_CNT_HIGH0                0x000030e0
2568
2569 #define REG_A5XX_VBIF_PERF_CNT_HIGH1                0x000030e1
2570
2571 #define REG_A5XX_VBIF_PERF_CNT_HIGH2                0x000030e2
2572
2573 #define REG_A5XX_VBIF_PERF_CNT_HIGH3                0x000030e3
2574
2575 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0              0x00003100
2576
2577 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1              0x00003101
2578
2579 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2              0x00003102
2580
2581 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0             0x00003110
2582
2583 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1             0x00003111
2584
2585 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2             0x00003112
2586
2587 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0            0x00003118
2588
2589 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1            0x00003119
2590
2591 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2            0x0000311a
2592
2593 #define REG_A5XX_GPMU_INST_RAM_BASE             0x00008800
2594
2595 #define REG_A5XX_GPMU_DATA_RAM_BASE             0x00009800
2596
2597 #define REG_A5XX_GPMU_SP_POWER_CNTL             0x0000a881
2598
2599 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL              0x0000a886
2600
2601 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL              0x0000a887
2602
2603 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS             0x0000a88b
2604 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON          0x00100000
2605
2606 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS          0x0000a88d
2607 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON           0x00100000
2608
2609 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY         0x0000a891
2610
2611 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL          0x0000a892
2612
2613 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST          0x0000a893
2614
2615 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL          0x0000a894
2616
2617 #define REG_A5XX_GPMU_WFI_CONFIG                0x0000a8c1
2618
2619 #define REG_A5XX_GPMU_RBBM_INTR_INFO                0x0000a8d6
2620
2621 #define REG_A5XX_GPMU_CM3_SYSRESET              0x0000a8d8
2622
2623 #define REG_A5XX_GPMU_GENERAL_0                 0x0000a8e0
2624
2625 #define REG_A5XX_GPMU_GENERAL_1                 0x0000a8e1
2626
2627 #define REG_A5XX_SP_POWER_COUNTER_0_LO              0x0000a840
2628
2629 #define REG_A5XX_SP_POWER_COUNTER_0_HI              0x0000a841
2630
2631 #define REG_A5XX_SP_POWER_COUNTER_1_LO              0x0000a842
2632
2633 #define REG_A5XX_SP_POWER_COUNTER_1_HI              0x0000a843
2634
2635 #define REG_A5XX_SP_POWER_COUNTER_2_LO              0x0000a844
2636
2637 #define REG_A5XX_SP_POWER_COUNTER_2_HI              0x0000a845
2638
2639 #define REG_A5XX_SP_POWER_COUNTER_3_LO              0x0000a846
2640
2641 #define REG_A5XX_SP_POWER_COUNTER_3_HI              0x0000a847
2642
2643 #define REG_A5XX_TP_POWER_COUNTER_0_LO              0x0000a848
2644
2645 #define REG_A5XX_TP_POWER_COUNTER_0_HI              0x0000a849
2646
2647 #define REG_A5XX_TP_POWER_COUNTER_1_LO              0x0000a84a
2648
2649 #define REG_A5XX_TP_POWER_COUNTER_1_HI              0x0000a84b
2650
2651 #define REG_A5XX_TP_POWER_COUNTER_2_LO              0x0000a84c
2652
2653 #define REG_A5XX_TP_POWER_COUNTER_2_HI              0x0000a84d
2654
2655 #define REG_A5XX_TP_POWER_COUNTER_3_LO              0x0000a84e
2656
2657 #define REG_A5XX_TP_POWER_COUNTER_3_HI              0x0000a84f
2658
2659 #define REG_A5XX_RB_POWER_COUNTER_0_LO              0x0000a850
2660
2661 #define REG_A5XX_RB_POWER_COUNTER_0_HI              0x0000a851
2662
2663 #define REG_A5XX_RB_POWER_COUNTER_1_LO              0x0000a852
2664
2665 #define REG_A5XX_RB_POWER_COUNTER_1_HI              0x0000a853
2666
2667 #define REG_A5XX_RB_POWER_COUNTER_2_LO              0x0000a854
2668
2669 #define REG_A5XX_RB_POWER_COUNTER_2_HI              0x0000a855
2670
2671 #define REG_A5XX_RB_POWER_COUNTER_3_LO              0x0000a856
2672
2673 #define REG_A5XX_RB_POWER_COUNTER_3_HI              0x0000a857
2674
2675 #define REG_A5XX_CCU_POWER_COUNTER_0_LO             0x0000a858
2676
2677 #define REG_A5XX_CCU_POWER_COUNTER_0_HI             0x0000a859
2678
2679 #define REG_A5XX_CCU_POWER_COUNTER_1_LO             0x0000a85a
2680
2681 #define REG_A5XX_CCU_POWER_COUNTER_1_HI             0x0000a85b
2682
2683 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO            0x0000a85c
2684
2685 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI            0x0000a85d
2686
2687 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO            0x0000a85e
2688
2689 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI            0x0000a85f
2690
2691 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO            0x0000a860
2692
2693 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI            0x0000a861
2694
2695 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO            0x0000a862
2696
2697 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI            0x0000a863
2698
2699 #define REG_A5XX_CP_POWER_COUNTER_0_LO              0x0000a864
2700
2701 #define REG_A5XX_CP_POWER_COUNTER_0_HI              0x0000a865
2702
2703 #define REG_A5XX_CP_POWER_COUNTER_1_LO              0x0000a866
2704
2705 #define REG_A5XX_CP_POWER_COUNTER_1_HI              0x0000a867
2706
2707 #define REG_A5XX_CP_POWER_COUNTER_2_LO              0x0000a868
2708
2709 #define REG_A5XX_CP_POWER_COUNTER_2_HI              0x0000a869
2710
2711 #define REG_A5XX_CP_POWER_COUNTER_3_LO              0x0000a86a
2712
2713 #define REG_A5XX_CP_POWER_COUNTER_3_HI              0x0000a86b
2714
2715 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO            0x0000a86c
2716
2717 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI            0x0000a86d
2718
2719 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO            0x0000a86e
2720
2721 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI            0x0000a86f
2722
2723 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO            0x0000a870
2724
2725 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI            0x0000a871
2726
2727 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO            0x0000a872
2728
2729 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI            0x0000a873
2730
2731 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO            0x0000a874
2732
2733 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI            0x0000a875
2734
2735 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO            0x0000a876
2736
2737 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI            0x0000a877
2738
2739 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE          0x0000a878
2740
2741 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO          0x0000a879
2742
2743 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI          0x0000a87a
2744
2745 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET           0x0000a87b
2746
2747 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0            0x0000a87c
2748
2749 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1            0x0000a87d
2750
2751 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL           0x0000a8a3
2752
2753 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL        0x0000a8a8
2754
2755 #define REG_A5XX_GPMU_TEMP_SENSOR_ID                0x0000ac00
2756
2757 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG            0x0000ac01
2758
2759 #define REG_A5XX_GPMU_TEMP_VAL                  0x0000ac02
2760
2761 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD          0x0000ac03
2762
2763 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS        0x0000ac05
2764
2765 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK       0x0000ac06
2766
2767 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1            0x0000ac40
2768
2769 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3            0x0000ac41
2770
2771 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1         0x0000ac42
2772
2773 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3         0x0000ac43
2774
2775 #define REG_A5XX_GPMU_BASE_LEAKAGE              0x0000ac46
2776
2777 #define REG_A5XX_GPMU_GPMU_VOLTAGE              0x0000ac60
2778
2779 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS          0x0000ac61
2780
2781 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK         0x0000ac62
2782
2783 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD            0x0000ac80
2784
2785 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL           0x0000acc4
2786
2787 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS         0x0000acc5
2788
2789 #define REG_A5XX_GDPM_CONFIG1                   0x0000b80c
2790
2791 #define REG_A5XX_GDPM_CONFIG2                   0x0000b80d
2792
2793 #define REG_A5XX_GDPM_INT_EN                    0x0000b80f
2794
2795 #define REG_A5XX_GDPM_INT_MASK                  0x0000b811
2796
2797 #define REG_A5XX_GPMU_BEC_ENABLE                0x0000b9a0
2798
2799 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS           0x0000c41a
2800
2801 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0       0x0000c41d
2802
2803 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2       0x0000c41f
2804
2805 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4       0x0000c421
2806
2807 #define REG_A5XX_GPU_CS_ENABLE_REG              0x0000c520
2808
2809 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1        0x0000c557
2810
2811 #define REG_A5XX_GRAS_CL_CNTL                   0x0000e000
2812 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z           0x00000040
2813
2814 #define REG_A5XX_GRAS_VS_CL_CNTL                0x0000e001
2815 #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK            0x000000ff
2816 #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT           0
2817 static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2818 {
2819     return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2820 }
2821 #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK            0x0000ff00
2822 #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT           8
2823 static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2824 {
2825     return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2826 }
2827
2828 #define REG_A5XX_UNKNOWN_E004                   0x0000e004
2829
2830 #define REG_A5XX_GRAS_CNTL                  0x0000e005
2831 #define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL               0x00000001
2832 #define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID            0x00000002
2833 #define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE              0x00000004
2834 #define A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL              0x00000008
2835 #define A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID           0x00000010
2836 #define A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE             0x00000020
2837 #define A5XX_GRAS_CNTL_COORD_MASK__MASK             0x000003c0
2838 #define A5XX_GRAS_CNTL_COORD_MASK__SHIFT            6
2839 static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2840 {
2841     return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
2842 }
2843
2844 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ         0x0000e006
2845 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK      0x000003ff
2846 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT     0
2847 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2848 {
2849     return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2850 }
2851 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK      0x000ffc00
2852 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT     10
2853 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2854 {
2855     return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2856 }
2857
2858 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0            0x0000e010
2859 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK          0xffffffff
2860 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT         0
2861 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2862 {
2863     return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2864 }
2865
2866 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0             0x0000e011
2867 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK           0xffffffff
2868 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT          0
2869 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
2870 {
2871     return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2872 }
2873
2874 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0            0x0000e012
2875 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK          0xffffffff
2876 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT         0
2877 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2878 {
2879     return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2880 }
2881
2882 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0             0x0000e013
2883 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK           0xffffffff
2884 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT          0
2885 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
2886 {
2887     return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2888 }
2889
2890 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0            0x0000e014
2891 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK          0xffffffff
2892 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT         0
2893 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2894 {
2895     return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2896 }
2897
2898 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0             0x0000e015
2899 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK           0xffffffff
2900 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT          0
2901 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2902 {
2903     return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2904 }
2905
2906 #define REG_A5XX_GRAS_SU_CNTL                   0x0000e090
2907 #define A5XX_GRAS_SU_CNTL_CULL_FRONT                0x00000001
2908 #define A5XX_GRAS_SU_CNTL_CULL_BACK             0x00000002
2909 #define A5XX_GRAS_SU_CNTL_FRONT_CW              0x00000004
2910 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK           0x000007f8
2911 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT          3
2912 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2913 {
2914     return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2915 }
2916 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET               0x00000800
2917 #define A5XX_GRAS_SU_CNTL_LINE_MODE__MASK           0x00002000
2918 #define A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT          13
2919 static inline uint32_t A5XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
2920 {
2921     return ((val) << A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A5XX_GRAS_SU_CNTL_LINE_MODE__MASK;
2922 }
2923
2924 #define REG_A5XX_GRAS_SU_POINT_MINMAX               0x0000e091
2925 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK         0x0000ffff
2926 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT            0
2927 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2928 {
2929     return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2930 }
2931 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK         0xffff0000
2932 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT            16
2933 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2934 {
2935     return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2936 }
2937
2938 #define REG_A5XX_GRAS_SU_POINT_SIZE             0x0000e092
2939 #define A5XX_GRAS_SU_POINT_SIZE__MASK               0xffffffff
2940 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT              0
2941 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2942 {
2943     return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2944 }
2945
2946 #define REG_A5XX_GRAS_SU_LAYERED                0x0000e093
2947
2948 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL           0x0000e094
2949 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z     0x00000001
2950 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1          0x00000002
2951
2952 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE          0x0000e095
2953 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK            0xffffffff
2954 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT           0
2955 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2956 {
2957     return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2958 }
2959
2960 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET         0x0000e096
2961 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK           0xffffffff
2962 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT          0
2963 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2964 {
2965     return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2966 }
2967
2968 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP       0x0000e097
2969 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK     0xffffffff
2970 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT        0
2971 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2972 {
2973     return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2974 }
2975
2976 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO          0x0000e098
2977 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK   0x00000007
2978 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT  0
2979 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2980 {
2981     return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2982 }
2983
2984 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL          0x0000e099
2985
2986 #define REG_A5XX_GRAS_SC_CNTL                   0x0000e0a0
2987 #define A5XX_GRAS_SC_CNTL_BINNING_PASS              0x00000001
2988 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED            0x00008000
2989
2990 #define REG_A5XX_GRAS_SC_BIN_CNTL               0x0000e0a1
2991
2992 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL              0x0000e0a2
2993 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK        0x00000003
2994 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT       0
2995 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2996 {
2997     return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2998 }
2999
3000 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL             0x0000e0a3
3001 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK       0x00000003
3002 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT      0
3003 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3004 {
3005     return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
3006 }
3007 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE        0x00000004
3008
3009 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL            0x0000e0a4
3010
3011 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0            0x0000e0aa
3012 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE  0x80000000
3013 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK        0x00007fff
3014 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT       0
3015 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
3016 {
3017     return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
3018 }
3019 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK        0x7fff0000
3020 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT       16
3021 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
3022 {
3023     return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
3024 }
3025
3026 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0            0x0000e0ab
3027 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE  0x80000000
3028 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK        0x00007fff
3029 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT       0
3030 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
3031 {
3032     return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
3033 }
3034 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK        0x7fff0000
3035 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT       16
3036 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
3037 {
3038     return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
3039 }
3040
3041 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0          0x0000e0ca
3042 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE    0x80000000
3043 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK      0x00007fff
3044 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT     0
3045 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
3046 {
3047     return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
3048 }
3049 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK      0x7fff0000
3050 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT     16
3051 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
3052 {
3053     return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
3054 }
3055
3056 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0          0x0000e0cb
3057 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE    0x80000000
3058 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK      0x00007fff
3059 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT     0
3060 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
3061 {
3062     return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
3063 }
3064 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK      0x7fff0000
3065 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT     16
3066 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
3067 {
3068     return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
3069 }
3070
3071 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL          0x0000e0ea
3072 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
3073 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK          0x00007fff
3074 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT         0
3075 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3076 {
3077     return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3078 }
3079 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK          0x7fff0000
3080 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT         16
3081 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3082 {
3083     return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3084 }
3085
3086 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR          0x0000e0eb
3087 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
3088 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK          0x00007fff
3089 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT         0
3090 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3091 {
3092     return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3093 }
3094 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK          0x7fff0000
3095 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT         16
3096 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3097 {
3098     return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3099 }
3100
3101 #define REG_A5XX_GRAS_LRZ_CNTL                  0x0000e100
3102 #define A5XX_GRAS_LRZ_CNTL_ENABLE               0x00000001
3103 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE                0x00000002
3104 #define A5XX_GRAS_LRZ_CNTL_GREATER              0x00000004
3105
3106 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO            0x0000e101
3107
3108 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI            0x0000e102
3109
3110 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH              0x0000e103
3111 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK            0xffffffff
3112 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT           0
3113 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
3114 {
3115     return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
3116 }
3117
3118 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO     0x0000e104
3119
3120 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI     0x0000e105
3121
3122 #define REG_A5XX_RB_CNTL                    0x0000e140
3123 #define A5XX_RB_CNTL_WIDTH__MASK                0x000000ff
3124 #define A5XX_RB_CNTL_WIDTH__SHIFT               0
3125 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
3126 {
3127     return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
3128 }
3129 #define A5XX_RB_CNTL_HEIGHT__MASK               0x0001fe00
3130 #define A5XX_RB_CNTL_HEIGHT__SHIFT              9
3131 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
3132 {
3133     return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
3134 }
3135 #define A5XX_RB_CNTL_BYPASS                 0x00020000
3136
3137 #define REG_A5XX_RB_RENDER_CNTL                 0x0000e141
3138 #define A5XX_RB_RENDER_CNTL_BINNING_PASS            0x00000001
3139 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED          0x00000040
3140 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE          0x00000080
3141 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH              0x00004000
3142 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2             0x00008000
3143 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK         0x00ff0000
3144 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT            16
3145 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3146 {
3147     return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3148 }
3149 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK            0xff000000
3150 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT           24
3151 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
3152 {
3153     return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
3154 }
3155
3156 #define REG_A5XX_RB_RAS_MSAA_CNTL               0x0000e142
3157 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK         0x00000003
3158 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT            0
3159 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3160 {
3161     return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3162 }
3163
3164 #define REG_A5XX_RB_DEST_MSAA_CNTL              0x0000e143
3165 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK            0x00000003
3166 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT           0
3167 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3168 {
3169     return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3170 }
3171 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE         0x00000004
3172
3173 #define REG_A5XX_RB_RENDER_CONTROL0             0x0000e144
3174 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL          0x00000001
3175 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID       0x00000002
3176 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE         0x00000004
3177 #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL         0x00000008
3178 #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID      0x00000010
3179 #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE        0x00000020
3180 #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK        0x000003c0
3181 #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT       6
3182 static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3183 {
3184     return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3185 }
3186
3187 #define REG_A5XX_RB_RENDER_CONTROL1             0x0000e145
3188 #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK          0x00000001
3189 #define A5XX_RB_RENDER_CONTROL1_FACENESS            0x00000002
3190 #define A5XX_RB_RENDER_CONTROL1_SAMPLEID            0x00000004
3191
3192 #define REG_A5XX_RB_FS_OUTPUT_CNTL              0x0000e146
3193 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK            0x0000000f
3194 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT           0
3195 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
3196 {
3197     return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
3198 }
3199 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z            0x00000020
3200
3201 #define REG_A5XX_RB_RENDER_COMPONENTS               0x0000e147
3202 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK         0x0000000f
3203 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT            0
3204 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3205 {
3206     return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
3207 }
3208 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK         0x000000f0
3209 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT            4
3210 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3211 {
3212     return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
3213 }
3214 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK         0x00000f00
3215 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT            8
3216 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3217 {
3218     return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
3219 }
3220 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK         0x0000f000
3221 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT            12
3222 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3223 {
3224     return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
3225 }
3226 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK         0x000f0000
3227 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT            16
3228 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3229 {
3230     return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
3231 }
3232 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK         0x00f00000
3233 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT            20
3234 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3235 {
3236     return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
3237 }
3238 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK         0x0f000000
3239 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT            24
3240 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3241 {
3242     return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
3243 }
3244 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK         0xf0000000
3245 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT            28
3246 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3247 {
3248     return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
3249 }
3250
3251 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3252
3253 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3254 #define A5XX_RB_MRT_CONTROL_BLEND               0x00000001
3255 #define A5XX_RB_MRT_CONTROL_BLEND2              0x00000002
3256 #define A5XX_RB_MRT_CONTROL_ROP_ENABLE              0x00000004
3257 #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK          0x00000078
3258 #define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT         3
3259 static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3260 {
3261     return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3262 }
3263 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK      0x00000780
3264 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT     7
3265 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3266 {
3267     return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3268 }
3269
3270 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
3271 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK      0x0000001f
3272 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT     0
3273 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3274 {
3275     return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3276 }
3277 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK    0x000000e0
3278 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT   5
3279 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3280 {
3281     return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3282 }
3283 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK     0x00001f00
3284 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT    8
3285 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3286 {
3287     return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3288 }
3289 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK    0x001f0000
3290 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT   16
3291 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3292 {
3293     return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3294 }
3295 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK  0x00e00000
3296 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
3297 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3298 {
3299     return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3300 }
3301 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK   0x1f000000
3302 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT  24
3303 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3304 {
3305     return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3306 }
3307
3308 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
3309 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK         0x000000ff
3310 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT        0
3311 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3312 {
3313     return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3314 }
3315 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK      0x00000300
3316 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT     8
3317 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
3318 {
3319     return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3320 }
3321 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK          0x00001800
3322 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT         11
3323 static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
3324 {
3325     return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
3326 }
3327 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK           0x00006000
3328 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT          13
3329 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3330 {
3331     return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3332 }
3333 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB             0x00008000
3334
3335 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
3336 #define A5XX_RB_MRT_PITCH__MASK                 0xffffffff
3337 #define A5XX_RB_MRT_PITCH__SHIFT                0
3338 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
3339 {
3340     return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
3341 }
3342
3343 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
3344 #define A5XX_RB_MRT_ARRAY_PITCH__MASK               0xffffffff
3345 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT              0
3346 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3347 {
3348     return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
3349 }
3350
3351 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
3352
3353 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
3354
3355 #define REG_A5XX_RB_BLEND_RED                   0x0000e1a0
3356 #define A5XX_RB_BLEND_RED_UINT__MASK                0x000000ff
3357 #define A5XX_RB_BLEND_RED_UINT__SHIFT               0
3358 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
3359 {
3360     return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
3361 }
3362 #define A5XX_RB_BLEND_RED_SINT__MASK                0x0000ff00
3363 #define A5XX_RB_BLEND_RED_SINT__SHIFT               8
3364 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3365 {
3366     return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3367 }
3368 #define A5XX_RB_BLEND_RED_FLOAT__MASK               0xffff0000
3369 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT              16
3370 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3371 {
3372     return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3373 }
3374
3375 #define REG_A5XX_RB_BLEND_RED_F32               0x0000e1a1
3376 #define A5XX_RB_BLEND_RED_F32__MASK             0xffffffff
3377 #define A5XX_RB_BLEND_RED_F32__SHIFT                0
3378 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3379 {
3380     return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
3381 }
3382
3383 #define REG_A5XX_RB_BLEND_GREEN                 0x0000e1a2
3384 #define A5XX_RB_BLEND_GREEN_UINT__MASK              0x000000ff
3385 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT             0
3386 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
3387 {
3388     return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
3389 }
3390 #define A5XX_RB_BLEND_GREEN_SINT__MASK              0x0000ff00
3391 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT             8
3392 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3393 {
3394     return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3395 }
3396 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK             0xffff0000
3397 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT            16
3398 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3399 {
3400     return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3401 }
3402
3403 #define REG_A5XX_RB_BLEND_GREEN_F32             0x0000e1a3
3404 #define A5XX_RB_BLEND_GREEN_F32__MASK               0xffffffff
3405 #define A5XX_RB_BLEND_GREEN_F32__SHIFT              0
3406 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3407 {
3408     return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
3409 }
3410
3411 #define REG_A5XX_RB_BLEND_BLUE                  0x0000e1a4
3412 #define A5XX_RB_BLEND_BLUE_UINT__MASK               0x000000ff
3413 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT              0
3414 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
3415 {
3416     return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
3417 }
3418 #define A5XX_RB_BLEND_BLUE_SINT__MASK               0x0000ff00
3419 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT              8
3420 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3421 {
3422     return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3423 }
3424 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK              0xffff0000
3425 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT             16
3426 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3427 {
3428     return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3429 }
3430
3431 #define REG_A5XX_RB_BLEND_BLUE_F32              0x0000e1a5
3432 #define A5XX_RB_BLEND_BLUE_F32__MASK                0xffffffff
3433 #define A5XX_RB_BLEND_BLUE_F32__SHIFT               0
3434 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3435 {
3436     return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
3437 }
3438
3439 #define REG_A5XX_RB_BLEND_ALPHA                 0x0000e1a6
3440 #define A5XX_RB_BLEND_ALPHA_UINT__MASK              0x000000ff
3441 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT             0
3442 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
3443 {
3444     return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
3445 }
3446 #define A5XX_RB_BLEND_ALPHA_SINT__MASK              0x0000ff00
3447 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT             8
3448 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3449 {
3450     return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3451 }
3452 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK             0xffff0000
3453 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT            16
3454 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3455 {
3456     return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3457 }
3458
3459 #define REG_A5XX_RB_BLEND_ALPHA_F32             0x0000e1a7
3460 #define A5XX_RB_BLEND_ALPHA_F32__MASK               0xffffffff
3461 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT              0
3462 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3463 {
3464     return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
3465 }
3466
3467 #define REG_A5XX_RB_ALPHA_CONTROL               0x0000e1a8
3468 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK           0x000000ff
3469 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT          0
3470 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3471 {
3472     return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3473 }
3474 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST            0x00000100
3475 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK     0x00000e00
3476 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT        9
3477 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3478 {
3479     return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3480 }
3481
3482 #define REG_A5XX_RB_BLEND_CNTL                  0x0000e1a9
3483 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK           0x000000ff
3484 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT          0
3485 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3486 {
3487     return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3488 }
3489 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND            0x00000100
3490 #define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE            0x00000400
3491 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK            0xffff0000
3492 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT           16
3493 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3494 {
3495     return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3496 }
3497
3498 #define REG_A5XX_RB_DEPTH_PLANE_CNTL                0x0000e1b0
3499 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z          0x00000001
3500 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1               0x00000002
3501
3502 #define REG_A5XX_RB_DEPTH_CNTL                  0x0000e1b1
3503 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE            0x00000001
3504 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE           0x00000002
3505 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK              0x0000001c
3506 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT             2
3507 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3508 {
3509     return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3510 }
3511 #define A5XX_RB_DEPTH_CNTL_Z_READ_ENABLE            0x00000040
3512
3513 #define REG_A5XX_RB_DEPTH_BUFFER_INFO               0x0000e1b2
3514 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK        0x00000007
3515 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT       0
3516 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
3517 {
3518     return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3519 }
3520
3521 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO            0x0000e1b3
3522
3523 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI            0x0000e1b4
3524
3525 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH              0x0000e1b5
3526 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK            0xffffffff
3527 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT           0
3528 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3529 {
3530     return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
3531 }
3532
3533 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH            0x0000e1b6
3534 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK          0xffffffff
3535 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT         0
3536 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3537 {
3538     return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3539 }
3540
3541 #define REG_A5XX_RB_STENCIL_CONTROL             0x0000e1c0
3542 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE          0x00000001
3543 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF       0x00000002
3544 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ            0x00000004
3545 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK          0x00000700
3546 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT         8
3547 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3548 {
3549     return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
3550 }
3551 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK          0x00003800
3552 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT         11
3553 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3554 {
3555     return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
3556 }
3557 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK         0x0001c000
3558 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT            14
3559 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3560 {
3561     return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3562 }
3563 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK         0x000e0000
3564 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT            17
3565 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3566 {
3567     return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3568 }
3569 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK           0x00700000
3570 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT          20
3571 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3572 {
3573     return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3574 }
3575 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK           0x03800000
3576 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT          23
3577 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3578 {
3579     return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3580 }
3581 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK          0x1c000000
3582 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT         26
3583 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3584 {
3585     return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3586 }
3587 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK          0xe0000000
3588 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT         29
3589 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3590 {
3591     return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3592 }
3593
3594 #define REG_A5XX_RB_STENCIL_INFO                0x0000e1c1
3595 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL           0x00000001
3596
3597 #define REG_A5XX_RB_STENCIL_BASE_LO             0x0000e1c2
3598
3599 #define REG_A5XX_RB_STENCIL_BASE_HI             0x0000e1c3
3600
3601 #define REG_A5XX_RB_STENCIL_PITCH               0x0000e1c4
3602 #define A5XX_RB_STENCIL_PITCH__MASK             0xffffffff
3603 #define A5XX_RB_STENCIL_PITCH__SHIFT                0
3604 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
3605 {
3606     return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
3607 }
3608
3609 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH             0x0000e1c5
3610 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK           0xffffffff
3611 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT          0
3612 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
3613 {
3614     return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
3615 }
3616
3617 #define REG_A5XX_RB_STENCILREFMASK              0x0000e1c6
3618 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK         0x000000ff
3619 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT        0
3620 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
3621 {
3622     return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
3623 }
3624 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK        0x0000ff00
3625 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT       8
3626 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
3627 {
3628     return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
3629 }
3630 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK       0x00ff0000
3631 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT      16
3632 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
3633 {
3634     return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
3635 }
3636
3637 #define REG_A5XX_RB_STENCILREFMASK_BF               0x0000e1c7
3638 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK      0x000000ff
3639 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT     0
3640 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
3641 {
3642     return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
3643 }
3644 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK     0x0000ff00
3645 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT        8
3646 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
3647 {
3648     return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
3649 }
3650 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK    0x00ff0000
3651 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT   16
3652 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
3653 {
3654     return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
3655 }
3656
3657 #define REG_A5XX_RB_WINDOW_OFFSET               0x0000e1d0
3658 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE     0x80000000
3659 #define A5XX_RB_WINDOW_OFFSET_X__MASK               0x00007fff
3660 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT              0
3661 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
3662 {
3663     return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
3664 }
3665 #define A5XX_RB_WINDOW_OFFSET_Y__MASK               0x7fff0000
3666 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT              16
3667 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3668 {
3669     return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
3670 }
3671
3672 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL            0x0000e1d1
3673 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY           0x00000002
3674
3675 #define REG_A5XX_RB_BLIT_CNTL                   0x0000e210
3676 #define A5XX_RB_BLIT_CNTL_BUF__MASK             0x0000000f
3677 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT                0
3678 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
3679 {
3680     return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
3681 }
3682
3683 #define REG_A5XX_RB_RESOLVE_CNTL_1              0x0000e211
3684 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE        0x80000000
3685 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK              0x00007fff
3686 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT             0
3687 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
3688 {
3689     return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
3690 }
3691 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK              0x7fff0000
3692 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT             16
3693 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
3694 {
3695     return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
3696 }
3697
3698 #define REG_A5XX_RB_RESOLVE_CNTL_2              0x0000e212
3699 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE        0x80000000
3700 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK              0x00007fff
3701 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT             0
3702 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
3703 {
3704     return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
3705 }
3706 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK              0x7fff0000
3707 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT             16
3708 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
3709 {
3710     return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
3711 }
3712
3713 #define REG_A5XX_RB_RESOLVE_CNTL_3              0x0000e213
3714 #define A5XX_RB_RESOLVE_CNTL_3_TILED                0x00000001
3715
3716 #define REG_A5XX_RB_BLIT_DST_LO                 0x0000e214
3717
3718 #define REG_A5XX_RB_BLIT_DST_HI                 0x0000e215
3719
3720 #define REG_A5XX_RB_BLIT_DST_PITCH              0x0000e216
3721 #define A5XX_RB_BLIT_DST_PITCH__MASK                0xffffffff
3722 #define A5XX_RB_BLIT_DST_PITCH__SHIFT               0
3723 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
3724 {
3725     return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
3726 }
3727
3728 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH            0x0000e217
3729 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK          0xffffffff
3730 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT         0
3731 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3732 {
3733     return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3734 }
3735
3736 #define REG_A5XX_RB_CLEAR_COLOR_DW0             0x0000e218
3737
3738 #define REG_A5XX_RB_CLEAR_COLOR_DW1             0x0000e219
3739
3740 #define REG_A5XX_RB_CLEAR_COLOR_DW2             0x0000e21a
3741
3742 #define REG_A5XX_RB_CLEAR_COLOR_DW3             0x0000e21b
3743
3744 #define REG_A5XX_RB_CLEAR_CNTL                  0x0000e21c
3745 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR               0x00000002
3746 #define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE             0x00000004
3747 #define A5XX_RB_CLEAR_CNTL_MASK__MASK               0x000000f0
3748 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT              4
3749 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
3750 {
3751     return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
3752 }
3753
3754 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO           0x0000e240
3755
3756 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI           0x0000e241
3757
3758 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH         0x0000e242
3759
3760 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3761
3762 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3763
3764 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
3765
3766 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
3767 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK         0xffffffff
3768 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT            0
3769 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
3770 {
3771     return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
3772 }
3773
3774 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
3775 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK       0xffffffff
3776 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT      0
3777 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
3778 {
3779     return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
3780 }
3781
3782 #define REG_A5XX_RB_BLIT_FLAG_DST_LO                0x0000e263
3783
3784 #define REG_A5XX_RB_BLIT_FLAG_DST_HI                0x0000e264
3785
3786 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH             0x0000e265
3787 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK           0xffffffff
3788 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT          0
3789 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
3790 {
3791     return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
3792 }
3793
3794 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH           0x0000e266
3795 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK         0xffffffff
3796 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT        0
3797 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
3798 {
3799     return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
3800 }
3801
3802 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO            0x0000e267
3803
3804 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI            0x0000e268
3805
3806 #define REG_A5XX_VPC_CNTL_0                 0x0000e280
3807 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK         0x0000007f
3808 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT            0
3809 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
3810 {
3811     return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
3812 }
3813 #define A5XX_VPC_CNTL_0_VARYING                 0x00000800
3814
3815 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3816
3817 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3818
3819 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3820
3821 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3822
3823 #define REG_A5XX_UNKNOWN_E292                   0x0000e292
3824
3825 #define REG_A5XX_UNKNOWN_E293                   0x0000e293
3826
3827 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3828
3829 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3830
3831 #define REG_A5XX_VPC_GS_SIV_CNTL                0x0000e298
3832
3833 #define REG_A5XX_VPC_CLIP_CNTL                  0x0000e29a
3834 #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK          0x000000ff
3835 #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT         0
3836 static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3837 {
3838     return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
3839 }
3840 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK       0x0000ff00
3841 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT      8
3842 static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
3843 {
3844     return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
3845 }
3846 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK       0x00ff0000
3847 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT      16
3848 static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
3849 {
3850     return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
3851 }
3852
3853 #define REG_A5XX_VPC_PACK                   0x0000e29d
3854 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK            0x000000ff
3855 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT           0
3856 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3857 {
3858     return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3859 }
3860 #define A5XX_VPC_PACK_PSIZELOC__MASK                0x0000ff00
3861 #define A5XX_VPC_PACK_PSIZELOC__SHIFT               8
3862 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
3863 {
3864     return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
3865 }
3866
3867 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL            0x0000e2a0
3868
3869 #define REG_A5XX_VPC_SO_BUF_CNTL                0x0000e2a1
3870 #define A5XX_VPC_SO_BUF_CNTL_BUF0               0x00000001
3871 #define A5XX_VPC_SO_BUF_CNTL_BUF1               0x00000008
3872 #define A5XX_VPC_SO_BUF_CNTL_BUF2               0x00000040
3873 #define A5XX_VPC_SO_BUF_CNTL_BUF3               0x00000200
3874 #define A5XX_VPC_SO_BUF_CNTL_ENABLE             0x00008000
3875
3876 #define REG_A5XX_VPC_SO_OVERRIDE                0x0000e2a2
3877 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE             0x00000001
3878
3879 #define REG_A5XX_VPC_SO_CNTL                    0x0000e2a3
3880 #define A5XX_VPC_SO_CNTL_ENABLE                 0x00010000
3881
3882 #define REG_A5XX_VPC_SO_PROG                    0x0000e2a4
3883 #define A5XX_VPC_SO_PROG_A_BUF__MASK                0x00000003
3884 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT               0
3885 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
3886 {
3887     return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
3888 }
3889 #define A5XX_VPC_SO_PROG_A_OFF__MASK                0x000007fc
3890 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT               2
3891 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
3892 {
3893     return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
3894 }
3895 #define A5XX_VPC_SO_PROG_A_EN                   0x00000800
3896 #define A5XX_VPC_SO_PROG_B_BUF__MASK                0x00003000
3897 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT               12
3898 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
3899 {
3900     return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
3901 }
3902 #define A5XX_VPC_SO_PROG_B_OFF__MASK                0x007fc000
3903 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT               14
3904 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
3905 {
3906     return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
3907 }
3908 #define A5XX_VPC_SO_PROG_B_EN                   0x00800000
3909
3910 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3911
3912 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3913
3914 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
3915
3916 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
3917
3918 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
3919
3920 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
3921
3922 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
3923
3924 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
3925
3926 #define REG_A5XX_PC_PRIMITIVE_CNTL              0x0000e384
3927 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK      0x0000007f
3928 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT     0
3929 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3930 {
3931     return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3932 }
3933 #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART        0x00000100
3934 #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES         0x00000200
3935 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST       0x00000400
3936
3937 #define REG_A5XX_PC_PRIM_VTX_CNTL               0x0000e385
3938 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE             0x00000800
3939
3940 #define REG_A5XX_PC_RASTER_CNTL                 0x0000e388
3941 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK      0x00000007
3942 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT     0
3943 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3944 {
3945     return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK;
3946 }
3947 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK       0x00000038
3948 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT      3
3949 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3950 {
3951     return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
3952 }
3953 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE         0x00000040
3954
3955 #define REG_A5XX_PC_CLIP_CNTL                   0x0000e389
3956 #define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK           0x000000ff
3957 #define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT          0
3958 static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3959 {
3960     return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
3961 }
3962
3963 #define REG_A5XX_PC_RESTART_INDEX               0x0000e38c
3964
3965 #define REG_A5XX_PC_GS_LAYERED                  0x0000e38d
3966
3967 #define REG_A5XX_PC_GS_PARAM                    0x0000e38e
3968 #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK         0x000003ff
3969 #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT            0
3970 static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3971 {
3972     return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3973 }
3974 #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK          0x0000f800
3975 #define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT         11
3976 static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3977 {
3978     return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK;
3979 }
3980 #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK             0x01800000
3981 #define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT            23
3982 static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3983 {
3984     return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK;
3985 }
3986
3987 #define REG_A5XX_PC_HS_PARAM                    0x0000e38f
3988 #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK         0x0000003f
3989 #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT            0
3990 static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3991 {
3992     return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3993 }
3994 #define A5XX_PC_HS_PARAM_SPACING__MASK              0x00600000
3995 #define A5XX_PC_HS_PARAM_SPACING__SHIFT             21
3996 static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3997 {
3998     return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK;
3999 }
4000 #define A5XX_PC_HS_PARAM_CW                 0x00800000
4001 #define A5XX_PC_HS_PARAM_CONNECTED              0x01000000
4002
4003 #define REG_A5XX_PC_POWER_CNTL                  0x0000e3b0
4004
4005 #define REG_A5XX_VFD_CONTROL_0                  0x0000e400
4006 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK             0x0000003f
4007 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT            0
4008 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
4009 {
4010     return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
4011 }
4012
4013 #define REG_A5XX_VFD_CONTROL_1                  0x0000e401
4014 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK          0x000000ff
4015 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT         0
4016 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
4017 {
4018     return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
4019 }
4020 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK         0x0000ff00
4021 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT            8
4022 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
4023 {
4024     return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
4025 }
4026 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK           0x00ff0000
4027 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT          16
4028 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4029 {
4030     return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4031 }
4032
4033 #define REG_A5XX_VFD_CONTROL_2                  0x0000e402
4034 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK          0x000000ff
4035 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT         0
4036 static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
4037 {
4038     return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
4039 }
4040
4041 #define REG_A5XX_VFD_CONTROL_3                  0x0000e403
4042 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK          0x0000ff00
4043 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT         8
4044 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
4045 {
4046     return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
4047 }
4048 #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK            0x00ff0000
4049 #define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT           16
4050 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4051 {
4052     return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4053 }
4054 #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK            0xff000000
4055 #define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT           24
4056 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4057 {
4058     return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4059 }
4060
4061 #define REG_A5XX_VFD_CONTROL_4                  0x0000e404
4062
4063 #define REG_A5XX_VFD_CONTROL_5                  0x0000e405
4064
4065 #define REG_A5XX_VFD_INDEX_OFFSET               0x0000e408
4066
4067 #define REG_A5XX_VFD_INSTANCE_START_OFFSET          0x0000e409
4068
4069 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
4070
4071 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
4072
4073 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
4074
4075 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
4076
4077 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
4078
4079 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
4080
4081 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
4082 #define A5XX_VFD_DECODE_INSTR_IDX__MASK             0x0000001f
4083 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT            0
4084 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
4085 {
4086     return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
4087 }
4088 #define A5XX_VFD_DECODE_INSTR_INSTANCED             0x00020000
4089 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK          0x0ff00000
4090 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT         20
4091 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
4092 {
4093     return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
4094 }
4095 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK            0x30000000
4096 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT           28
4097 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
4098 {
4099     return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
4100 }
4101 #define A5XX_VFD_DECODE_INSTR_UNK30             0x40000000
4102 #define A5XX_VFD_DECODE_INSTR_FLOAT             0x80000000
4103
4104 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
4105
4106 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
4107
4108 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
4109 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK        0x0000000f
4110 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT       0
4111 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
4112 {
4113     return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
4114 }
4115 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK            0x00000ff0
4116 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT           4
4117 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
4118 {
4119     return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
4120 }
4121
4122 #define REG_A5XX_VFD_POWER_CNTL                 0x0000e4f0
4123
4124 #define REG_A5XX_SP_SP_CNTL                 0x0000e580
4125
4126 #define REG_A5XX_SP_VS_CONFIG                   0x0000e584
4127 #define A5XX_SP_VS_CONFIG_ENABLED               0x00000001
4128 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK       0x000000fe
4129 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT      1
4130 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4131 {
4132     return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4133 }
4134 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK         0x00007f00
4135 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT        8
4136 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4137 {
4138     return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
4139 }
4140
4141 #define REG_A5XX_SP_FS_CONFIG                   0x0000e585
4142 #define A5XX_SP_FS_CONFIG_ENABLED               0x00000001
4143 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK       0x000000fe
4144 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT      1
4145 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4146 {
4147     return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4148 }
4149 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK         0x00007f00
4150 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT        8
4151 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4152 {
4153     return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
4154 }
4155
4156 #define REG_A5XX_SP_HS_CONFIG                   0x0000e586
4157 #define A5XX_SP_HS_CONFIG_ENABLED               0x00000001
4158 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK       0x000000fe
4159 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT      1
4160 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4161 {
4162     return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4163 }
4164 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK         0x00007f00
4165 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT        8
4166 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4167 {
4168     return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
4169 }
4170
4171 #define REG_A5XX_SP_DS_CONFIG                   0x0000e587
4172 #define A5XX_SP_DS_CONFIG_ENABLED               0x00000001
4173 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK       0x000000fe
4174 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT      1
4175 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4176 {
4177     return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4178 }
4179 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK         0x00007f00
4180 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT        8
4181 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4182 {
4183     return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
4184 }
4185
4186 #define REG_A5XX_SP_GS_CONFIG                   0x0000e588
4187 #define A5XX_SP_GS_CONFIG_ENABLED               0x00000001
4188 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK       0x000000fe
4189 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT      1
4190 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4191 {
4192     return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4193 }
4194 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK         0x00007f00
4195 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT        8
4196 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4197 {
4198     return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
4199 }
4200
4201 #define REG_A5XX_SP_CS_CONFIG                   0x0000e589
4202 #define A5XX_SP_CS_CONFIG_ENABLED               0x00000001
4203 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK       0x000000fe
4204 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT      1
4205 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4206 {
4207     return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4208 }
4209 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK         0x00007f00
4210 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT        8
4211 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4212 {
4213     return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
4214 }
4215
4216 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST             0x0000e58a
4217
4218 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST             0x0000e58b
4219
4220 #define REG_A5XX_SP_VS_CTRL_REG0                0x0000e590
4221 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK           0x00000008
4222 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT          3
4223 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4224 {
4225     return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4226 }
4227 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x000003f0
4228 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        4
4229 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4230 {
4231     return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4232 }
4233 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x0000fc00
4234 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        10
4235 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4236 {
4237     return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4238 }
4239 #define A5XX_SP_VS_CTRL_REG0_VARYING                0x00010000
4240 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE           0x00100000
4241 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK          0xfe000000
4242 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT         25
4243 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4244 {
4245     return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4246 }
4247
4248 #define REG_A5XX_SP_PRIMITIVE_CNTL              0x0000e592
4249 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK          0x0000001f
4250 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT         0
4251 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
4252 {
4253     return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
4254 }
4255
4256 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4257
4258 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4259 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK            0x000000ff
4260 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT           0
4261 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4262 {
4263     return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
4264 }
4265 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK         0x00000f00
4266 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT            8
4267 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4268 {
4269     return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4270 }
4271 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK            0x00ff0000
4272 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT           16
4273 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4274 {
4275     return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
4276 }
4277 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK         0x0f000000
4278 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT            24
4279 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4280 {
4281     return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4282 }
4283
4284 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4285
4286 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4287 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK            0x000000ff
4288 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT           0
4289 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
4290 {
4291     return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4292 }
4293 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK            0x0000ff00
4294 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT           8
4295 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4296 {
4297     return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4298 }
4299 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK            0x00ff0000
4300 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT           16
4301 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4302 {
4303     return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4304 }
4305 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK            0xff000000
4306 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT           24
4307 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4308 {
4309     return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4310 }
4311
4312 #define REG_A5XX_UNKNOWN_E5AB                   0x0000e5ab
4313
4314 #define REG_A5XX_SP_VS_OBJ_START_LO             0x0000e5ac
4315
4316 #define REG_A5XX_SP_VS_OBJ_START_HI             0x0000e5ad
4317
4318 #define REG_A5XX_SP_FS_CTRL_REG0                0x0000e5c0
4319 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK           0x00000008
4320 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT          3
4321 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4322 {
4323     return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4324 }
4325 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x000003f0
4326 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        4
4327 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4328 {
4329     return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4330 }
4331 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x0000fc00
4332 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        10
4333 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4334 {
4335     return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4336 }
4337 #define A5XX_SP_FS_CTRL_REG0_VARYING                0x00010000
4338 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE           0x00100000
4339 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK          0xfe000000
4340 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT         25
4341 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4342 {
4343     return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4344 }
4345
4346 #define REG_A5XX_UNKNOWN_E5C2                   0x0000e5c2
4347
4348 #define REG_A5XX_SP_FS_OBJ_START_LO             0x0000e5c3
4349
4350 #define REG_A5XX_SP_FS_OBJ_START_HI             0x0000e5c4
4351
4352 #define REG_A5XX_SP_BLEND_CNTL                  0x0000e5c9
4353 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK           0x000000ff
4354 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT          0
4355 static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
4356 {
4357     return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
4358 }
4359 #define A5XX_SP_BLEND_CNTL_UNK8                 0x00000100
4360 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE            0x00000400
4361
4362 #define REG_A5XX_SP_FS_OUTPUT_CNTL              0x0000e5ca
4363 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK            0x0000000f
4364 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT           0
4365 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4366 {
4367     return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
4368 }
4369 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK        0x00001fe0
4370 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT       5
4371 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
4372 {
4373     return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
4374 }
4375 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK       0x001fe000
4376 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT      13
4377 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
4378 {
4379     return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
4380 }
4381
4382 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4383
4384 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4385 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK           0x000000ff
4386 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT          0
4387 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4388 {
4389     return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
4390 }
4391 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION            0x00000100
4392
4393 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4394
4395 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4396 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK           0x000000ff
4397 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT          0
4398 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
4399 {
4400     return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4401 }
4402 #define A5XX_SP_FS_MRT_REG_COLOR_SINT               0x00000100
4403 #define A5XX_SP_FS_MRT_REG_COLOR_UINT               0x00000200
4404 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB               0x00000400
4405
4406 #define REG_A5XX_UNKNOWN_E5DB                   0x0000e5db
4407
4408 #define REG_A5XX_SP_CS_CTRL_REG0                0x0000e5f0
4409 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK           0x00000008
4410 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT          3
4411 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4412 {
4413     return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4414 }
4415 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x000003f0
4416 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        4
4417 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4418 {
4419     return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4420 }
4421 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x0000fc00
4422 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        10
4423 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4424 {
4425     return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4426 }
4427 #define A5XX_SP_CS_CTRL_REG0_VARYING                0x00010000
4428 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE           0x00100000
4429 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK          0xfe000000
4430 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT         25
4431 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4432 {
4433     return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4434 }
4435
4436 #define REG_A5XX_UNKNOWN_E5F2                   0x0000e5f2
4437
4438 #define REG_A5XX_SP_CS_OBJ_START_LO             0x0000e5f3
4439
4440 #define REG_A5XX_SP_CS_OBJ_START_HI             0x0000e5f4
4441
4442 #define REG_A5XX_SP_HS_CTRL_REG0                0x0000e600
4443 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK           0x00000008
4444 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT          3
4445 static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4446 {
4447     return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
4448 }
4449 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x000003f0
4450 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        4
4451 static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4452 {
4453     return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4454 }
4455 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x0000fc00
4456 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        10
4457 static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4458 {
4459     return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4460 }
4461 #define A5XX_SP_HS_CTRL_REG0_VARYING                0x00010000
4462 #define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE           0x00100000
4463 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK          0xfe000000
4464 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT         25
4465 static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4466 {
4467     return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
4468 }
4469
4470 #define REG_A5XX_UNKNOWN_E602                   0x0000e602
4471
4472 #define REG_A5XX_SP_HS_OBJ_START_LO             0x0000e603
4473
4474 #define REG_A5XX_SP_HS_OBJ_START_HI             0x0000e604
4475
4476 #define REG_A5XX_SP_DS_CTRL_REG0                0x0000e610
4477 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK           0x00000008
4478 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT          3
4479 static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4480 {
4481     return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
4482 }
4483 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x000003f0
4484 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        4
4485 static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4486 {
4487     return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4488 }
4489 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x0000fc00
4490 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        10
4491 static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4492 {
4493     return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4494 }
4495 #define A5XX_SP_DS_CTRL_REG0_VARYING                0x00010000
4496 #define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE           0x00100000
4497 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK          0xfe000000
4498 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT         25
4499 static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4500 {
4501     return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
4502 }
4503
4504 #define REG_A5XX_UNKNOWN_E62B                   0x0000e62b
4505
4506 #define REG_A5XX_SP_DS_OBJ_START_LO             0x0000e62c
4507
4508 #define REG_A5XX_SP_DS_OBJ_START_HI             0x0000e62d
4509
4510 #define REG_A5XX_SP_GS_CTRL_REG0                0x0000e640
4511 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK           0x00000008
4512 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT          3
4513 static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4514 {
4515     return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
4516 }
4517 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK     0x000003f0
4518 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT        4
4519 static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4520 {
4521     return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4522 }
4523 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK     0x0000fc00
4524 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT        10
4525 static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4526 {
4527     return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4528 }
4529 #define A5XX_SP_GS_CTRL_REG0_VARYING                0x00010000
4530 #define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE           0x00100000
4531 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK          0xfe000000
4532 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT         25
4533 static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4534 {
4535     return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
4536 }
4537
4538 #define REG_A5XX_UNKNOWN_E65B                   0x0000e65b
4539
4540 #define REG_A5XX_SP_GS_OBJ_START_LO             0x0000e65c
4541
4542 #define REG_A5XX_SP_GS_OBJ_START_HI             0x0000e65d
4543
4544 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL              0x0000e704
4545 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK        0x00000003
4546 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT       0
4547 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4548 {
4549     return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4550 }
4551
4552 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL             0x0000e705
4553 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK       0x00000003
4554 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT      0
4555 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4556 {
4557     return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4558 }
4559 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE        0x00000004
4560
4561 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO      0x0000e706
4562
4563 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI      0x0000e707
4564
4565 #define REG_A5XX_TPL1_VS_TEX_COUNT              0x0000e700
4566
4567 #define REG_A5XX_TPL1_HS_TEX_COUNT              0x0000e701
4568
4569 #define REG_A5XX_TPL1_DS_TEX_COUNT              0x0000e702
4570
4571 #define REG_A5XX_TPL1_GS_TEX_COUNT              0x0000e703
4572
4573 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO                0x0000e722
4574
4575 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI                0x0000e723
4576
4577 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO                0x0000e724
4578
4579 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI                0x0000e725
4580
4581 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO                0x0000e726
4582
4583 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI                0x0000e727
4584
4585 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO                0x0000e728
4586
4587 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI                0x0000e729
4588
4589 #define REG_A5XX_TPL1_VS_TEX_CONST_LO               0x0000e72a
4590
4591 #define REG_A5XX_TPL1_VS_TEX_CONST_HI               0x0000e72b
4592
4593 #define REG_A5XX_TPL1_HS_TEX_CONST_LO               0x0000e72c
4594
4595 #define REG_A5XX_TPL1_HS_TEX_CONST_HI               0x0000e72d
4596
4597 #define REG_A5XX_TPL1_DS_TEX_CONST_LO               0x0000e72e
4598
4599 #define REG_A5XX_TPL1_DS_TEX_CONST_HI               0x0000e72f
4600
4601 #define REG_A5XX_TPL1_GS_TEX_CONST_LO               0x0000e730
4602
4603 #define REG_A5XX_TPL1_GS_TEX_CONST_HI               0x0000e731
4604
4605 #define REG_A5XX_TPL1_FS_TEX_COUNT              0x0000e750
4606
4607 #define REG_A5XX_TPL1_CS_TEX_COUNT              0x0000e751
4608
4609 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO                0x0000e75a
4610
4611 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI                0x0000e75b
4612
4613 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO                0x0000e75c
4614
4615 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI                0x0000e75d
4616
4617 #define REG_A5XX_TPL1_FS_TEX_CONST_LO               0x0000e75e
4618
4619 #define REG_A5XX_TPL1_FS_TEX_CONST_HI               0x0000e75f
4620
4621 #define REG_A5XX_TPL1_CS_TEX_CONST_LO               0x0000e760
4622
4623 #define REG_A5XX_TPL1_CS_TEX_CONST_HI               0x0000e761
4624
4625 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL           0x0000e764
4626
4627 #define REG_A5XX_HLSQ_CONTROL_0_REG             0x0000e784
4628 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK      0x00000001
4629 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT     0
4630 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
4631 {
4632     return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
4633 }
4634 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK      0x00000004
4635 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT     2
4636 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
4637 {
4638     return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
4639 }
4640
4641 #define REG_A5XX_HLSQ_CONTROL_1_REG             0x0000e785
4642 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK    0x0000003f
4643 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT   0
4644 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
4645 {
4646     return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
4647 }
4648
4649 #define REG_A5XX_HLSQ_CONTROL_2_REG             0x0000e786
4650 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK         0x000000ff
4651 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT        0
4652 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4653 {
4654     return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4655 }
4656 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK          0x0000ff00
4657 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT         8
4658 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
4659 {
4660     return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
4661 }
4662 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK        0x00ff0000
4663 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT       16
4664 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
4665 {
4666     return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
4667 }
4668 #define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK          0xff000000
4669 #define A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT         24
4670 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
4671 {
4672     return ((val) << A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
4673 }
4674
4675 #define REG_A5XX_HLSQ_CONTROL_3_REG             0x0000e787
4676 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK        0x000000ff
4677 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT       0
4678 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
4679 {
4680     return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
4681 }
4682 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK       0x0000ff00
4683 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT      8
4684 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
4685 {
4686     return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
4687 }
4688 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK     0x00ff0000
4689 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT    16
4690 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
4691 {
4692     return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
4693 }
4694 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK    0xff000000
4695 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT   24
4696 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
4697 {
4698     return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
4699 }
4700
4701 #define REG_A5XX_HLSQ_CONTROL_4_REG             0x0000e788
4702 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK       0x000000ff
4703 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT      0
4704 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
4705 {
4706     return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
4707 }
4708 #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK      0x0000ff00
4709 #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT     8
4710 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
4711 {
4712     return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
4713 }
4714 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK      0x00ff0000
4715 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT     16
4716 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4717 {
4718     return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4719 }
4720 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK      0xff000000
4721 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT     24
4722 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4723 {
4724     return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4725 }
4726
4727 #define REG_A5XX_HLSQ_UPDATE_CNTL               0x0000e78a
4728
4729 #define REG_A5XX_HLSQ_VS_CONFIG                 0x0000e78b
4730 #define A5XX_HLSQ_VS_CONFIG_ENABLED             0x00000001
4731 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK     0x000000fe
4732 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT        1
4733 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4734 {
4735     return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4736 }
4737 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK       0x00007f00
4738 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT      8
4739 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4740 {
4741     return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
4742 }
4743
4744 #define REG_A5XX_HLSQ_FS_CONFIG                 0x0000e78c
4745 #define A5XX_HLSQ_FS_CONFIG_ENABLED             0x00000001
4746 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK     0x000000fe
4747 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT        1
4748 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4749 {
4750     return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4751 }
4752 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK       0x00007f00
4753 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT      8
4754 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4755 {
4756     return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
4757 }
4758
4759 #define REG_A5XX_HLSQ_HS_CONFIG                 0x0000e78d
4760 #define A5XX_HLSQ_HS_CONFIG_ENABLED             0x00000001
4761 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK     0x000000fe
4762 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT        1
4763 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4764 {
4765     return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4766 }
4767 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK       0x00007f00
4768 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT      8
4769 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4770 {
4771     return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
4772 }
4773
4774 #define REG_A5XX_HLSQ_DS_CONFIG                 0x0000e78e
4775 #define A5XX_HLSQ_DS_CONFIG_ENABLED             0x00000001
4776 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK     0x000000fe
4777 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT        1
4778 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4779 {
4780     return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4781 }
4782 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK       0x00007f00
4783 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT      8
4784 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4785 {
4786     return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
4787 }
4788
4789 #define REG_A5XX_HLSQ_GS_CONFIG                 0x0000e78f
4790 #define A5XX_HLSQ_GS_CONFIG_ENABLED             0x00000001
4791 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK     0x000000fe
4792 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT        1
4793 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4794 {
4795     return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4796 }
4797 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK       0x00007f00
4798 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT      8
4799 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4800 {
4801     return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
4802 }
4803
4804 #define REG_A5XX_HLSQ_CS_CONFIG                 0x0000e790
4805 #define A5XX_HLSQ_CS_CONFIG_ENABLED             0x00000001
4806 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK     0x000000fe
4807 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT        1
4808 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4809 {
4810     return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4811 }
4812 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK       0x00007f00
4813 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT      8
4814 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4815 {
4816     return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
4817 }
4818
4819 #define REG_A5XX_HLSQ_VS_CNTL                   0x0000e791
4820 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE               0x00000001
4821 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK            0xfffffffe
4822 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT           1
4823 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
4824 {
4825     return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
4826 }
4827
4828 #define REG_A5XX_HLSQ_FS_CNTL                   0x0000e792
4829 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE               0x00000001
4830 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK            0xfffffffe
4831 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT           1
4832 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
4833 {
4834     return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
4835 }
4836
4837 #define REG_A5XX_HLSQ_HS_CNTL                   0x0000e793
4838 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE               0x00000001
4839 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK            0xfffffffe
4840 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT           1
4841 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
4842 {
4843     return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
4844 }
4845
4846 #define REG_A5XX_HLSQ_DS_CNTL                   0x0000e794
4847 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE               0x00000001
4848 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK            0xfffffffe
4849 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT           1
4850 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
4851 {
4852     return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
4853 }
4854
4855 #define REG_A5XX_HLSQ_GS_CNTL                   0x0000e795
4856 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE               0x00000001
4857 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK            0xfffffffe
4858 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT           1
4859 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
4860 {
4861     return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
4862 }
4863
4864 #define REG_A5XX_HLSQ_CS_CNTL                   0x0000e796
4865 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE               0x00000001
4866 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK            0xfffffffe
4867 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT           1
4868 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
4869 {
4870     return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
4871 }
4872
4873 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X             0x0000e7b9
4874
4875 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y             0x0000e7ba
4876
4877 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z             0x0000e7bb
4878
4879 #define REG_A5XX_HLSQ_CS_NDRANGE_0              0x0000e7b0
4880 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK          0x00000003
4881 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT         0
4882 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4883 {
4884     return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4885 }
4886 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK         0x00000ffc
4887 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT        2
4888 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4889 {
4890     return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4891 }
4892 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK         0x003ff000
4893 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT        12
4894 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4895 {
4896     return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4897 }
4898 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK         0xffc00000
4899 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT        22
4900 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4901 {
4902     return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4903 }
4904
4905 #define REG_A5XX_HLSQ_CS_NDRANGE_1              0x0000e7b1
4906 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK       0xffffffff
4907 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT      0
4908 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
4909 {
4910     return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
4911 }
4912
4913 #define REG_A5XX_HLSQ_CS_NDRANGE_2              0x0000e7b2
4914 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK        0xffffffff
4915 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT       0
4916 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
4917 {
4918     return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
4919 }
4920
4921 #define REG_A5XX_HLSQ_CS_NDRANGE_3              0x0000e7b3
4922 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK       0xffffffff
4923 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT      0
4924 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
4925 {
4926     return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
4927 }
4928
4929 #define REG_A5XX_HLSQ_CS_NDRANGE_4              0x0000e7b4
4930 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK        0xffffffff
4931 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT       0
4932 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
4933 {
4934     return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
4935 }
4936
4937 #define REG_A5XX_HLSQ_CS_NDRANGE_5              0x0000e7b5
4938 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK       0xffffffff
4939 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT      0
4940 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
4941 {
4942     return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
4943 }
4944
4945 #define REG_A5XX_HLSQ_CS_NDRANGE_6              0x0000e7b6
4946 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK        0xffffffff
4947 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT       0
4948 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
4949 {
4950     return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
4951 }
4952
4953 #define REG_A5XX_HLSQ_CS_CNTL_0                 0x0000e7b7
4954 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK           0x000000ff
4955 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT          0
4956 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4957 {
4958     return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4959 }
4960 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK              0x0000ff00
4961 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT             8
4962 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4963 {
4964     return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4965 }
4966 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK              0x00ff0000
4967 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT             16
4968 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4969 {
4970     return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4971 }
4972 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK          0xff000000
4973 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT         24
4974 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4975 {
4976     return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4977 }
4978
4979 #define REG_A5XX_HLSQ_CS_CNTL_1                 0x0000e7b8
4980
4981 #define REG_A5XX_UNKNOWN_E7C0                   0x0000e7c0
4982
4983 #define REG_A5XX_HLSQ_VS_CONSTLEN               0x0000e7c3
4984
4985 #define REG_A5XX_HLSQ_VS_INSTRLEN               0x0000e7c4
4986
4987 #define REG_A5XX_UNKNOWN_E7C5                   0x0000e7c5
4988
4989 #define REG_A5XX_HLSQ_HS_CONSTLEN               0x0000e7c8
4990
4991 #define REG_A5XX_HLSQ_HS_INSTRLEN               0x0000e7c9
4992
4993 #define REG_A5XX_UNKNOWN_E7CA                   0x0000e7ca
4994
4995 #define REG_A5XX_HLSQ_DS_CONSTLEN               0x0000e7cd
4996
4997 #define REG_A5XX_HLSQ_DS_INSTRLEN               0x0000e7ce
4998
4999 #define REG_A5XX_UNKNOWN_E7CF                   0x0000e7cf
5000
5001 #define REG_A5XX_HLSQ_GS_CONSTLEN               0x0000e7d2
5002
5003 #define REG_A5XX_HLSQ_GS_INSTRLEN               0x0000e7d3
5004
5005 #define REG_A5XX_UNKNOWN_E7D4                   0x0000e7d4
5006
5007 #define REG_A5XX_HLSQ_FS_CONSTLEN               0x0000e7d7
5008
5009 #define REG_A5XX_HLSQ_FS_INSTRLEN               0x0000e7d8
5010
5011 #define REG_A5XX_UNKNOWN_E7D9                   0x0000e7d9
5012
5013 #define REG_A5XX_HLSQ_CS_CONSTLEN               0x0000e7dc
5014
5015 #define REG_A5XX_HLSQ_CS_INSTRLEN               0x0000e7dd
5016
5017 #define REG_A5XX_RB_2D_BLIT_CNTL                0x00002100
5018
5019 #define REG_A5XX_RB_2D_SRC_SOLID_DW0                0x00002101
5020
5021 #define REG_A5XX_RB_2D_SRC_SOLID_DW1                0x00002102
5022
5023 #define REG_A5XX_RB_2D_SRC_SOLID_DW2                0x00002103
5024
5025 #define REG_A5XX_RB_2D_SRC_SOLID_DW3                0x00002104
5026
5027 #define REG_A5XX_RB_2D_SRC_INFO                 0x00002107
5028 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK          0x000000ff
5029 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT         0
5030 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5031 {
5032     return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
5033 }
5034 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK         0x00000300
5035 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT            8
5036 static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
5037 {
5038     return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK;
5039 }
5040 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK            0x00000c00
5041 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT           10
5042 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5043 {
5044     return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
5045 }
5046 #define A5XX_RB_2D_SRC_INFO_FLAGS               0x00001000
5047 #define A5XX_RB_2D_SRC_INFO_SRGB                0x00002000
5048
5049 #define REG_A5XX_RB_2D_SRC_LO                   0x00002108
5050
5051 #define REG_A5XX_RB_2D_SRC_HI                   0x00002109
5052
5053 #define REG_A5XX_RB_2D_SRC_SIZE                 0x0000210a
5054 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK             0x0000ffff
5055 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT            0
5056 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
5057 {
5058     return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
5059 }
5060 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK           0xffff0000
5061 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT          16
5062 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
5063 {
5064     return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
5065 }
5066
5067 #define REG_A5XX_RB_2D_DST_INFO                 0x00002110
5068 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK          0x000000ff
5069 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT         0
5070 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5071 {
5072     return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
5073 }
5074 #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK         0x00000300
5075 #define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT            8
5076 static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
5077 {
5078     return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK;
5079 }
5080 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK            0x00000c00
5081 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT           10
5082 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5083 {
5084     return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
5085 }
5086 #define A5XX_RB_2D_DST_INFO_FLAGS               0x00001000
5087 #define A5XX_RB_2D_DST_INFO_SRGB                0x00002000
5088
5089 #define REG_A5XX_RB_2D_DST_LO                   0x00002111
5090
5091 #define REG_A5XX_RB_2D_DST_HI                   0x00002112
5092
5093 #define REG_A5XX_RB_2D_DST_SIZE                 0x00002113
5094 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK             0x0000ffff
5095 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT            0
5096 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
5097 {
5098     return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
5099 }
5100 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK           0xffff0000
5101 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT          16
5102 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
5103 {
5104     return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
5105 }
5106
5107 #define REG_A5XX_RB_2D_SRC_FLAGS_LO             0x00002140
5108
5109 #define REG_A5XX_RB_2D_SRC_FLAGS_HI             0x00002141
5110
5111 #define REG_A5XX_RB_2D_SRC_FLAGS_PITCH              0x00002142
5112 #define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK            0xffffffff
5113 #define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT           0
5114 static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
5115 {
5116     return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
5117 }
5118
5119 #define REG_A5XX_RB_2D_DST_FLAGS_LO             0x00002143
5120
5121 #define REG_A5XX_RB_2D_DST_FLAGS_HI             0x00002144
5122
5123 #define REG_A5XX_RB_2D_DST_FLAGS_PITCH              0x00002145
5124 #define A5XX_RB_2D_DST_FLAGS_PITCH__MASK            0xffffffff
5125 #define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT           0
5126 static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
5127 {
5128     return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
5129 }
5130
5131 #define REG_A5XX_GRAS_2D_BLIT_CNTL              0x00002180
5132
5133 #define REG_A5XX_GRAS_2D_SRC_INFO               0x00002181
5134 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK        0x000000ff
5135 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT       0
5136 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5137 {
5138     return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
5139 }
5140 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK           0x00000300
5141 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT          8
5142 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
5143 {
5144     return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK;
5145 }
5146 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK          0x00000c00
5147 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT         10
5148 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5149 {
5150     return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
5151 }
5152 #define A5XX_GRAS_2D_SRC_INFO_FLAGS             0x00001000
5153 #define A5XX_GRAS_2D_SRC_INFO_SRGB              0x00002000
5154
5155 #define REG_A5XX_GRAS_2D_DST_INFO               0x00002182
5156 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK        0x000000ff
5157 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT       0
5158 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5159 {
5160     return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
5161 }
5162 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK           0x00000300
5163 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT          8
5164 static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
5165 {
5166     return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK;
5167 }
5168 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK          0x00000c00
5169 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT         10
5170 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5171 {
5172     return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
5173 }
5174 #define A5XX_GRAS_2D_DST_INFO_FLAGS             0x00001000
5175 #define A5XX_GRAS_2D_DST_INFO_SRGB              0x00002000
5176
5177 #define REG_A5XX_UNKNOWN_2184                   0x00002184
5178
5179 #define REG_A5XX_TEX_SAMP_0                 0x00000000
5180 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR           0x00000001
5181 #define A5XX_TEX_SAMP_0_XY_MAG__MASK                0x00000006
5182 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT               1
5183 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
5184 {
5185     return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
5186 }
5187 #define A5XX_TEX_SAMP_0_XY_MIN__MASK                0x00000018
5188 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT               3
5189 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
5190 {
5191     return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
5192 }
5193 #define A5XX_TEX_SAMP_0_WRAP_S__MASK                0x000000e0
5194 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT               5
5195 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
5196 {
5197     return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
5198 }
5199 #define A5XX_TEX_SAMP_0_WRAP_T__MASK                0x00000700
5200 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT               8
5201 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
5202 {
5203     return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
5204 }
5205 #define A5XX_TEX_SAMP_0_WRAP_R__MASK                0x00003800
5206 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT               11
5207 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
5208 {
5209     return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
5210 }
5211 #define A5XX_TEX_SAMP_0_ANISO__MASK             0x0001c000
5212 #define A5XX_TEX_SAMP_0_ANISO__SHIFT                14
5213 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
5214 {
5215     return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
5216 }
5217 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK              0xfff80000
5218 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT             19
5219 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
5220 {
5221     return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
5222 }
5223
5224 #define REG_A5XX_TEX_SAMP_1                 0x00000001
5225 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK          0x0000000e
5226 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT         1
5227 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
5228 {
5229     return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
5230 }
5231 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF          0x00000010
5232 #define A5XX_TEX_SAMP_1_UNNORM_COORDS               0x00000020
5233 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR            0x00000040
5234 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK               0x000fff00
5235 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT              8
5236 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
5237 {
5238     return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
5239 }
5240 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK               0xfff00000
5241 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT              20
5242 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
5243 {
5244     return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
5245 }
5246
5247 #define REG_A5XX_TEX_SAMP_2                 0x00000002
5248 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK         0xffffff80
5249 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT            7
5250 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5251 {
5252     return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
5253 }
5254
5255 #define REG_A5XX_TEX_SAMP_3                 0x00000003
5256
5257 #define REG_A5XX_TEX_CONST_0                    0x00000000
5258 #define A5XX_TEX_CONST_0_TILE_MODE__MASK            0x00000003
5259 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT           0
5260 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
5261 {
5262     return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
5263 }
5264 #define A5XX_TEX_CONST_0_SRGB                   0x00000004
5265 #define A5XX_TEX_CONST_0_SWIZ_X__MASK               0x00000070
5266 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT              4
5267 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
5268 {
5269     return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
5270 }
5271 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK               0x00000380
5272 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT              7
5273 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
5274 {
5275     return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
5276 }
5277 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK               0x00001c00
5278 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT              10
5279 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
5280 {
5281     return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
5282 }
5283 #define A5XX_TEX_CONST_0_SWIZ_W__MASK               0x0000e000
5284 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT              13
5285 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
5286 {
5287     return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
5288 }
5289 #define A5XX_TEX_CONST_0_MIPLVLS__MASK              0x000f0000
5290 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT             16
5291 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5292 {
5293     return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
5294 }
5295 #define A5XX_TEX_CONST_0_SAMPLES__MASK              0x00300000
5296 #define A5XX_TEX_CONST_0_SAMPLES__SHIFT             20
5297 static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
5298 {
5299     return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK;
5300 }
5301 #define A5XX_TEX_CONST_0_FMT__MASK              0x3fc00000
5302 #define A5XX_TEX_CONST_0_FMT__SHIFT             22
5303 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
5304 {
5305     return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
5306 }
5307 #define A5XX_TEX_CONST_0_SWAP__MASK             0xc0000000
5308 #define A5XX_TEX_CONST_0_SWAP__SHIFT                30
5309 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
5310 {
5311     return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
5312 }
5313
5314 #define REG_A5XX_TEX_CONST_1                    0x00000001
5315 #define A5XX_TEX_CONST_1_WIDTH__MASK                0x00007fff
5316 #define A5XX_TEX_CONST_1_WIDTH__SHIFT               0
5317 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
5318 {
5319     return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
5320 }
5321 #define A5XX_TEX_CONST_1_HEIGHT__MASK               0x3fff8000
5322 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT              15
5323 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
5324 {
5325     return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
5326 }
5327
5328 #define REG_A5XX_TEX_CONST_2                    0x00000002
5329 #define A5XX_TEX_CONST_2_BUFFER                 0x00000010
5330 #define A5XX_TEX_CONST_2_PITCHALIGN__MASK           0x0000000f
5331 #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT          0
5332 static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
5333 {
5334     return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
5335 }
5336 #define A5XX_TEX_CONST_2_PITCH__MASK                0x1fffff80
5337 #define A5XX_TEX_CONST_2_PITCH__SHIFT               7
5338 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
5339 {
5340     return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
5341 }
5342 #define A5XX_TEX_CONST_2_TYPE__MASK             0xe0000000
5343 #define A5XX_TEX_CONST_2_TYPE__SHIFT                29
5344 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
5345 {
5346     return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
5347 }
5348
5349 #define REG_A5XX_TEX_CONST_3                    0x00000003
5350 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK          0x00003fff
5351 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT         0
5352 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5353 {
5354     return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5355 }
5356 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK          0x07800000
5357 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT         23
5358 static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
5359 {
5360     return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
5361 }
5362 #define A5XX_TEX_CONST_3_TILE_ALL               0x08000000
5363 #define A5XX_TEX_CONST_3_FLAG                   0x10000000
5364
5365 #define REG_A5XX_TEX_CONST_4                    0x00000004
5366 #define A5XX_TEX_CONST_4_BASE_LO__MASK              0xffffffe0
5367 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT             5
5368 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
5369 {
5370     return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
5371 }
5372
5373 #define REG_A5XX_TEX_CONST_5                    0x00000005
5374 #define A5XX_TEX_CONST_5_BASE_HI__MASK              0x0001ffff
5375 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT             0
5376 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
5377 {
5378     return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
5379 }
5380 #define A5XX_TEX_CONST_5_DEPTH__MASK                0x3ffe0000
5381 #define A5XX_TEX_CONST_5_DEPTH__SHIFT               17
5382 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
5383 {
5384     return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
5385 }
5386
5387 #define REG_A5XX_TEX_CONST_6                    0x00000006
5388
5389 #define REG_A5XX_TEX_CONST_7                    0x00000007
5390
5391 #define REG_A5XX_TEX_CONST_8                    0x00000008
5392
5393 #define REG_A5XX_TEX_CONST_9                    0x00000009
5394
5395 #define REG_A5XX_TEX_CONST_10                   0x0000000a
5396
5397 #define REG_A5XX_TEX_CONST_11                   0x0000000b
5398
5399 #define REG_A5XX_SSBO_0_0                   0x00000000
5400 #define A5XX_SSBO_0_0_BASE_LO__MASK             0xffffffe0
5401 #define A5XX_SSBO_0_0_BASE_LO__SHIFT                5
5402 static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
5403 {
5404     return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
5405 }
5406
5407 #define REG_A5XX_SSBO_0_1                   0x00000001
5408 #define A5XX_SSBO_0_1_PITCH__MASK               0x003fffff
5409 #define A5XX_SSBO_0_1_PITCH__SHIFT              0
5410 static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
5411 {
5412     return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK;
5413 }
5414
5415 #define REG_A5XX_SSBO_0_2                   0x00000002
5416 #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK             0x03fff000
5417 #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT            12
5418 static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
5419 {
5420     return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
5421 }
5422
5423 #define REG_A5XX_SSBO_0_3                   0x00000003
5424 #define A5XX_SSBO_0_3_CPP__MASK                 0x0000003f
5425 #define A5XX_SSBO_0_3_CPP__SHIFT                0
5426 static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
5427 {
5428     return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK;
5429 }
5430
5431 #define REG_A5XX_SSBO_1_0                   0x00000000
5432 #define A5XX_SSBO_1_0_FMT__MASK                 0x0000ff00
5433 #define A5XX_SSBO_1_0_FMT__SHIFT                8
5434 static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
5435 {
5436     return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK;
5437 }
5438 #define A5XX_SSBO_1_0_WIDTH__MASK               0xffff0000
5439 #define A5XX_SSBO_1_0_WIDTH__SHIFT              16
5440 static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
5441 {
5442     return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK;
5443 }
5444
5445 #define REG_A5XX_SSBO_1_1                   0x00000001
5446 #define A5XX_SSBO_1_1_HEIGHT__MASK              0x0000ffff
5447 #define A5XX_SSBO_1_1_HEIGHT__SHIFT             0
5448 static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
5449 {
5450     return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK;
5451 }
5452 #define A5XX_SSBO_1_1_DEPTH__MASK               0xffff0000
5453 #define A5XX_SSBO_1_1_DEPTH__SHIFT              16
5454 static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
5455 {
5456     return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK;
5457 }
5458
5459 #define REG_A5XX_SSBO_2_0                   0x00000000
5460 #define A5XX_SSBO_2_0_BASE_LO__MASK             0xffffffff
5461 #define A5XX_SSBO_2_0_BASE_LO__SHIFT                0
5462 static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
5463 {
5464     return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK;
5465 }
5466
5467 #define REG_A5XX_SSBO_2_1                   0x00000001
5468 #define A5XX_SSBO_2_1_BASE_HI__MASK             0xffffffff
5469 #define A5XX_SSBO_2_1_BASE_HI__SHIFT                0
5470 static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
5471 {
5472     return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
5473 }
5474
5475 #define REG_A5XX_UBO_0                      0x00000000
5476 #define A5XX_UBO_0_BASE_LO__MASK                0xffffffff
5477 #define A5XX_UBO_0_BASE_LO__SHIFT               0
5478 static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
5479 {
5480     return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
5481 }
5482
5483 #define REG_A5XX_UBO_1                      0x00000001
5484 #define A5XX_UBO_1_BASE_HI__MASK                0x0001ffff
5485 #define A5XX_UBO_1_BASE_HI__SHIFT               0
5486 static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
5487 {
5488     return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
5489 }
5490
5491
5492 #endif /* A5XX_XML */