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0001 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
0002  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
0003  *
0004  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
0005  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
0006  * All rights reserved.
0007  *
0008  * Permission is hereby granted, free of charge, to any person obtaining a
0009  * copy of this software and associated documentation files (the "Software"),
0010  * to deal in the Software without restriction, including without limitation
0011  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0012  * and/or sell copies of the Software, and to permit persons to whom the
0013  * Software is furnished to do so, subject to the following conditions:
0014  *
0015  * The above copyright notice and this permission notice (including the next
0016  * paragraph) shall be included in all copies or substantial portions of the
0017  * Software.
0018  *
0019  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0020  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0021  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0022  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0023  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0024  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0025  * OTHER DEALINGS IN THE SOFTWARE.
0026  *
0027  * Authors:
0028  *    Gareth Hughes <gareth@valinux.com>
0029  */
0030 
0031 #ifndef __MGA_DRV_H__
0032 #define __MGA_DRV_H__
0033 
0034 #include <linux/irqreturn.h>
0035 #include <linux/pci.h>
0036 #include <linux/slab.h>
0037 
0038 #include <drm/drm_device.h>
0039 #include <drm/drm_file.h>
0040 #include <drm/drm_ioctl.h>
0041 #include <drm/drm_legacy.h>
0042 #include <drm/drm_print.h>
0043 #include <drm/drm_sarea.h>
0044 #include <drm/drm_vblank.h>
0045 #include <drm/mga_drm.h>
0046 
0047 /* General customization:
0048  */
0049 
0050 #define DRIVER_AUTHOR       "Gareth Hughes, VA Linux Systems Inc."
0051 
0052 #define DRIVER_NAME     "mga"
0053 #define DRIVER_DESC     "Matrox G200/G400"
0054 #define DRIVER_DATE     "20051102"
0055 
0056 #define DRIVER_MAJOR        3
0057 #define DRIVER_MINOR        2
0058 #define DRIVER_PATCHLEVEL   1
0059 
0060 typedef struct drm_mga_primary_buffer {
0061     u8 *start;
0062     u8 *end;
0063     int size;
0064 
0065     u32 tail;
0066     int space;
0067     volatile long wrapped;
0068 
0069     volatile u32 *status;
0070 
0071     u32 last_flush;
0072     u32 last_wrap;
0073 
0074     u32 high_mark;
0075 } drm_mga_primary_buffer_t;
0076 
0077 typedef struct drm_mga_freelist {
0078     struct drm_mga_freelist *next;
0079     struct drm_mga_freelist *prev;
0080     drm_mga_age_t age;
0081     struct drm_buf *buf;
0082 } drm_mga_freelist_t;
0083 
0084 typedef struct {
0085     drm_mga_freelist_t *list_entry;
0086     int discard;
0087     int dispatched;
0088 } drm_mga_buf_priv_t;
0089 
0090 typedef struct drm_mga_private {
0091     drm_mga_primary_buffer_t prim;
0092     drm_mga_sarea_t *sarea_priv;
0093 
0094     drm_mga_freelist_t *head;
0095     drm_mga_freelist_t *tail;
0096 
0097     unsigned int warp_pipe;
0098     unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
0099 
0100     int chipset;
0101     int usec_timeout;
0102 
0103     /**
0104      * If set, the new DMA initialization sequence was used.  This is
0105      * primarilly used to select how the driver should uninitialized its
0106      * internal DMA structures.
0107      */
0108     int used_new_dma_init;
0109 
0110     /**
0111      * If AGP memory is used for DMA buffers, this will be the value
0112      * \c MGA_PAGPXFER.  Otherwise, it will be zero (for a PCI transfer).
0113      */
0114     u32 dma_access;
0115 
0116     /**
0117      * If AGP memory is used for DMA buffers, this will be the value
0118      * \c MGA_WAGP_ENABLE.  Otherwise, it will be zero (for a PCI
0119      * transfer).
0120      */
0121     u32 wagp_enable;
0122 
0123     /**
0124      * \name MMIO region parameters.
0125      *
0126      * \sa drm_mga_private_t::mmio
0127      */
0128     /*@{ */
0129     resource_size_t mmio_base;     /**< Bus address of base of MMIO. */
0130     resource_size_t mmio_size;     /**< Size of the MMIO region. */
0131     /*@} */
0132 
0133     u32 clear_cmd;
0134     u32 maccess;
0135 
0136     atomic_t vbl_received;          /**< Number of vblanks received. */
0137     wait_queue_head_t fence_queue;
0138     atomic_t last_fence_retired;
0139     u32 next_fence_to_post;
0140 
0141     unsigned int fb_cpp;
0142     unsigned int front_offset;
0143     unsigned int front_pitch;
0144     unsigned int back_offset;
0145     unsigned int back_pitch;
0146 
0147     unsigned int depth_cpp;
0148     unsigned int depth_offset;
0149     unsigned int depth_pitch;
0150 
0151     unsigned int texture_offset;
0152     unsigned int texture_size;
0153 
0154     drm_local_map_t *sarea;
0155     drm_local_map_t *mmio;
0156     drm_local_map_t *status;
0157     drm_local_map_t *warp;
0158     drm_local_map_t *primary;
0159     drm_local_map_t *agp_textures;
0160 
0161     unsigned long agp_handle;
0162     unsigned int agp_size;
0163 } drm_mga_private_t;
0164 
0165 extern const struct drm_ioctl_desc mga_ioctls[];
0166 extern int mga_max_ioctl;
0167 
0168                 /* mga_dma.c */
0169 extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
0170                  struct drm_file *file_priv);
0171 extern int mga_dma_init(struct drm_device *dev, void *data,
0172             struct drm_file *file_priv);
0173 extern int mga_getparam(struct drm_device *dev, void *data,
0174             struct drm_file *file_priv);
0175 extern int mga_dma_flush(struct drm_device *dev, void *data,
0176              struct drm_file *file_priv);
0177 extern int mga_dma_reset(struct drm_device *dev, void *data,
0178              struct drm_file *file_priv);
0179 extern int mga_dma_buffers(struct drm_device *dev, void *data,
0180                struct drm_file *file_priv);
0181 extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
0182 extern void mga_driver_unload(struct drm_device *dev);
0183 extern void mga_driver_lastclose(struct drm_device *dev);
0184 extern int mga_driver_dma_quiescent(struct drm_device *dev);
0185 
0186 extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
0187 
0188 extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
0189 extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
0190 extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
0191 
0192 extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
0193 
0194                 /* mga_warp.c */
0195 extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
0196 extern int mga_warp_init(drm_mga_private_t *dev_priv);
0197 
0198                 /* mga_irq.c */
0199 extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe);
0200 extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe);
0201 extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
0202 extern void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
0203 extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
0204 extern irqreturn_t mga_driver_irq_handler(int irq, void *arg);
0205 extern void mga_driver_irq_preinstall(struct drm_device *dev);
0206 extern int mga_driver_irq_postinstall(struct drm_device *dev);
0207 extern void mga_driver_irq_uninstall(struct drm_device *dev);
0208 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
0209                  unsigned long arg);
0210 
0211 #define mga_flush_write_combine()   wmb()
0212 
0213 #define MGA_READ8(reg) \
0214     readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
0215 #define MGA_READ(reg) \
0216     readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
0217 #define MGA_WRITE8(reg, val) \
0218     writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
0219 #define MGA_WRITE(reg, val) \
0220     writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
0221 
0222 #define DWGREG0     0x1c00
0223 #define DWGREG0_END 0x1dff
0224 #define DWGREG1     0x2c00
0225 #define DWGREG1_END 0x2dff
0226 
0227 #define ISREG0(r)   (r >= DWGREG0 && r <= DWGREG0_END)
0228 #define DMAREG0(r)  (u8)((r - DWGREG0) >> 2)
0229 #define DMAREG1(r)  (u8)(((r - DWGREG1) >> 2) | 0x80)
0230 #define DMAREG(r)   (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
0231 
0232 /* ================================================================
0233  * Helper macross...
0234  */
0235 
0236 #define MGA_EMIT_STATE(dev_priv, dirty)                 \
0237 do {                                    \
0238     if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) {              \
0239         if (dev_priv->chipset >= MGA_CARD_TYPE_G400)        \
0240             mga_g400_emit_state(dev_priv);          \
0241         else                            \
0242             mga_g200_emit_state(dev_priv);          \
0243     }                               \
0244 } while (0)
0245 
0246 #define WRAP_TEST_WITH_RETURN(dev_priv)                 \
0247 do {                                    \
0248     if (test_bit(0, &dev_priv->prim.wrapped)) {         \
0249         if (mga_is_idle(dev_priv)) {                \
0250             mga_do_dma_wrap_end(dev_priv);          \
0251         } else if (dev_priv->prim.space <           \
0252                dev_priv->prim.high_mark) {          \
0253             if (MGA_DMA_DEBUG)              \
0254                 DRM_INFO("wrap...\n");          \
0255             return -EBUSY;                  \
0256         }                           \
0257     }                               \
0258 } while (0)
0259 
0260 #define WRAP_WAIT_WITH_RETURN(dev_priv)                 \
0261 do {                                    \
0262     if (test_bit(0, &dev_priv->prim.wrapped)) {         \
0263         if (mga_do_wait_for_idle(dev_priv) < 0) {       \
0264             if (MGA_DMA_DEBUG)              \
0265                 DRM_INFO("wrap...\n");          \
0266             return -EBUSY;                  \
0267         }                           \
0268         mga_do_dma_wrap_end(dev_priv);              \
0269     }                               \
0270 } while (0)
0271 
0272 /* ================================================================
0273  * Primary DMA command stream
0274  */
0275 
0276 #define MGA_VERBOSE 0
0277 
0278 #define DMA_LOCALS  unsigned int write; volatile u8 *prim;
0279 
0280 #define DMA_BLOCK_SIZE  (5 * sizeof(u32))
0281 
0282 #define BEGIN_DMA(n)                            \
0283 do {                                    \
0284     if (MGA_VERBOSE) {                      \
0285         DRM_INFO("BEGIN_DMA(%d)\n", (n));           \
0286         DRM_INFO("   space=0x%x req=0x%zx\n",           \
0287              dev_priv->prim.space, (n) * DMA_BLOCK_SIZE);   \
0288     }                               \
0289     prim = dev_priv->prim.start;                    \
0290     write = dev_priv->prim.tail;                    \
0291 } while (0)
0292 
0293 #define BEGIN_DMA_WRAP()                        \
0294 do {                                    \
0295     if (MGA_VERBOSE) {                      \
0296         DRM_INFO("BEGIN_DMA()\n");              \
0297         DRM_INFO("   space=0x%x\n", dev_priv->prim.space);  \
0298     }                               \
0299     prim = dev_priv->prim.start;                    \
0300     write = dev_priv->prim.tail;                    \
0301 } while (0)
0302 
0303 #define ADVANCE_DMA()                           \
0304 do {                                    \
0305     dev_priv->prim.tail = write;                    \
0306     if (MGA_VERBOSE)                        \
0307         DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n",     \
0308              write, dev_priv->prim.space);          \
0309 } while (0)
0310 
0311 #define FLUSH_DMA()                         \
0312 do {                                    \
0313     if (0) {                            \
0314         DRM_INFO("\n");                     \
0315         DRM_INFO("   tail=0x%06x head=0x%06lx\n",       \
0316              dev_priv->prim.tail,               \
0317              (unsigned long)(MGA_READ(MGA_PRIMADDRESS) -    \
0318                      dev_priv->primary->offset));   \
0319     }                               \
0320     if (!test_bit(0, &dev_priv->prim.wrapped)) {            \
0321         if (dev_priv->prim.space < dev_priv->prim.high_mark)    \
0322             mga_do_dma_wrap_start(dev_priv);        \
0323         else                            \
0324             mga_do_dma_flush(dev_priv);         \
0325     }                               \
0326 } while (0)
0327 
0328 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
0329  */
0330 #define DMA_WRITE(offset, val)                      \
0331 do {                                    \
0332     if (MGA_VERBOSE)                        \
0333         DRM_INFO("   DMA_WRITE( 0x%08x ) at 0x%04zx\n",     \
0334              (u32)(val), write + (offset) * sizeof(u32));   \
0335     *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
0336 } while (0)
0337 
0338 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3)   \
0339 do {                                    \
0340     DMA_WRITE(0, ((DMAREG(reg0) << 0) |             \
0341               (DMAREG(reg1) << 8) |             \
0342               (DMAREG(reg2) << 16) |                \
0343               (DMAREG(reg3) << 24)));               \
0344     DMA_WRITE(1, val0);                     \
0345     DMA_WRITE(2, val1);                     \
0346     DMA_WRITE(3, val2);                     \
0347     DMA_WRITE(4, val3);                     \
0348     write += DMA_BLOCK_SIZE;                    \
0349 } while (0)
0350 
0351 /* Buffer aging via primary DMA stream head pointer.
0352  */
0353 
0354 #define SET_AGE(age, h, w)                      \
0355 do {                                    \
0356     (age)->head = h;                        \
0357     (age)->wrap = w;                        \
0358 } while (0)
0359 
0360 #define TEST_AGE(age, h, w)     ((age)->wrap < w ||     \
0361                      ((age)->wrap == w &&       \
0362                       (age)->head < h))
0363 
0364 #define AGE_BUFFER(buf_priv)                        \
0365 do {                                    \
0366     drm_mga_freelist_t *entry = (buf_priv)->list_entry;     \
0367     if ((buf_priv)->dispatched) {                   \
0368         entry->age.head = (dev_priv->prim.tail +        \
0369                    dev_priv->primary->offset);      \
0370         entry->age.wrap = dev_priv->sarea_priv->last_wrap;  \
0371     } else {                            \
0372         entry->age.head = 0;                    \
0373         entry->age.wrap = 0;                    \
0374     }                               \
0375 } while (0)
0376 
0377 #define MGA_ENGINE_IDLE_MASK        (MGA_SOFTRAPEN |        \
0378                      MGA_DWGENGSTS |        \
0379                      MGA_ENDPRDMASTS)
0380 #define MGA_DMA_IDLE_MASK       (MGA_SOFTRAPEN |        \
0381                      MGA_ENDPRDMASTS)
0382 
0383 #define MGA_DMA_DEBUG           0
0384 
0385 /* A reduced set of the mga registers.
0386  */
0387 #define MGA_CRTC_INDEX          0x1fd4
0388 #define MGA_CRTC_DATA           0x1fd5
0389 
0390 /* CRTC11 */
0391 #define MGA_VINTCLR         (1 << 4)
0392 #define MGA_VINTEN          (1 << 5)
0393 
0394 #define MGA_ALPHACTRL           0x2c7c
0395 #define MGA_AR0             0x1c60
0396 #define MGA_AR1             0x1c64
0397 #define MGA_AR2             0x1c68
0398 #define MGA_AR3             0x1c6c
0399 #define MGA_AR4             0x1c70
0400 #define MGA_AR5             0x1c74
0401 #define MGA_AR6             0x1c78
0402 
0403 #define MGA_CXBNDRY         0x1c80
0404 #define MGA_CXLEFT          0x1ca0
0405 #define MGA_CXRIGHT         0x1ca4
0406 
0407 #define MGA_DMAPAD          0x1c54
0408 #define MGA_DSTORG          0x2cb8
0409 #define MGA_DWGCTL          0x1c00
0410 #   define MGA_OPCOD_MASK           (15 << 0)
0411 #   define MGA_OPCOD_TRAP           (4 << 0)
0412 #   define MGA_OPCOD_TEXTURE_TRAP       (6 << 0)
0413 #   define MGA_OPCOD_BITBLT         (8 << 0)
0414 #   define MGA_OPCOD_ILOAD          (9 << 0)
0415 #   define MGA_ATYPE_MASK           (7 << 4)
0416 #   define MGA_ATYPE_RPL            (0 << 4)
0417 #   define MGA_ATYPE_RSTR           (1 << 4)
0418 #   define MGA_ATYPE_ZI         (3 << 4)
0419 #   define MGA_ATYPE_BLK            (4 << 4)
0420 #   define MGA_ATYPE_I          (7 << 4)
0421 #   define MGA_LINEAR           (1 << 7)
0422 #   define MGA_ZMODE_MASK           (7 << 8)
0423 #   define MGA_ZMODE_NOZCMP         (0 << 8)
0424 #   define MGA_ZMODE_ZE         (2 << 8)
0425 #   define MGA_ZMODE_ZNE            (3 << 8)
0426 #   define MGA_ZMODE_ZLT            (4 << 8)
0427 #   define MGA_ZMODE_ZLTE           (5 << 8)
0428 #   define MGA_ZMODE_ZGT            (6 << 8)
0429 #   define MGA_ZMODE_ZGTE           (7 << 8)
0430 #   define MGA_SOLID            (1 << 11)
0431 #   define MGA_ARZERO           (1 << 12)
0432 #   define MGA_SGNZERO          (1 << 13)
0433 #   define MGA_SHIFTZERO            (1 << 14)
0434 #   define MGA_BOP_MASK         (15 << 16)
0435 #   define MGA_BOP_ZERO         (0 << 16)
0436 #   define MGA_BOP_DST          (10 << 16)
0437 #   define MGA_BOP_SRC          (12 << 16)
0438 #   define MGA_BOP_ONE          (15 << 16)
0439 #   define MGA_TRANS_SHIFT          20
0440 #   define MGA_TRANS_MASK           (15 << 20)
0441 #   define MGA_BLTMOD_MASK          (15 << 25)
0442 #   define MGA_BLTMOD_BMONOLEF      (0 << 25)
0443 #   define MGA_BLTMOD_BMONOWF       (4 << 25)
0444 #   define MGA_BLTMOD_PLAN          (1 << 25)
0445 #   define MGA_BLTMOD_BFCOL         (2 << 25)
0446 #   define MGA_BLTMOD_BU32BGR       (3 << 25)
0447 #   define MGA_BLTMOD_BU32RGB       (7 << 25)
0448 #   define MGA_BLTMOD_BU24BGR       (11 << 25)
0449 #   define MGA_BLTMOD_BU24RGB       (15 << 25)
0450 #   define MGA_PATTERN          (1 << 29)
0451 #   define MGA_TRANSC           (1 << 30)
0452 #   define MGA_CLIPDIS          (1 << 31)
0453 #define MGA_DWGSYNC         0x2c4c
0454 
0455 #define MGA_FCOL            0x1c24
0456 #define MGA_FIFOSTATUS          0x1e10
0457 #define MGA_FOGCOL          0x1cf4
0458 #define MGA_FXBNDRY         0x1c84
0459 #define MGA_FXLEFT          0x1ca8
0460 #define MGA_FXRIGHT         0x1cac
0461 
0462 #define MGA_ICLEAR          0x1e18
0463 #   define MGA_SOFTRAPICLR          (1 << 0)
0464 #   define MGA_VLINEICLR            (1 << 5)
0465 #define MGA_IEN             0x1e1c
0466 #   define MGA_SOFTRAPIEN           (1 << 0)
0467 #   define MGA_VLINEIEN         (1 << 5)
0468 
0469 #define MGA_LEN             0x1c5c
0470 
0471 #define MGA_MACCESS         0x1c04
0472 
0473 #define MGA_PITCH           0x1c8c
0474 #define MGA_PLNWT           0x1c1c
0475 #define MGA_PRIMADDRESS         0x1e58
0476 #   define MGA_DMA_GENERAL          (0 << 0)
0477 #   define MGA_DMA_BLIT         (1 << 0)
0478 #   define MGA_DMA_VECTOR           (2 << 0)
0479 #   define MGA_DMA_VERTEX           (3 << 0)
0480 #define MGA_PRIMEND         0x1e5c
0481 #   define MGA_PRIMNOSTART          (1 << 0)
0482 #   define MGA_PAGPXFER         (1 << 1)
0483 #define MGA_PRIMPTR         0x1e50
0484 #   define MGA_PRIMPTREN0           (1 << 0)
0485 #   define MGA_PRIMPTREN1           (1 << 1)
0486 
0487 #define MGA_RST             0x1e40
0488 #   define MGA_SOFTRESET            (1 << 0)
0489 #   define MGA_SOFTEXTRST           (1 << 1)
0490 
0491 #define MGA_SECADDRESS          0x2c40
0492 #define MGA_SECEND          0x2c44
0493 #define MGA_SETUPADDRESS        0x2cd0
0494 #define MGA_SETUPEND            0x2cd4
0495 #define MGA_SGN             0x1c58
0496 #define MGA_SOFTRAP         0x2c48
0497 #define MGA_SRCORG          0x2cb4
0498 #   define MGA_SRMMAP_MASK          (1 << 0)
0499 #   define MGA_SRCMAP_FB            (0 << 0)
0500 #   define MGA_SRCMAP_SYSMEM        (1 << 0)
0501 #   define MGA_SRCACC_MASK          (1 << 1)
0502 #   define MGA_SRCACC_PCI           (0 << 1)
0503 #   define MGA_SRCACC_AGP           (1 << 1)
0504 #define MGA_STATUS          0x1e14
0505 #   define MGA_SOFTRAPEN            (1 << 0)
0506 #   define MGA_VSYNCPEN         (1 << 4)
0507 #   define MGA_VLINEPEN         (1 << 5)
0508 #   define MGA_DWGENGSTS            (1 << 16)
0509 #   define MGA_ENDPRDMASTS          (1 << 17)
0510 #define MGA_STENCIL         0x2cc8
0511 #define MGA_STENCILCTL          0x2ccc
0512 
0513 #define MGA_TDUALSTAGE0         0x2cf8
0514 #define MGA_TDUALSTAGE1         0x2cfc
0515 #define MGA_TEXBORDERCOL        0x2c5c
0516 #define MGA_TEXCTL          0x2c30
0517 #define MGA_TEXCTL2         0x2c3c
0518 #   define MGA_DUALTEX          (1 << 7)
0519 #   define MGA_G400_TC2_MAGIC       (1 << 15)
0520 #   define MGA_MAP1_ENABLE          (1 << 31)
0521 #define MGA_TEXFILTER           0x2c58
0522 #define MGA_TEXHEIGHT           0x2c2c
0523 #define MGA_TEXORG          0x2c24
0524 #   define MGA_TEXORGMAP_MASK       (1 << 0)
0525 #   define MGA_TEXORGMAP_FB         (0 << 0)
0526 #   define MGA_TEXORGMAP_SYSMEM     (1 << 0)
0527 #   define MGA_TEXORGACC_MASK       (1 << 1)
0528 #   define MGA_TEXORGACC_PCI        (0 << 1)
0529 #   define MGA_TEXORGACC_AGP        (1 << 1)
0530 #define MGA_TEXORG1         0x2ca4
0531 #define MGA_TEXORG2         0x2ca8
0532 #define MGA_TEXORG3         0x2cac
0533 #define MGA_TEXORG4         0x2cb0
0534 #define MGA_TEXTRANS            0x2c34
0535 #define MGA_TEXTRANSHIGH        0x2c38
0536 #define MGA_TEXWIDTH            0x2c28
0537 
0538 #define MGA_WACCEPTSEQ          0x1dd4
0539 #define MGA_WCODEADDR           0x1e6c
0540 #define MGA_WFLAG           0x1dc4
0541 #define MGA_WFLAG1          0x1de0
0542 #define MGA_WFLAGNB         0x1e64
0543 #define MGA_WFLAGNB1            0x1e08
0544 #define MGA_WGETMSB         0x1dc8
0545 #define MGA_WIADDR          0x1dc0
0546 #define MGA_WIADDR2         0x1dd8
0547 #   define MGA_WMODE_SUSPEND        (0 << 0)
0548 #   define MGA_WMODE_RESUME         (1 << 0)
0549 #   define MGA_WMODE_JUMP           (2 << 0)
0550 #   define MGA_WMODE_START          (3 << 0)
0551 #   define MGA_WAGP_ENABLE          (1 << 2)
0552 #define MGA_WMISC           0x1e70
0553 #   define MGA_WUCODECACHE_ENABLE       (1 << 0)
0554 #   define MGA_WMASTER_ENABLE       (1 << 1)
0555 #   define MGA_WCACHEFLUSH_ENABLE       (1 << 3)
0556 #define MGA_WVRTXSZ         0x1dcc
0557 
0558 #define MGA_YBOT            0x1c9c
0559 #define MGA_YDST            0x1c90
0560 #define MGA_YDSTLEN         0x1c88
0561 #define MGA_YDSTORG         0x1c94
0562 #define MGA_YTOP            0x1c98
0563 
0564 #define MGA_ZORG            0x1c0c
0565 
0566 /* This finishes the current batch of commands
0567  */
0568 #define MGA_EXEC            0x0100
0569 
0570 /* AGP PLL encoding (for G200 only).
0571  */
0572 #define MGA_AGP_PLL         0x1e4c
0573 #   define MGA_AGP2XPLL_DISABLE     (0 << 0)
0574 #   define MGA_AGP2XPLL_ENABLE      (1 << 0)
0575 
0576 /* Warp registers
0577  */
0578 #define MGA_WR0             0x2d00
0579 #define MGA_WR1             0x2d04
0580 #define MGA_WR2             0x2d08
0581 #define MGA_WR3             0x2d0c
0582 #define MGA_WR4             0x2d10
0583 #define MGA_WR5             0x2d14
0584 #define MGA_WR6             0x2d18
0585 #define MGA_WR7             0x2d1c
0586 #define MGA_WR8             0x2d20
0587 #define MGA_WR9             0x2d24
0588 #define MGA_WR10            0x2d28
0589 #define MGA_WR11            0x2d2c
0590 #define MGA_WR12            0x2d30
0591 #define MGA_WR13            0x2d34
0592 #define MGA_WR14            0x2d38
0593 #define MGA_WR15            0x2d3c
0594 #define MGA_WR16            0x2d40
0595 #define MGA_WR17            0x2d44
0596 #define MGA_WR18            0x2d48
0597 #define MGA_WR19            0x2d4c
0598 #define MGA_WR20            0x2d50
0599 #define MGA_WR21            0x2d54
0600 #define MGA_WR22            0x2d58
0601 #define MGA_WR23            0x2d5c
0602 #define MGA_WR24            0x2d60
0603 #define MGA_WR25            0x2d64
0604 #define MGA_WR26            0x2d68
0605 #define MGA_WR27            0x2d6c
0606 #define MGA_WR28            0x2d70
0607 #define MGA_WR29            0x2d74
0608 #define MGA_WR30            0x2d78
0609 #define MGA_WR31            0x2d7c
0610 #define MGA_WR32            0x2d80
0611 #define MGA_WR33            0x2d84
0612 #define MGA_WR34            0x2d88
0613 #define MGA_WR35            0x2d8c
0614 #define MGA_WR36            0x2d90
0615 #define MGA_WR37            0x2d94
0616 #define MGA_WR38            0x2d98
0617 #define MGA_WR39            0x2d9c
0618 #define MGA_WR40            0x2da0
0619 #define MGA_WR41            0x2da4
0620 #define MGA_WR42            0x2da8
0621 #define MGA_WR43            0x2dac
0622 #define MGA_WR44            0x2db0
0623 #define MGA_WR45            0x2db4
0624 #define MGA_WR46            0x2db8
0625 #define MGA_WR47            0x2dbc
0626 #define MGA_WR48            0x2dc0
0627 #define MGA_WR49            0x2dc4
0628 #define MGA_WR50            0x2dc8
0629 #define MGA_WR51            0x2dcc
0630 #define MGA_WR52            0x2dd0
0631 #define MGA_WR53            0x2dd4
0632 #define MGA_WR54            0x2dd8
0633 #define MGA_WR55            0x2ddc
0634 #define MGA_WR56            0x2de0
0635 #define MGA_WR57            0x2de4
0636 #define MGA_WR58            0x2de8
0637 #define MGA_WR59            0x2dec
0638 #define MGA_WR60            0x2df0
0639 #define MGA_WR61            0x2df4
0640 #define MGA_WR62            0x2df8
0641 #define MGA_WR63            0x2dfc
0642 #   define MGA_G400_WR_MAGIC        (1 << 6)
0643 #   define MGA_G400_WR56_MAGIC      0x46480000  /* 12800.0f */
0644 
0645 #define MGA_ILOAD_ALIGN     64
0646 #define MGA_ILOAD_MASK      (MGA_ILOAD_ALIGN - 1)
0647 
0648 #define MGA_DWGCTL_FLUSH    (MGA_OPCOD_TEXTURE_TRAP |       \
0649                  MGA_ATYPE_I |              \
0650                  MGA_ZMODE_NOZCMP |         \
0651                  MGA_ARZERO |               \
0652                  MGA_SGNZERO |              \
0653                  MGA_BOP_SRC |              \
0654                  (15 << MGA_TRANS_SHIFT))
0655 
0656 #define MGA_DWGCTL_CLEAR    (MGA_OPCOD_TRAP |           \
0657                  MGA_ZMODE_NOZCMP |         \
0658                  MGA_SOLID |                \
0659                  MGA_ARZERO |               \
0660                  MGA_SGNZERO |              \
0661                  MGA_SHIFTZERO |            \
0662                  MGA_BOP_SRC |              \
0663                  (0 << MGA_TRANS_SHIFT) |       \
0664                  MGA_BLTMOD_BMONOLEF |          \
0665                  MGA_TRANSC |               \
0666                  MGA_CLIPDIS)
0667 
0668 #define MGA_DWGCTL_COPY     (MGA_OPCOD_BITBLT |         \
0669                  MGA_ATYPE_RPL |            \
0670                  MGA_SGNZERO |              \
0671                  MGA_SHIFTZERO |            \
0672                  MGA_BOP_SRC |              \
0673                  (0 << MGA_TRANS_SHIFT) |       \
0674                  MGA_BLTMOD_BFCOL |         \
0675                  MGA_CLIPDIS)
0676 
0677 /* Simple idle test.
0678  */
0679 static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
0680 {
0681     u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
0682     return (status == MGA_ENDPRDMASTS);
0683 }
0684 
0685 #endif
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