drm/meson/meson_viu.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2016 BayLibre, SAS
0004  * Author: Neil Armstrong <narmstrong@baylibre.com>
0005  */
0006
0007 /* Video Input Unit */
0008
0009 #ifndef __MESON_VIU_H
0010 #define __MESON_VIU_H
0011
0012 /* OSDx_BLKx_CFG */
0013 #define OSD_MALI_SRC_EN     BIT(30)
0014
0015 #define OSD_CANVAS_SEL      16
0016
0017 #define OSD_ENDIANNESS_LE   BIT(15)
0018 #define OSD_ENDIANNESS_BE   (0)
0019
0020 #define OSD_BLK_MODE_422    (0x03 << 8)
0021 #define OSD_BLK_MODE_16     (0x04 << 8)
0022 #define OSD_BLK_MODE_32     (0x05 << 8)
0023 #define OSD_BLK_MODE_24     (0x07 << 8)
0024
0025 #define OSD_OUTPUT_COLOR_RGB    BIT(7)
0026 #define OSD_OUTPUT_COLOR_YUV    (0)
0027
0028 #define OSD_COLOR_MATRIX_32_RGBA    (0x00 << 2)
0029 #define OSD_COLOR_MATRIX_32_ARGB    (0x01 << 2)
0030 #define OSD_COLOR_MATRIX_32_ABGR    (0x02 << 2)
0031 #define OSD_COLOR_MATRIX_32_BGRA    (0x03 << 2)
0032
0033 #define OSD_COLOR_MATRIX_24_RGB     (0x00 << 2)
0034
0035 #define OSD_COLOR_MATRIX_16_RGB655  (0x00 << 2)
0036 #define OSD_COLOR_MATRIX_16_RGB565  (0x04 << 2)
0037
0038 #define OSD_MALI_COLOR_MODE_R8      (0 << 8)
0039 #define OSD_MALI_COLOR_MODE_YUV422  (1 << 8)
0040 #define OSD_MALI_COLOR_MODE_RGB565  (2 << 8)
0041 #define OSD_MALI_COLOR_MODE_RGBA5551    (3 << 8)
0042 #define OSD_MALI_COLOR_MODE_RGBA4444    (4 << 8)
0043 #define OSD_MALI_COLOR_MODE_RGBA8888    (5 << 8)
0044 #define OSD_MALI_COLOR_MODE_RGB888  (7 << 8)
0045 #define OSD_MALI_COLOR_MODE_YUV422_10B  (8 << 8)
0046 #define OSD_MALI_COLOR_MODE_RGBA1010102 (9 << 8)
0047
0048 #define OSD_INTERLACE_ENABLED   BIT(1)
0049 #define OSD_INTERLACE_ODD   BIT(0)
0050 #define OSD_INTERLACE_EVEN  (0)
0051
0052 /* OSDx_CTRL_STAT */
0053 #define OSD_ENABLE      BIT(21)
0054 #define OSD_MEM_LINEAR_ADDR BIT(2)
0055 #define OSD_BLK0_ENABLE     BIT(0)
0056
0057 #define OSD_GLOBAL_ALPHA_SHIFT  12
0058
0059 /* OSDx_CTRL_STAT2 */
0060 #define OSD_DPATH_MALI_AFBCD    BIT(15)
0061 #define OSD_REPLACE_EN      BIT(14)
0062 #define OSD_REPLACE_SHIFT   6
0063 #define OSD_PENDING_STAT_CLEAN  BIT(1)
0064
0065 void meson_viu_osd1_reset(struct meson_drm *priv);
0066 void meson_viu_g12a_enable_osd1_afbc(struct meson_drm *priv);
0067 void meson_viu_g12a_disable_osd1_afbc(struct meson_drm *priv);
0068 void meson_viu_gxm_enable_osd1_afbc(struct meson_drm *priv);
0069 void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv);
0070 void meson_viu_init(struct meson_drm *priv);
0071
0072 #endif /* __MESON_VIU_H */