drm/meson/meson_venc.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2016 BayLibre, SAS
0004  * Author: Neil Armstrong <narmstrong@baylibre.com>
0005  */
0006
0007 /*
0008  * Video Encoders
0009  * - ENCI : Interlace Video Encoder
0010  * - ENCI_DVI : Interlace Video Encoder for DVI/HDMI
0011  * - ENCP : Progressive Video Encoder
0012  */
0013
0014 #ifndef __MESON_VENC_H
0015 #define __MESON_VENC_H
0016
0017 struct drm_display_mode;
0018
0019 enum {
0020     MESON_VENC_MODE_NONE = 0,
0021     MESON_VENC_MODE_CVBS_PAL,
0022     MESON_VENC_MODE_CVBS_NTSC,
0023     MESON_VENC_MODE_HDMI,
0024 };
0025
0026 struct meson_cvbs_enci_mode {
0027     unsigned int mode_tag;
0028     unsigned int hso_begin; /* HSO begin position */
0029     unsigned int hso_end; /* HSO end position */
0030     unsigned int vso_even; /* VSO even line */
0031     unsigned int vso_odd; /* VSO odd line */
0032     unsigned int macv_max_amp; /* Macrovision max amplitude */
0033     unsigned int video_prog_mode;
0034     unsigned int video_mode;
0035     unsigned int sch_adjust;
0036     unsigned int yc_delay;
0037     unsigned int pixel_start;
0038     unsigned int pixel_end;
0039     unsigned int top_field_line_start;
0040     unsigned int top_field_line_end;
0041     unsigned int bottom_field_line_start;
0042     unsigned int bottom_field_line_end;
0043     unsigned int video_saturation;
0044     unsigned int video_contrast;
0045     unsigned int video_brightness;
0046     unsigned int video_hue;
0047     unsigned int analog_sync_adj;
0048 };
0049
0050 /* HDMI Clock parameters */
0051 enum drm_mode_status
0052 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode);
0053 bool meson_venc_hdmi_supported_vic(int vic);
0054 bool meson_venc_hdmi_venc_repeat(int vic);
0055
0056 /* CVBS Timings and Parameters */
0057 extern struct meson_cvbs_enci_mode meson_cvbs_enci_pal;
0058 extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc;
0059
0060 void meson_venci_cvbs_mode_set(struct meson_drm *priv,
0061                    struct meson_cvbs_enci_mode *mode);
0062 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
0063                   unsigned int ycrcb_map,
0064                   bool yuv420_mode,
0065                   const struct drm_display_mode *mode);
0066 unsigned int meson_venci_get_field(struct meson_drm *priv);
0067
0068 void meson_venc_enable_vsync(struct meson_drm *priv);
0069 void meson_venc_disable_vsync(struct meson_drm *priv);
0070
0071 void meson_venc_init(struct meson_drm *priv);
0072
0073 #endif /* __MESON_VENC_H */