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0009 #ifndef __MESON_VCLK_H
0010 #define __MESON_VCLK_H
0011
0012 #include <drm/drm_modes.h>
0013
0014 struct meson_drm;
0015
0016 enum {
0017 MESON_VCLK_TARGET_CVBS = 0,
0018 MESON_VCLK_TARGET_HDMI = 1,
0019 MESON_VCLK_TARGET_DMT = 2,
0020 };
0021
0022
0023 #define MESON_VCLK_CVBS 27000
0024
0025 enum drm_mode_status
0026 meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
0027 enum drm_mode_status
0028 meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq,
0029 unsigned int vclk_freq);
0030
0031 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
0032 unsigned int phy_freq, unsigned int vclk_freq,
0033 unsigned int venc_freq, unsigned int dac_freq,
0034 bool hdmi_use_enci);
0035
0036 #endif