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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2018 BayLibre, SAS
0004  * Author: Neil Armstrong <narmstrong@baylibre.com>
0005  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 
0010 #include <drm/drm_atomic.h>
0011 #include <drm/drm_atomic_helper.h>
0012 #include <drm/drm_blend.h>
0013 #include <drm/drm_device.h>
0014 #include <drm/drm_fb_cma_helper.h>
0015 #include <drm/drm_fourcc.h>
0016 #include <drm/drm_framebuffer.h>
0017 #include <drm/drm_gem_atomic_helper.h>
0018 #include <drm/drm_gem_cma_helper.h>
0019 #include <drm/drm_plane_helper.h>
0020 
0021 #include "meson_overlay.h"
0022 #include "meson_registers.h"
0023 #include "meson_viu.h"
0024 #include "meson_vpp.h"
0025 
0026 /* VD1_IF0_GEN_REG */
0027 #define VD_URGENT_CHROMA        BIT(28)
0028 #define VD_URGENT_LUMA          BIT(27)
0029 #define VD_HOLD_LINES(lines)        FIELD_PREP(GENMASK(24, 19), lines)
0030 #define VD_DEMUX_MODE_RGB       BIT(16)
0031 #define VD_BYTES_PER_PIXEL(val)     FIELD_PREP(GENMASK(15, 14), val)
0032 #define VD_CHRO_RPT_LASTL_CTRL      BIT(6)
0033 #define VD_LITTLE_ENDIAN        BIT(4)
0034 #define VD_SEPARATE_EN          BIT(1)
0035 #define VD_ENABLE           BIT(0)
0036 
0037 /* VD1_IF0_CANVAS0 */
0038 #define CANVAS_ADDR2(addr)      FIELD_PREP(GENMASK(23, 16), addr)
0039 #define CANVAS_ADDR1(addr)      FIELD_PREP(GENMASK(15, 8), addr)
0040 #define CANVAS_ADDR0(addr)      FIELD_PREP(GENMASK(7, 0), addr)
0041 
0042 /* VD1_IF0_LUMA_X0 VD1_IF0_CHROMA_X0 */
0043 #define VD_X_START(value)       FIELD_PREP(GENMASK(14, 0), value)
0044 #define VD_X_END(value)         FIELD_PREP(GENMASK(30, 16), value)
0045 
0046 /* VD1_IF0_LUMA_Y0 VD1_IF0_CHROMA_Y0 */
0047 #define VD_Y_START(value)       FIELD_PREP(GENMASK(12, 0), value)
0048 #define VD_Y_END(value)         FIELD_PREP(GENMASK(28, 16), value)
0049 
0050 /* VD1_IF0_GEN_REG2 */
0051 #define VD_COLOR_MAP(value)     FIELD_PREP(GENMASK(1, 0), value)
0052 
0053 /* VIU_VD1_FMT_CTRL */
0054 #define VD_HORZ_Y_C_RATIO(value)    FIELD_PREP(GENMASK(22, 21), value)
0055 #define VD_HORZ_FMT_EN          BIT(20)
0056 #define VD_VERT_RPT_LINE0       BIT(16)
0057 #define VD_VERT_INITIAL_PHASE(value)    FIELD_PREP(GENMASK(11, 8), value)
0058 #define VD_VERT_PHASE_STEP(value)   FIELD_PREP(GENMASK(7, 1), value)
0059 #define VD_VERT_FMT_EN          BIT(0)
0060 
0061 /* VPP_POSTBLEND_VD1_H_START_END */
0062 #define VD_H_END(value)         FIELD_PREP(GENMASK(11, 0), value)
0063 #define VD_H_START(value)       FIELD_PREP(GENMASK(27, 16), \
0064                            ((value) & GENMASK(13, 0)))
0065 
0066 /* VPP_POSTBLEND_VD1_V_START_END */
0067 #define VD_V_END(value)         FIELD_PREP(GENMASK(11, 0), value)
0068 #define VD_V_START(value)       FIELD_PREP(GENMASK(27, 16), value)
0069 
0070 /* VPP_BLEND_VD2_V_START_END */
0071 #define VD2_V_END(value)        FIELD_PREP(GENMASK(11, 0), value)
0072 #define VD2_V_START(value)      FIELD_PREP(GENMASK(27, 16), value)
0073 
0074 /* VIU_VD1_FMT_W */
0075 #define VD_V_WIDTH(value)       FIELD_PREP(GENMASK(11, 0), value)
0076 #define VD_H_WIDTH(value)       FIELD_PREP(GENMASK(27, 16), value)
0077 
0078 /* VPP_HSC_REGION12_STARTP VPP_HSC_REGION34_STARTP */
0079 #define VD_REGION24_START(value)    FIELD_PREP(GENMASK(11, 0), value)
0080 #define VD_REGION13_END(value)      FIELD_PREP(GENMASK(27, 16), value)
0081 
0082 /* AFBC_ENABLE */
0083 #define AFBC_DEC_ENABLE         BIT(8)
0084 #define AFBC_FRM_START          BIT(0)
0085 
0086 /* AFBC_MODE */
0087 #define AFBC_HORZ_SKIP_UV(value)    FIELD_PREP(GENMASK(1, 0), value)
0088 #define AFBC_VERT_SKIP_UV(value)    FIELD_PREP(GENMASK(3, 2), value)
0089 #define AFBC_HORZ_SKIP_Y(value)     FIELD_PREP(GENMASK(5, 4), value)
0090 #define AFBC_VERT_SKIP_Y(value)     FIELD_PREP(GENMASK(7, 6), value)
0091 #define AFBC_COMPBITS_YUV(value)    FIELD_PREP(GENMASK(13, 8), value)
0092 #define AFBC_COMPBITS_8BIT      0
0093 #define AFBC_COMPBITS_10BIT     (2 | (2 << 2) | (2 << 4))
0094 #define AFBC_BURST_LEN(value)       FIELD_PREP(GENMASK(15, 14), value)
0095 #define AFBC_HOLD_LINE_NUM(value)   FIELD_PREP(GENMASK(22, 16), value)
0096 #define AFBC_MIF_URGENT(value)      FIELD_PREP(GENMASK(25, 24), value)
0097 #define AFBC_REV_MODE(value)        FIELD_PREP(GENMASK(27, 26), value)
0098 #define AFBC_BLK_MEM_MODE       BIT(28)
0099 #define AFBC_SCATTER_MODE       BIT(29)
0100 #define AFBC_SOFT_RESET         BIT(31)
0101 
0102 /* AFBC_SIZE_IN */
0103 #define AFBC_HSIZE_IN(value)        FIELD_PREP(GENMASK(28, 16), value)
0104 #define AFBC_VSIZE_IN(value)        FIELD_PREP(GENMASK(12, 0), value)
0105 
0106 /* AFBC_DEC_DEF_COLOR */
0107 #define AFBC_DEF_COLOR_Y(value)     FIELD_PREP(GENMASK(29, 20), value)
0108 #define AFBC_DEF_COLOR_U(value)     FIELD_PREP(GENMASK(19, 10), value)
0109 #define AFBC_DEF_COLOR_V(value)     FIELD_PREP(GENMASK(9, 0), value)
0110 
0111 /* AFBC_CONV_CTRL */
0112 #define AFBC_CONV_LBUF_LEN(value)   FIELD_PREP(GENMASK(11, 0), value)
0113 
0114 /* AFBC_LBUF_DEPTH */
0115 #define AFBC_DEC_LBUF_DEPTH(value)  FIELD_PREP(GENMASK(27, 16), value)
0116 #define AFBC_MIF_LBUF_DEPTH(value)  FIELD_PREP(GENMASK(11, 0), value)
0117 
0118 /* AFBC_OUT_XSCOPE/AFBC_SIZE_OUT */
0119 #define AFBC_HSIZE_OUT(value)       FIELD_PREP(GENMASK(28, 16), value)
0120 #define AFBC_VSIZE_OUT(value)       FIELD_PREP(GENMASK(12, 0), value)
0121 #define AFBC_OUT_HORZ_BGN(value)    FIELD_PREP(GENMASK(28, 16), value)
0122 #define AFBC_OUT_HORZ_END(value)    FIELD_PREP(GENMASK(12, 0), value)
0123 
0124 /* AFBC_OUT_YSCOPE */
0125 #define AFBC_OUT_VERT_BGN(value)    FIELD_PREP(GENMASK(28, 16), value)
0126 #define AFBC_OUT_VERT_END(value)    FIELD_PREP(GENMASK(12, 0), value)
0127 
0128 /* AFBC_VD_CFMT_CTRL */
0129 #define AFBC_HORZ_RPT_PIXEL0        BIT(23)
0130 #define AFBC_HORZ_Y_C_RATIO(value)  FIELD_PREP(GENMASK(22, 21), value)
0131 #define AFBC_HORZ_FMT_EN        BIT(20)
0132 #define AFBC_VERT_RPT_LINE0     BIT(16)
0133 #define AFBC_VERT_INITIAL_PHASE(value)  FIELD_PREP(GENMASK(11, 8), value)
0134 #define AFBC_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)
0135 #define AFBC_VERT_FMT_EN        BIT(0)
0136 
0137 /* AFBC_VD_CFMT_W */
0138 #define AFBC_VD_V_WIDTH(value)      FIELD_PREP(GENMASK(11, 0), value)
0139 #define AFBC_VD_H_WIDTH(value)      FIELD_PREP(GENMASK(27, 16), value)
0140 
0141 /* AFBC_MIF_HOR_SCOPE */
0142 #define AFBC_MIF_BLK_BGN_H(value)   FIELD_PREP(GENMASK(25, 16), value)
0143 #define AFBC_MIF_BLK_END_H(value)   FIELD_PREP(GENMASK(9, 0), value)
0144 
0145 /* AFBC_MIF_VER_SCOPE */
0146 #define AFBC_MIF_BLK_BGN_V(value)   FIELD_PREP(GENMASK(27, 16), value)
0147 #define AFBC_MIF_BLK_END_V(value)   FIELD_PREP(GENMASK(11, 0), value)
0148 
0149 /* AFBC_PIXEL_HOR_SCOPE */
0150 #define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), \
0151                            ((value) & GENMASK(12, 0)))
0152 #define AFBC_DEC_PIXEL_END_H(value) FIELD_PREP(GENMASK(12, 0), value)
0153 
0154 /* AFBC_PIXEL_VER_SCOPE */
0155 #define AFBC_DEC_PIXEL_BGN_V(value) FIELD_PREP(GENMASK(28, 16), value)
0156 #define AFBC_DEC_PIXEL_END_V(value) FIELD_PREP(GENMASK(12, 0), value)
0157 
0158 /* AFBC_VD_CFMT_H */
0159 #define AFBC_VD_HEIGHT(value)       FIELD_PREP(GENMASK(12, 0), value)
0160 
0161 struct meson_overlay {
0162     struct drm_plane base;
0163     struct meson_drm *priv;
0164 };
0165 #define to_meson_overlay(x) container_of(x, struct meson_overlay, base)
0166 
0167 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
0168 
0169 static int meson_overlay_atomic_check(struct drm_plane *plane,
0170                       struct drm_atomic_state *state)
0171 {
0172     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0173                                          plane);
0174     struct drm_crtc_state *crtc_state;
0175 
0176     if (!new_plane_state->crtc)
0177         return 0;
0178 
0179     crtc_state = drm_atomic_get_crtc_state(state,
0180                            new_plane_state->crtc);
0181     if (IS_ERR(crtc_state))
0182         return PTR_ERR(crtc_state);
0183 
0184     return drm_atomic_helper_check_plane_state(new_plane_state,
0185                            crtc_state,
0186                            FRAC_16_16(1, 5),
0187                            FRAC_16_16(5, 1),
0188                            true, true);
0189 }
0190 
0191 /* Takes a fixed 16.16 number and converts it to integer. */
0192 static inline int64_t fixed16_to_int(int64_t value)
0193 {
0194     return value >> 16;
0195 }
0196 
0197 static const uint8_t skip_tab[6] = {
0198     0x24, 0x04, 0x68, 0x48, 0x28, 0x08,
0199 };
0200 
0201 static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase,
0202                          int *repeat, bool interlace)
0203 {
0204     int offset_in = 0;
0205     int offset_out = 0;
0206     int repeat_skip = 0;
0207 
0208     if (!interlace && ratio_y > (1 << 18))
0209         offset_out = (1 * ratio_y) >> 10;
0210 
0211     while ((offset_in + (4 << 8)) <= offset_out) {
0212         repeat_skip++;
0213         offset_in += 4 << 8;
0214     }
0215 
0216     *phase = (offset_out - offset_in) >> 2;
0217 
0218     if (*phase > 0x100)
0219         repeat_skip++;
0220 
0221     *phase = *phase & 0xff;
0222 
0223     if (repeat_skip > 5)
0224         repeat_skip = 5;
0225 
0226     *repeat = skip_tab[repeat_skip];
0227 }
0228 
0229 static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
0230                           struct drm_plane *plane,
0231                           bool interlace_mode)
0232 {
0233     struct drm_crtc_state *crtc_state = priv->crtc->state;
0234     int video_top, video_left, video_width, video_height;
0235     struct drm_plane_state *state = plane->state;
0236     unsigned int vd_start_lines, vd_end_lines;
0237     unsigned int hd_start_lines, hd_end_lines;
0238     unsigned int crtc_height, crtc_width;
0239     unsigned int vsc_startp, vsc_endp;
0240     unsigned int hsc_startp, hsc_endp;
0241     unsigned int crop_top, crop_left;
0242     int vphase, vphase_repeat_skip;
0243     unsigned int ratio_x, ratio_y;
0244     int temp_height, temp_width;
0245     unsigned int w_in, h_in;
0246     int afbc_left, afbc_right;
0247     int afbc_top_src, afbc_bottom_src;
0248     int afbc_top, afbc_bottom;
0249     int temp, start, end;
0250 
0251     if (!crtc_state) {
0252         DRM_ERROR("Invalid crtc_state\n");
0253         return;
0254     }
0255 
0256     crtc_height = crtc_state->mode.vdisplay;
0257     crtc_width = crtc_state->mode.hdisplay;
0258 
0259     w_in = fixed16_to_int(state->src_w);
0260     h_in = fixed16_to_int(state->src_h);
0261     crop_top = fixed16_to_int(state->src_y);
0262     crop_left = fixed16_to_int(state->src_x);
0263 
0264     video_top = state->crtc_y;
0265     video_left = state->crtc_x;
0266     video_width = state->crtc_w;
0267     video_height = state->crtc_h;
0268 
0269     DRM_DEBUG("crtc_width %d crtc_height %d interlace %d\n",
0270           crtc_width, crtc_height, interlace_mode);
0271     DRM_DEBUG("w_in %d h_in %d crop_top %d crop_left %d\n",
0272           w_in, h_in, crop_top, crop_left);
0273     DRM_DEBUG("video top %d left %d width %d height %d\n",
0274           video_top, video_left, video_width, video_height);
0275 
0276     ratio_x = (w_in << 18) / video_width;
0277     ratio_y = (h_in << 18) / video_height;
0278 
0279     if (ratio_x * video_width < (w_in << 18))
0280         ratio_x++;
0281 
0282     DRM_DEBUG("ratio x 0x%x y 0x%x\n", ratio_x, ratio_y);
0283 
0284     meson_overlay_get_vertical_phase(ratio_y, &vphase, &vphase_repeat_skip,
0285                      interlace_mode);
0286 
0287     DRM_DEBUG("vphase 0x%x skip %d\n", vphase, vphase_repeat_skip);
0288 
0289     /* Vertical */
0290 
0291     start = video_top + video_height / 2 - ((h_in << 17) / ratio_y);
0292     end = (h_in << 18) / ratio_y + start - 1;
0293 
0294     if (video_top < 0 && start < 0)
0295         vd_start_lines = (-(start) * ratio_y) >> 18;
0296     else if (start < video_top)
0297         vd_start_lines = ((video_top - start) * ratio_y) >> 18;
0298     else
0299         vd_start_lines = 0;
0300 
0301     if (video_top < 0)
0302         temp_height = min_t(unsigned int,
0303                     video_top + video_height - 1,
0304                     crtc_height - 1);
0305     else
0306         temp_height = min_t(unsigned int,
0307                     video_top + video_height - 1,
0308                     crtc_height - 1) - video_top + 1;
0309 
0310     temp = vd_start_lines + (temp_height * ratio_y >> 18);
0311     vd_end_lines = (temp <= (h_in - 1)) ? temp : (h_in - 1);
0312 
0313     vd_start_lines += crop_left;
0314     vd_end_lines += crop_left;
0315 
0316     /*
0317      * TOFIX: Input frames are handled and scaled like progressive frames,
0318      * proper handling of interlaced field input frames need to be figured
0319      * out using the proper framebuffer flags set by userspace.
0320      */
0321     if (interlace_mode) {
0322         start >>= 1;
0323         end >>= 1;
0324     }
0325 
0326     vsc_startp = max_t(int, start,
0327                max_t(int, 0, video_top));
0328     vsc_endp = min_t(int, end,
0329              min_t(int, crtc_height - 1,
0330                    video_top + video_height - 1));
0331 
0332     DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n",
0333          vsc_startp, vsc_endp, vd_start_lines, vd_end_lines);
0334 
0335     afbc_top = round_down(vd_start_lines, 4);
0336     afbc_bottom = round_up(vd_end_lines + 1, 4);
0337     afbc_top_src = 0;
0338     afbc_bottom_src = round_up(h_in + 1, 4);
0339 
0340     DRM_DEBUG("afbc top %d (src %d) bottom %d (src %d)\n",
0341           afbc_top, afbc_top_src, afbc_bottom, afbc_bottom_src);
0342 
0343     /* Horizontal */
0344 
0345     start = video_left + video_width / 2 - ((w_in << 17) / ratio_x);
0346     end = (w_in << 18) / ratio_x + start - 1;
0347 
0348     if (video_left < 0 && start < 0)
0349         hd_start_lines = (-(start) * ratio_x) >> 18;
0350     else if (start < video_left)
0351         hd_start_lines = ((video_left - start) * ratio_x) >> 18;
0352     else
0353         hd_start_lines = 0;
0354 
0355     if (video_left < 0)
0356         temp_width = min_t(unsigned int,
0357                    video_left + video_width - 1,
0358                    crtc_width - 1);
0359     else
0360         temp_width = min_t(unsigned int,
0361                    video_left + video_width - 1,
0362                    crtc_width - 1) - video_left + 1;
0363 
0364     temp = hd_start_lines + (temp_width * ratio_x >> 18);
0365     hd_end_lines = (temp <= (w_in - 1)) ? temp : (w_in - 1);
0366 
0367     priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
0368     hsc_startp = max_t(int, start, max_t(int, 0, video_left));
0369     hsc_endp = min_t(int, end, min_t(int, crtc_width - 1,
0370                      video_left + video_width - 1));
0371 
0372     hd_start_lines += crop_top;
0373     hd_end_lines += crop_top;
0374 
0375     DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n",
0376          hsc_startp, hsc_endp, hd_start_lines, hd_end_lines);
0377 
0378     if (hd_start_lines > 0 || (hd_end_lines < w_in)) {
0379         afbc_left = 0;
0380         afbc_right = round_up(w_in, 32);
0381     } else {
0382         afbc_left = round_down(hd_start_lines, 32);
0383         afbc_right = round_up(hd_end_lines + 1, 32);
0384     }
0385 
0386     DRM_DEBUG("afbc left %d right %d\n", afbc_left, afbc_right);
0387 
0388     priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
0389 
0390     priv->viu.vpp_vsc_ini_phase = vphase << 8;
0391     priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) |
0392                        vphase_repeat_skip;
0393 
0394     priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) |
0395                     VD_X_END(hd_end_lines);
0396     priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) |
0397                       VD_X_END(hd_end_lines >> 1);
0398 
0399     priv->viu.viu_vd1_fmt_w =
0400             VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) |
0401             VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1);
0402 
0403     priv->viu.vd1_afbc_vd_cfmt_w =
0404             AFBC_VD_H_WIDTH(afbc_right - afbc_left) |
0405             AFBC_VD_V_WIDTH(afbc_right / 2 - afbc_left / 2);
0406 
0407     priv->viu.vd1_afbc_vd_cfmt_h =
0408             AFBC_VD_HEIGHT((afbc_bottom - afbc_top) / 2);
0409 
0410     priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) |
0411                 AFBC_MIF_BLK_END_H((afbc_right / 32) - 1);
0412 
0413     priv->viu.vd1_afbc_mif_ver_scope = AFBC_MIF_BLK_BGN_V(afbc_top / 4) |
0414                 AFBC_MIF_BLK_END_H((afbc_bottom / 4) - 1);
0415 
0416     priv->viu.vd1_afbc_size_out =
0417             AFBC_HSIZE_OUT(afbc_right - afbc_left) |
0418             AFBC_VSIZE_OUT(afbc_bottom - afbc_top);
0419 
0420     priv->viu.vd1_afbc_pixel_hor_scope =
0421             AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) |
0422             AFBC_DEC_PIXEL_END_H(hd_end_lines - afbc_left);
0423 
0424     priv->viu.vd1_afbc_pixel_ver_scope =
0425             AFBC_DEC_PIXEL_BGN_V(vd_start_lines - afbc_top) |
0426             AFBC_DEC_PIXEL_END_V(vd_end_lines - afbc_top);
0427 
0428     priv->viu.vd1_afbc_size_in =
0429                 AFBC_HSIZE_IN(afbc_right - afbc_left) |
0430                 AFBC_VSIZE_IN(afbc_bottom_src - afbc_top_src);
0431 
0432     priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) |
0433                     VD_Y_END(vd_end_lines);
0434 
0435     priv->viu.vd1_if0_chroma_y0 = VD_Y_START(vd_start_lines >> 1) |
0436                       VD_Y_END(vd_end_lines >> 1);
0437 
0438     priv->viu.vpp_pic_in_height = h_in;
0439 
0440     priv->viu.vpp_postblend_vd1_h_start_end = VD_H_START(hsc_startp) |
0441                           VD_H_END(hsc_endp);
0442     priv->viu.vpp_blend_vd2_h_start_end = VD_H_START(hd_start_lines) |
0443                           VD_H_END(hd_end_lines);
0444     priv->viu.vpp_hsc_region12_startp = VD_REGION13_END(0) |
0445                         VD_REGION24_START(hsc_startp);
0446     priv->viu.vpp_hsc_region34_startp =
0447                 VD_REGION13_END(hsc_startp) |
0448                 VD_REGION24_START(hsc_endp - hsc_startp);
0449     priv->viu.vpp_hsc_region4_endp = hsc_endp - hsc_startp;
0450     priv->viu.vpp_hsc_start_phase_step = ratio_x << 6;
0451     priv->viu.vpp_hsc_region1_phase_slope = 0;
0452     priv->viu.vpp_hsc_region3_phase_slope = 0;
0453     priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16);
0454 
0455     priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
0456     priv->viu.vpp_preblend_h_size = hd_end_lines - hd_start_lines + 1;
0457 
0458     priv->viu.vpp_postblend_vd1_v_start_end = VD_V_START(vsc_startp) |
0459                           VD_V_END(vsc_endp);
0460     priv->viu.vpp_blend_vd2_v_start_end =
0461                 VD2_V_START((vd_end_lines + 1) >> 1) |
0462                 VD2_V_END(vd_end_lines);
0463 
0464     priv->viu.vpp_vsc_region12_startp = 0;
0465     priv->viu.vpp_vsc_region34_startp =
0466                 VD_REGION13_END(vsc_endp - vsc_startp) |
0467                 VD_REGION24_START(vsc_endp - vsc_startp);
0468     priv->viu.vpp_vsc_region4_endp = vsc_endp - vsc_startp;
0469     priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
0470 }
0471 
0472 static void meson_overlay_atomic_update(struct drm_plane *plane,
0473                     struct drm_atomic_state *state)
0474 {
0475     struct meson_overlay *meson_overlay = to_meson_overlay(plane);
0476     struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
0477                                        plane);
0478     struct drm_framebuffer *fb = new_state->fb;
0479     struct meson_drm *priv = meson_overlay->priv;
0480     struct drm_gem_cma_object *gem;
0481     unsigned long flags;
0482     bool interlace_mode;
0483 
0484     DRM_DEBUG_DRIVER("\n");
0485 
0486     interlace_mode = new_state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE;
0487 
0488     spin_lock_irqsave(&priv->drm->event_lock, flags);
0489 
0490     if ((fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
0491                 DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
0492         priv->viu.vd1_afbc = true;
0493 
0494         priv->viu.vd1_afbc_mode = AFBC_MIF_URGENT(3) |
0495                       AFBC_HOLD_LINE_NUM(8) |
0496                       AFBC_BURST_LEN(2);
0497 
0498         if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0,
0499                         AMLOGIC_FBC_OPTION_MEM_SAVING))
0500             priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE;
0501 
0502         if ((fb->modifier & __fourcc_mod_amlogic_layout_mask) ==
0503                 AMLOGIC_FBC_LAYOUT_SCATTER)
0504             priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE;
0505 
0506         priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE;
0507 
0508         priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256);
0509 
0510         priv->viu.vd1_afbc_dec_def_color = AFBC_DEF_COLOR_Y(1023);
0511 
0512         /* 420: horizontal / 2, vertical / 4 */
0513         priv->viu.vd1_afbc_vd_cfmt_ctrl = AFBC_HORZ_RPT_PIXEL0 |
0514                           AFBC_HORZ_Y_C_RATIO(1) |
0515                           AFBC_HORZ_FMT_EN |
0516                           AFBC_VERT_RPT_LINE0 |
0517                           AFBC_VERT_INITIAL_PHASE(12) |
0518                           AFBC_VERT_PHASE_STEP(8) |
0519                           AFBC_VERT_FMT_EN;
0520 
0521         switch (fb->format->format) {
0522         /* AFBC Only formats */
0523         case DRM_FORMAT_YUV420_10BIT:
0524             priv->viu.vd1_afbc_mode |=
0525                 AFBC_COMPBITS_YUV(AFBC_COMPBITS_10BIT);
0526             priv->viu.vd1_afbc_dec_def_color |=
0527                     AFBC_DEF_COLOR_U(512) |
0528                     AFBC_DEF_COLOR_V(512);
0529             break;
0530         case DRM_FORMAT_YUV420_8BIT:
0531             priv->viu.vd1_afbc_dec_def_color |=
0532                     AFBC_DEF_COLOR_U(128) |
0533                     AFBC_DEF_COLOR_V(128);
0534             break;
0535         }
0536 
0537         priv->viu.vd1_if0_gen_reg = 0;
0538         priv->viu.vd1_if0_canvas0 = 0;
0539         priv->viu.viu_vd1_fmt_ctrl = 0;
0540     } else {
0541         priv->viu.vd1_afbc = false;
0542 
0543         priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA |
0544                         VD_URGENT_LUMA |
0545                         VD_HOLD_LINES(9) |
0546                         VD_CHRO_RPT_LASTL_CTRL |
0547                         VD_ENABLE;
0548     }
0549 
0550     /* Setup scaler params */
0551     meson_overlay_setup_scaler_params(priv, plane, interlace_mode);
0552 
0553     priv->viu.vd1_if0_repeat_loop = 0;
0554     priv->viu.vd1_if0_luma0_rpt_pat = interlace_mode ? 8 : 0;
0555     priv->viu.vd1_if0_chroma0_rpt_pat = interlace_mode ? 8 : 0;
0556     priv->viu.vd1_range_map_y = 0;
0557     priv->viu.vd1_range_map_cb = 0;
0558     priv->viu.vd1_range_map_cr = 0;
0559 
0560     /* Default values for RGB888/YUV444 */
0561     priv->viu.vd1_if0_gen_reg2 = 0;
0562     priv->viu.viu_vd1_fmt_ctrl = 0;
0563 
0564     /* None will match for AFBC Only formats */
0565     switch (fb->format->format) {
0566     /* TOFIX DRM_FORMAT_RGB888 should be supported */
0567     case DRM_FORMAT_YUYV:
0568         priv->viu.vd1_if0_gen_reg |= VD_BYTES_PER_PIXEL(1);
0569         priv->viu.vd1_if0_canvas0 =
0570                     CANVAS_ADDR2(priv->canvas_id_vd1_0) |
0571                     CANVAS_ADDR1(priv->canvas_id_vd1_0) |
0572                     CANVAS_ADDR0(priv->canvas_id_vd1_0);
0573         priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
0574                          VD_HORZ_FMT_EN |
0575                          VD_VERT_RPT_LINE0 |
0576                          VD_VERT_INITIAL_PHASE(12) |
0577                          VD_VERT_PHASE_STEP(16) | /* /2 */
0578                          VD_VERT_FMT_EN;
0579         break;
0580     case DRM_FORMAT_NV12:
0581     case DRM_FORMAT_NV21:
0582         priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
0583         priv->viu.vd1_if0_canvas0 =
0584                     CANVAS_ADDR2(priv->canvas_id_vd1_1) |
0585                     CANVAS_ADDR1(priv->canvas_id_vd1_1) |
0586                     CANVAS_ADDR0(priv->canvas_id_vd1_0);
0587         if (fb->format->format == DRM_FORMAT_NV12)
0588             priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(1);
0589         else
0590             priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(2);
0591         priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
0592                          VD_HORZ_FMT_EN |
0593                          VD_VERT_RPT_LINE0 |
0594                          VD_VERT_INITIAL_PHASE(12) |
0595                          VD_VERT_PHASE_STEP(8) | /* /4 */
0596                          VD_VERT_FMT_EN;
0597         break;
0598     case DRM_FORMAT_YUV444:
0599     case DRM_FORMAT_YUV422:
0600     case DRM_FORMAT_YUV420:
0601     case DRM_FORMAT_YUV411:
0602     case DRM_FORMAT_YUV410:
0603         priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
0604         priv->viu.vd1_if0_canvas0 =
0605                     CANVAS_ADDR2(priv->canvas_id_vd1_2) |
0606                     CANVAS_ADDR1(priv->canvas_id_vd1_1) |
0607                     CANVAS_ADDR0(priv->canvas_id_vd1_0);
0608         switch (fb->format->format) {
0609         case DRM_FORMAT_YUV422:
0610             priv->viu.viu_vd1_fmt_ctrl =
0611                     VD_HORZ_Y_C_RATIO(1) | /* /2 */
0612                     VD_HORZ_FMT_EN |
0613                     VD_VERT_RPT_LINE0 |
0614                     VD_VERT_INITIAL_PHASE(12) |
0615                     VD_VERT_PHASE_STEP(16) | /* /2 */
0616                     VD_VERT_FMT_EN;
0617             break;
0618         case DRM_FORMAT_YUV420:
0619             priv->viu.viu_vd1_fmt_ctrl =
0620                     VD_HORZ_Y_C_RATIO(1) | /* /2 */
0621                     VD_HORZ_FMT_EN |
0622                     VD_VERT_RPT_LINE0 |
0623                     VD_VERT_INITIAL_PHASE(12) |
0624                     VD_VERT_PHASE_STEP(8) | /* /4 */
0625                     VD_VERT_FMT_EN;
0626             break;
0627         case DRM_FORMAT_YUV411:
0628             priv->viu.viu_vd1_fmt_ctrl =
0629                     VD_HORZ_Y_C_RATIO(2) | /* /4 */
0630                     VD_HORZ_FMT_EN |
0631                     VD_VERT_RPT_LINE0 |
0632                     VD_VERT_INITIAL_PHASE(12) |
0633                     VD_VERT_PHASE_STEP(16) | /* /2 */
0634                     VD_VERT_FMT_EN;
0635             break;
0636         case DRM_FORMAT_YUV410:
0637             priv->viu.viu_vd1_fmt_ctrl =
0638                     VD_HORZ_Y_C_RATIO(2) | /* /4 */
0639                     VD_HORZ_FMT_EN |
0640                     VD_VERT_RPT_LINE0 |
0641                     VD_VERT_INITIAL_PHASE(12) |
0642                     VD_VERT_PHASE_STEP(8) | /* /4 */
0643                     VD_VERT_FMT_EN;
0644             break;
0645         }
0646         break;
0647     }
0648 
0649     /* Update Canvas with buffer address */
0650     priv->viu.vd1_planes = fb->format->num_planes;
0651 
0652     switch (priv->viu.vd1_planes) {
0653     case 3:
0654         gem = drm_fb_cma_get_gem_obj(fb, 2);
0655         priv->viu.vd1_addr2 = gem->paddr + fb->offsets[2];
0656         priv->viu.vd1_stride2 = fb->pitches[2];
0657         priv->viu.vd1_height2 =
0658             drm_format_info_plane_height(fb->format,
0659                         fb->height, 2);
0660         DRM_DEBUG("plane 2 addr 0x%x stride %d height %d\n",
0661              priv->viu.vd1_addr2,
0662              priv->viu.vd1_stride2,
0663              priv->viu.vd1_height2);
0664         fallthrough;
0665     case 2:
0666         gem = drm_fb_cma_get_gem_obj(fb, 1);
0667         priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1];
0668         priv->viu.vd1_stride1 = fb->pitches[1];
0669         priv->viu.vd1_height1 =
0670             drm_format_info_plane_height(fb->format,
0671                         fb->height, 1);
0672         DRM_DEBUG("plane 1 addr 0x%x stride %d height %d\n",
0673              priv->viu.vd1_addr1,
0674              priv->viu.vd1_stride1,
0675              priv->viu.vd1_height1);
0676         fallthrough;
0677     case 1:
0678         gem = drm_fb_cma_get_gem_obj(fb, 0);
0679         priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0];
0680         priv->viu.vd1_stride0 = fb->pitches[0];
0681         priv->viu.vd1_height0 =
0682             drm_format_info_plane_height(fb->format,
0683                              fb->height, 0);
0684         DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n",
0685              priv->viu.vd1_addr0,
0686              priv->viu.vd1_stride0,
0687              priv->viu.vd1_height0);
0688     }
0689 
0690     if (priv->viu.vd1_afbc) {
0691         if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) {
0692             /*
0693              * In Scatter mode, the header contains the physical
0694              * body content layout, thus the body content
0695              * size isn't needed.
0696              */
0697             priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4;
0698             priv->viu.vd1_afbc_body_addr = 0;
0699         } else {
0700             /* Default mode is 4k per superblock */
0701             unsigned long block_size = 4096;
0702             unsigned long body_size;
0703 
0704             /* 8bit mem saving mode is 3072bytes per superblock */
0705             if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE)
0706                 block_size = 3072;
0707 
0708             body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) *
0709                     (ALIGN(priv->viu.vd1_height0, 32) / 32) *
0710                     block_size;
0711 
0712             priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4;
0713             /* Header is after body content */
0714             priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 +
0715                             body_size) >> 4;
0716         }
0717     }
0718 
0719     priv->viu.vd1_enabled = true;
0720 
0721     spin_unlock_irqrestore(&priv->drm->event_lock, flags);
0722 
0723     DRM_DEBUG_DRIVER("\n");
0724 }
0725 
0726 static void meson_overlay_atomic_disable(struct drm_plane *plane,
0727                        struct drm_atomic_state *state)
0728 {
0729     struct meson_overlay *meson_overlay = to_meson_overlay(plane);
0730     struct meson_drm *priv = meson_overlay->priv;
0731 
0732     DRM_DEBUG_DRIVER("\n");
0733 
0734     priv->viu.vd1_enabled = false;
0735 
0736     /* Disable VD1 */
0737     if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
0738         writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
0739         writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
0740         writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
0741         writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0));
0742     } else
0743         writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0,
0744                     priv->io_base + _REG(VPP_MISC));
0745 
0746 }
0747 
0748 static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = {
0749     .atomic_check   = meson_overlay_atomic_check,
0750     .atomic_disable = meson_overlay_atomic_disable,
0751     .atomic_update  = meson_overlay_atomic_update,
0752 };
0753 
0754 static bool meson_overlay_format_mod_supported(struct drm_plane *plane,
0755                            u32 format, u64 modifier)
0756 {
0757     if (modifier == DRM_FORMAT_MOD_LINEAR &&
0758         format != DRM_FORMAT_YUV420_8BIT &&
0759         format != DRM_FORMAT_YUV420_10BIT)
0760         return true;
0761 
0762     if ((modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
0763             DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
0764         unsigned int layout = modifier &
0765             DRM_FORMAT_MOD_AMLOGIC_FBC(
0766                 __fourcc_mod_amlogic_layout_mask, 0);
0767         unsigned int options =
0768             (modifier >> __fourcc_mod_amlogic_options_shift) &
0769             __fourcc_mod_amlogic_options_mask;
0770 
0771         if (format != DRM_FORMAT_YUV420_8BIT &&
0772             format != DRM_FORMAT_YUV420_10BIT) {
0773             DRM_DEBUG_KMS("%llx invalid format 0x%08x\n",
0774                       modifier, format);
0775             return false;
0776         }
0777 
0778         if (layout != AMLOGIC_FBC_LAYOUT_BASIC &&
0779             layout != AMLOGIC_FBC_LAYOUT_SCATTER) {
0780             DRM_DEBUG_KMS("%llx invalid layout %x\n",
0781                       modifier, layout);
0782             return false;
0783         }
0784 
0785         if (options &&
0786             options != AMLOGIC_FBC_OPTION_MEM_SAVING) {
0787             DRM_DEBUG_KMS("%llx invalid layout %x\n",
0788                       modifier, layout);
0789             return false;
0790         }
0791 
0792         return true;
0793     }
0794 
0795     DRM_DEBUG_KMS("invalid modifier %llx for format 0x%08x\n",
0796               modifier, format);
0797 
0798     return false;
0799 }
0800 
0801 static const struct drm_plane_funcs meson_overlay_funcs = {
0802     .update_plane       = drm_atomic_helper_update_plane,
0803     .disable_plane      = drm_atomic_helper_disable_plane,
0804     .destroy        = drm_plane_cleanup,
0805     .reset          = drm_atomic_helper_plane_reset,
0806     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
0807     .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
0808     .format_mod_supported   = meson_overlay_format_mod_supported,
0809 };
0810 
0811 static const uint32_t supported_drm_formats[] = {
0812     DRM_FORMAT_YUYV,
0813     DRM_FORMAT_NV12,
0814     DRM_FORMAT_NV21,
0815     DRM_FORMAT_YUV444,
0816     DRM_FORMAT_YUV422,
0817     DRM_FORMAT_YUV420,
0818     DRM_FORMAT_YUV411,
0819     DRM_FORMAT_YUV410,
0820     DRM_FORMAT_YUV420_8BIT, /* Amlogic FBC Only */
0821     DRM_FORMAT_YUV420_10BIT, /* Amlogic FBC Only */
0822 };
0823 
0824 static const uint64_t format_modifiers[] = {
0825     DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,
0826                    AMLOGIC_FBC_OPTION_MEM_SAVING),
0827     DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC,
0828                    AMLOGIC_FBC_OPTION_MEM_SAVING),
0829     DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 0),
0830     DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0),
0831     DRM_FORMAT_MOD_LINEAR,
0832     DRM_FORMAT_MOD_INVALID,
0833 };
0834 
0835 int meson_overlay_create(struct meson_drm *priv)
0836 {
0837     struct meson_overlay *meson_overlay;
0838     struct drm_plane *plane;
0839 
0840     DRM_DEBUG_DRIVER("\n");
0841 
0842     meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay),
0843                    GFP_KERNEL);
0844     if (!meson_overlay)
0845         return -ENOMEM;
0846 
0847     meson_overlay->priv = priv;
0848     plane = &meson_overlay->base;
0849 
0850     drm_universal_plane_init(priv->drm, plane, 0xFF,
0851                  &meson_overlay_funcs,
0852                  supported_drm_formats,
0853                  ARRAY_SIZE(supported_drm_formats),
0854                  format_modifiers,
0855                  DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane");
0856 
0857     drm_plane_helper_add(plane, &meson_overlay_helper_funcs);
0858 
0859     /* For now, VD Overlay plane is always on the back */
0860     drm_plane_create_zpos_immutable_property(plane, 0);
0861 
0862     priv->overlay_plane = plane;
0863 
0864     DRM_DEBUG_DRIVER("\n");
0865 
0866     return 0;
0867 }
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