drm/meson/meson_dw_hdmi.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2016 BayLibre, SAS
0004  * Author: Neil Armstrong <narmstrong@baylibre.com>
0005  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
0006  */
0007
0008 #ifndef __MESON_DW_HDMI_H
0009 #define __MESON_DW_HDMI_H
0010
0011 /*
0012  * Bit 15-10: RW Reserved. Default 1 starting from G12A
0013  * Bit 9 RW sw_reset_i2c starting from G12A
0014  * Bit 8 RW sw_reset_axiarb starting from G12A
0015  * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
0016  * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
0017  * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
0018  * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
0019  *     Default 1.
0020  * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
0021  *     0=Release from reset.
0022  *     Default 1.
0023  * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
0024  *     Default 1.
0025  * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
0026  *     0=Release from reset. Default 1.
0027  * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
0028  *     0=Release from reset. Default 1.
0029  */
0030 #define HDMITX_TOP_SW_RESET                     (0x000)
0031
0032 /*
0033  * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable
0034  * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
0035  * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
0036  * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
0037  * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
0038  * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
0039  * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
0040  * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable
0041  * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable
0042  * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A
0043  * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
0044  * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
0045  * Bit 1 RW tmds_clk_en: 1=enable tmds_clk;  0=disable. Default 0.
0046  * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0.
0047  */
0048 #define HDMITX_TOP_CLK_CNTL                     (0x001)
0049
0050 /*
0051  * Bit 31:28 RW rxsense_glitch_width: starting from G12A
0052  * Bit 27:16 RW rxsense_valid_width: starting from G12A
0053  * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024.    Default 0.
0054  * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N.       Default 0.
0055  */
0056 #define HDMITX_TOP_HPD_FILTER                   (0x002)
0057
0058 /*
0059  * intr_maskn: MASK_N, one bit per interrupt source.
0060  *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
0061  * [  7] rxsense_fall starting from G12A
0062  * [  6] rxsense_rise starting from G12A
0063  * [  5] err_i2c_timeout starting from G12A
0064  * [  4] hdcp22_rndnum_err
0065  * [  3] nonce_rfrsh_rise
0066  * [  2] hpd_fall_intr
0067  * [  1] hpd_rise_intr
0068  * [  0] core_intr
0069  */
0070 #define HDMITX_TOP_INTR_MASKN                   (0x003)
0071
0072 /*
0073  * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
0074  *     bit, read back the interrupt status.
0075  * Bit    31 R  IP interrupt status
0076  * Bit     7 RW rxsense_fall starting from G12A
0077  * Bit     6 RW rxsense_rise starting from G12A
0078  * Bit     5 RW err_i2c_timeout starting from G12A
0079  * Bit     2 RW hpd_fall
0080  * Bit     1 RW hpd_rise
0081  * Bit     0 RW IP interrupt
0082  */
0083 #define HDMITX_TOP_INTR_STAT                    (0x004)
0084
0085 /*
0086  * [7]    rxsense_fall starting from G12A
0087  * [6]    rxsense_rise starting from G12A
0088  * [5]    err_i2c_timeout starting from G12A
0089  * [4]    hdcp22_rndnum_err
0090  * [3]    nonce_rfrsh_rise
0091  * [2]    hpd_fall
0092  * [1]    hpd_rise
0093  * [0]    core_intr_rise
0094  */
0095 #define HDMITX_TOP_INTR_STAT_CLR                (0x005)
0096
0097 #define HDMITX_TOP_INTR_CORE        BIT(0)
0098 #define HDMITX_TOP_INTR_HPD_RISE    BIT(1)
0099 #define HDMITX_TOP_INTR_HPD_FALL    BIT(2)
0100 #define HDMITX_TOP_INTR_RXSENSE_RISE    BIT(6)
0101 #define HDMITX_TOP_INTR_RXSENSE_FALL    BIT(7)
0102
0103 /*
0104  * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
0105  *     3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
0106  * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern
0107  *     every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
0108  * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable.
0109  *     Default 0.
0110  * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0.
0111  * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern;
0112  *     2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
0113  * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.
0114  */
0115 #define HDMITX_TOP_BIST_CNTL                    (0x006)
0116
0117 /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */
0118 /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */
0119 /* Bit  9: 0 RW shift_pttn_data[79:70]. Default 0. */
0120 #define HDMITX_TOP_SHIFT_PTTN_012               (0x007)
0121
0122 /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */
0123 /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */
0124 /* Bit  9: 0 RW shift_pttn_data[49:40]. Default 0. */
0125 #define HDMITX_TOP_SHIFT_PTTN_345               (0x008)
0126
0127 /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */
0128 /* Bit  9: 0 RW shift_pttn_data[19:10]. Default 0. */
0129 #define HDMITX_TOP_SHIFT_PTTN_67                (0x009)
0130
0131 /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */
0132 /* Bit  9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */
0133 #define HDMITX_TOP_TMDS_CLK_PTTN_01             (0x00A)
0134
0135 /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */
0136 /* Bit  9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
0137 #define HDMITX_TOP_TMDS_CLK_PTTN_23             (0x00B)
0138
0139 /*
0140  * Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
0141  * used when TMDS CLK rate = TMDS character rate /4. Default 0.
0142  * Bit 0 R  Reserved. Default 0.
0143  * [    1] shift_tmds_clk_pttn
0144  * [    0] load_tmds_clk_pttn
0145  */
0146 #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL           (0x00C)
0147
0148 /*
0149  * Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
0150  * failure, write 1 to clear the failure flag.  Default 0.
0151  */
0152 #define HDMITX_TOP_REVOCMEM_STAT                (0x00D)
0153
0154 /*
0155  * Bit     1 R  filtered RxSense status
0156  * Bit     0 R  filtered HPD status.
0157  */
0158 #define HDMITX_TOP_STAT0                        (0x00E)
0159
0160 #endif /* __MESON_DW_HDMI_H */