drm/meson/meson_drv.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2016 BayLibre, SAS
0004  * Author: Neil Armstrong <narmstrong@baylibre.com>
0005  */
0006
0007 #ifndef __MESON_DRV_H
0008 #define __MESON_DRV_H
0009
0010 #include <linux/device.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/regmap.h>
0014
0015 struct drm_crtc;
0016 struct drm_device;
0017 struct drm_plane;
0018 struct meson_drm;
0019 struct meson_afbcd_ops;
0020
0021 enum vpu_compatible {
0022     VPU_COMPATIBLE_GXBB = 0,
0023     VPU_COMPATIBLE_GXL  = 1,
0024     VPU_COMPATIBLE_GXM  = 2,
0025     VPU_COMPATIBLE_G12A = 3,
0026 };
0027
0028 struct meson_drm_match_data {
0029     enum vpu_compatible compat;
0030     struct meson_afbcd_ops *afbcd_ops;
0031 };
0032
0033 struct meson_drm_soc_limits {
0034     unsigned int max_hdmi_phy_freq;
0035 };
0036
0037 struct meson_drm {
0038     struct device *dev;
0039     enum vpu_compatible compat;
0040     void __iomem *io_base;
0041     struct regmap *hhi;
0042     int vsync_irq;
0043
0044     struct meson_canvas *canvas;
0045     u8 canvas_id_osd1;
0046     u8 canvas_id_vd1_0;
0047     u8 canvas_id_vd1_1;
0048     u8 canvas_id_vd1_2;
0049
0050     struct drm_device *drm;
0051     struct drm_crtc *crtc;
0052     struct drm_plane *primary_plane;
0053     struct drm_plane *overlay_plane;
0054
0055     const struct meson_drm_soc_limits *limits;
0056
0057     /* Components Data */
0058     struct {
0059         bool osd1_enabled;
0060         bool osd1_interlace;
0061         bool osd1_commit;
0062         bool osd1_afbcd;
0063         uint32_t osd1_ctrl_stat;
0064         uint32_t osd1_ctrl_stat2;
0065         uint32_t osd1_blk0_cfg[5];
0066         uint32_t osd1_blk1_cfg4;
0067         uint32_t osd1_blk2_cfg4;
0068         uint32_t osd1_addr;
0069         uint32_t osd1_stride;
0070         uint32_t osd1_height;
0071         uint32_t osd1_width;
0072         uint32_t osd_sc_ctrl0;
0073         uint32_t osd_sc_i_wh_m1;
0074         uint32_t osd_sc_o_h_start_end;
0075         uint32_t osd_sc_o_v_start_end;
0076         uint32_t osd_sc_v_ini_phase;
0077         uint32_t osd_sc_v_phase_step;
0078         uint32_t osd_sc_h_ini_phase;
0079         uint32_t osd_sc_h_phase_step;
0080         uint32_t osd_sc_h_ctrl0;
0081         uint32_t osd_sc_v_ctrl0;
0082         uint32_t osd_blend_din0_scope_h;
0083         uint32_t osd_blend_din0_scope_v;
0084         uint32_t osb_blend0_size;
0085         uint32_t osb_blend1_size;
0086
0087         bool vd1_enabled;
0088         bool vd1_commit;
0089         bool vd1_afbc;
0090         unsigned int vd1_planes;
0091         uint32_t vd1_if0_gen_reg;
0092         uint32_t vd1_if0_luma_x0;
0093         uint32_t vd1_if0_luma_y0;
0094         uint32_t vd1_if0_chroma_x0;
0095         uint32_t vd1_if0_chroma_y0;
0096         uint32_t vd1_if0_repeat_loop;
0097         uint32_t vd1_if0_luma0_rpt_pat;
0098         uint32_t vd1_if0_chroma0_rpt_pat;
0099         uint32_t vd1_range_map_y;
0100         uint32_t vd1_range_map_cb;
0101         uint32_t vd1_range_map_cr;
0102         uint32_t viu_vd1_fmt_w;
0103         uint32_t vd1_if0_canvas0;
0104         uint32_t vd1_if0_gen_reg2;
0105         uint32_t viu_vd1_fmt_ctrl;
0106         uint32_t vd1_addr0;
0107         uint32_t vd1_addr1;
0108         uint32_t vd1_addr2;
0109         uint32_t vd1_stride0;
0110         uint32_t vd1_stride1;
0111         uint32_t vd1_stride2;
0112         uint32_t vd1_height0;
0113         uint32_t vd1_height1;
0114         uint32_t vd1_height2;
0115         uint32_t vd1_afbc_mode;
0116         uint32_t vd1_afbc_en;
0117         uint32_t vd1_afbc_head_addr;
0118         uint32_t vd1_afbc_body_addr;
0119         uint32_t vd1_afbc_conv_ctrl;
0120         uint32_t vd1_afbc_dec_def_color;
0121         uint32_t vd1_afbc_vd_cfmt_ctrl;
0122         uint32_t vd1_afbc_vd_cfmt_w;
0123         uint32_t vd1_afbc_vd_cfmt_h;
0124         uint32_t vd1_afbc_mif_hor_scope;
0125         uint32_t vd1_afbc_mif_ver_scope;
0126         uint32_t vd1_afbc_size_out;
0127         uint32_t vd1_afbc_pixel_hor_scope;
0128         uint32_t vd1_afbc_pixel_ver_scope;
0129         uint32_t vd1_afbc_size_in;
0130         uint32_t vpp_pic_in_height;
0131         uint32_t vpp_postblend_vd1_h_start_end;
0132         uint32_t vpp_postblend_vd1_v_start_end;
0133         uint32_t vpp_hsc_region12_startp;
0134         uint32_t vpp_hsc_region34_startp;
0135         uint32_t vpp_hsc_region4_endp;
0136         uint32_t vpp_hsc_start_phase_step;
0137         uint32_t vpp_hsc_region1_phase_slope;
0138         uint32_t vpp_hsc_region3_phase_slope;
0139         uint32_t vpp_line_in_length;
0140         uint32_t vpp_preblend_h_size;
0141         uint32_t vpp_vsc_region12_startp;
0142         uint32_t vpp_vsc_region34_startp;
0143         uint32_t vpp_vsc_region4_endp;
0144         uint32_t vpp_vsc_start_phase_step;
0145         uint32_t vpp_vsc_ini_phase;
0146         uint32_t vpp_vsc_phase_ctrl;
0147         uint32_t vpp_hsc_phase_ctrl;
0148         uint32_t vpp_blend_vd2_h_start_end;
0149         uint32_t vpp_blend_vd2_v_start_end;
0150     } viu;
0151
0152     struct {
0153         unsigned int current_mode;
0154         bool hdmi_repeat;
0155         bool venc_repeat;
0156         bool hdmi_use_enci;
0157     } venc;
0158
0159     struct {
0160         dma_addr_t addr_dma;
0161         uint32_t *addr;
0162         unsigned int offset;
0163     } rdma;
0164
0165     struct {
0166         struct meson_afbcd_ops *ops;
0167         u64 modifier;
0168         u32 format;
0169     } afbcd;
0170 };
0171
0172 static inline int meson_vpu_is_compatible(struct meson_drm *priv,
0173                       enum vpu_compatible family)
0174 {
0175     return priv->compat == family;
0176 }
0177
0178 #endif /* __MESON_DRV_H */