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0006 #include <linux/kernel.h>
0007 #include <linux/module.h>
0008 #include <linux/i2c.h>
0009 #include <linux/time.h>
0010 #include <linux/delay.h>
0011 #include <linux/errno.h>
0012 #include <linux/err.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/clk.h>
0015 #include <linux/slab.h>
0016 #include <linux/io.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/of_platform.h>
0021
0022 #define SIF1_CLOK (288)
0023 #define DDC_DDCMCTL0 (0x0)
0024 #define DDCM_ODRAIN BIT(31)
0025 #define DDCM_CLK_DIV_OFFSET (16)
0026 #define DDCM_CLK_DIV_MASK (0xfff << 16)
0027 #define DDCM_CS_STATUS BIT(4)
0028 #define DDCM_SCL_STATE BIT(3)
0029 #define DDCM_SDA_STATE BIT(2)
0030 #define DDCM_SM0EN BIT(1)
0031 #define DDCM_SCL_STRECH BIT(0)
0032 #define DDC_DDCMCTL1 (0x4)
0033 #define DDCM_ACK_OFFSET (16)
0034 #define DDCM_ACK_MASK (0xff << 16)
0035 #define DDCM_PGLEN_OFFSET (8)
0036 #define DDCM_PGLEN_MASK (0x7 << 8)
0037 #define DDCM_SIF_MODE_OFFSET (4)
0038 #define DDCM_SIF_MODE_MASK (0x7 << 4)
0039 #define DDCM_START (0x1)
0040 #define DDCM_WRITE_DATA (0x2)
0041 #define DDCM_STOP (0x3)
0042 #define DDCM_READ_DATA_NO_ACK (0x4)
0043 #define DDCM_READ_DATA_ACK (0x5)
0044 #define DDCM_TRI BIT(0)
0045 #define DDC_DDCMD0 (0x8)
0046 #define DDCM_DATA3 (0xff << 24)
0047 #define DDCM_DATA2 (0xff << 16)
0048 #define DDCM_DATA1 (0xff << 8)
0049 #define DDCM_DATA0 (0xff << 0)
0050 #define DDC_DDCMD1 (0xc)
0051 #define DDCM_DATA7 (0xff << 24)
0052 #define DDCM_DATA6 (0xff << 16)
0053 #define DDCM_DATA5 (0xff << 8)
0054 #define DDCM_DATA4 (0xff << 0)
0055
0056 struct mtk_hdmi_ddc {
0057 struct i2c_adapter adap;
0058 struct clk *clk;
0059 void __iomem *regs;
0060 };
0061
0062 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
0063 unsigned int val)
0064 {
0065 writel(readl(ddc->regs + offset) | val, ddc->regs + offset);
0066 }
0067
0068 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
0069 unsigned int val)
0070 {
0071 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);
0072 }
0073
0074 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,
0075 unsigned int val)
0076 {
0077 return (readl(ddc->regs + offset) & val) == val;
0078 }
0079
0080 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,
0081 unsigned int mask, unsigned int shift,
0082 unsigned int val)
0083 {
0084 unsigned int tmp;
0085
0086 tmp = readl(ddc->regs + offset);
0087 tmp &= ~mask;
0088 tmp |= (val << shift) & mask;
0089 writel(tmp, ddc->regs + offset);
0090 }
0091
0092 static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,
0093 unsigned int offset, unsigned int mask,
0094 unsigned int shift)
0095 {
0096 return (readl(ddc->regs + offset) & mask) >> shift;
0097 }
0098
0099 static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)
0100 {
0101 u32 val;
0102
0103 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
0104 DDCM_SIF_MODE_OFFSET, mode);
0105 sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);
0106 readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,
0107 (val & DDCM_TRI) != DDCM_TRI, 4, 20000);
0108 }
0109
0110 static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
0111 {
0112 struct device *dev = ddc->adap.dev.parent;
0113 u32 remain_count, ack_count, ack_final, read_count, temp_count;
0114 u32 index = 0;
0115 u32 ack;
0116 int i;
0117
0118 ddcm_trigger_mode(ddc, DDCM_START);
0119 sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
0120 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
0121 0x00);
0122 ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
0123 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
0124 dev_dbg(dev, "ack = 0x%x\n", ack);
0125 if (ack != 0x01) {
0126 dev_err(dev, "i2c ack err!\n");
0127 return -ENXIO;
0128 }
0129
0130 remain_count = msg->len;
0131 ack_count = (msg->len - 1) / 8;
0132 ack_final = 0;
0133
0134 while (remain_count > 0) {
0135 if (ack_count > 0) {
0136 read_count = 8;
0137 ack_final = 0;
0138 ack_count--;
0139 } else {
0140 read_count = remain_count;
0141 ack_final = 1;
0142 }
0143
0144 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
0145 DDCM_PGLEN_OFFSET, read_count - 1);
0146 ddcm_trigger_mode(ddc, (ack_final == 1) ?
0147 DDCM_READ_DATA_NO_ACK :
0148 DDCM_READ_DATA_ACK);
0149
0150 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,
0151 DDCM_ACK_OFFSET);
0152 temp_count = 0;
0153 while (((ack & (1 << temp_count)) != 0) && (temp_count < 8))
0154 temp_count++;
0155 if (((ack_final == 1) && (temp_count != (read_count - 1))) ||
0156 ((ack_final == 0) && (temp_count != read_count))) {
0157 dev_err(dev, "Address NACK! ACK(0x%x)\n", ack);
0158 break;
0159 }
0160
0161 for (i = read_count; i >= 1; i--) {
0162 int shift;
0163 int offset;
0164
0165 if (i > 4) {
0166 offset = DDC_DDCMD1;
0167 shift = (i - 5) * 8;
0168 } else {
0169 offset = DDC_DDCMD0;
0170 shift = (i - 1) * 8;
0171 }
0172
0173 msg->buf[index + i - 1] = sif_read_mask(ddc, offset,
0174 0xff << shift,
0175 shift);
0176 }
0177
0178 remain_count -= read_count;
0179 index += read_count;
0180 }
0181
0182 return 0;
0183 }
0184
0185 static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
0186 {
0187 struct device *dev = ddc->adap.dev.parent;
0188 u32 ack;
0189
0190 ddcm_trigger_mode(ddc, DDCM_START);
0191 sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
0192 sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);
0193 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
0194 0x1);
0195 ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
0196
0197 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
0198 dev_dbg(dev, "ack = %d\n", ack);
0199
0200 if (ack != 0x03) {
0201 dev_err(dev, "i2c ack err!\n");
0202 return -EIO;
0203 }
0204
0205 return 0;
0206 }
0207
0208 static int mtk_hdmi_ddc_xfer(struct i2c_adapter *adapter,
0209 struct i2c_msg *msgs, int num)
0210 {
0211 struct mtk_hdmi_ddc *ddc = adapter->algo_data;
0212 struct device *dev = adapter->dev.parent;
0213 int ret;
0214 int i;
0215
0216 if (!ddc) {
0217 dev_err(dev, "invalid arguments\n");
0218 return -EINVAL;
0219 }
0220
0221 sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);
0222 sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);
0223 sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);
0224
0225 if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {
0226 dev_err(dev, "ddc line is busy!\n");
0227 return -EBUSY;
0228 }
0229
0230 sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,
0231 DDCM_CLK_DIV_OFFSET, SIF1_CLOK);
0232
0233 for (i = 0; i < num; i++) {
0234 struct i2c_msg *msg = &msgs[i];
0235
0236 dev_dbg(dev, "i2c msg, adr:0x%x, flags:%d, len :0x%x\n",
0237 msg->addr, msg->flags, msg->len);
0238
0239 if (msg->flags & I2C_M_RD)
0240 ret = mtk_hdmi_ddc_read_msg(ddc, msg);
0241 else
0242 ret = mtk_hdmi_ddc_write_msg(ddc, msg);
0243 if (ret < 0)
0244 goto xfer_end;
0245 }
0246
0247 ddcm_trigger_mode(ddc, DDCM_STOP);
0248
0249 return i;
0250
0251 xfer_end:
0252 ddcm_trigger_mode(ddc, DDCM_STOP);
0253 dev_err(dev, "ddc failed!\n");
0254 return ret;
0255 }
0256
0257 static u32 mtk_hdmi_ddc_func(struct i2c_adapter *adapter)
0258 {
0259 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0260 }
0261
0262 static const struct i2c_algorithm mtk_hdmi_ddc_algorithm = {
0263 .master_xfer = mtk_hdmi_ddc_xfer,
0264 .functionality = mtk_hdmi_ddc_func,
0265 };
0266
0267 static int mtk_hdmi_ddc_probe(struct platform_device *pdev)
0268 {
0269 struct device *dev = &pdev->dev;
0270 struct mtk_hdmi_ddc *ddc;
0271 struct resource *mem;
0272 int ret;
0273
0274 ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);
0275 if (!ddc)
0276 return -ENOMEM;
0277
0278 ddc->clk = devm_clk_get(dev, "ddc-i2c");
0279 if (IS_ERR(ddc->clk)) {
0280 dev_err(dev, "get ddc_clk failed: %p ,\n", ddc->clk);
0281 return PTR_ERR(ddc->clk);
0282 }
0283
0284 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0285 ddc->regs = devm_ioremap_resource(&pdev->dev, mem);
0286 if (IS_ERR(ddc->regs))
0287 return PTR_ERR(ddc->regs);
0288
0289 ret = clk_prepare_enable(ddc->clk);
0290 if (ret) {
0291 dev_err(dev, "enable ddc clk failed!\n");
0292 return ret;
0293 }
0294
0295 strlcpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));
0296 ddc->adap.owner = THIS_MODULE;
0297 ddc->adap.class = I2C_CLASS_DDC;
0298 ddc->adap.algo = &mtk_hdmi_ddc_algorithm;
0299 ddc->adap.retries = 3;
0300 ddc->adap.dev.of_node = dev->of_node;
0301 ddc->adap.algo_data = ddc;
0302 ddc->adap.dev.parent = &pdev->dev;
0303
0304 ret = i2c_add_adapter(&ddc->adap);
0305 if (ret < 0) {
0306 dev_err(dev, "failed to add bus to i2c core\n");
0307 goto err_clk_disable;
0308 }
0309
0310 platform_set_drvdata(pdev, ddc);
0311
0312 dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);
0313 dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);
0314 dev_dbg(dev, "physical adr: %pa, end: %pa\n", &mem->start,
0315 &mem->end);
0316
0317 return 0;
0318
0319 err_clk_disable:
0320 clk_disable_unprepare(ddc->clk);
0321 return ret;
0322 }
0323
0324 static int mtk_hdmi_ddc_remove(struct platform_device *pdev)
0325 {
0326 struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);
0327
0328 i2c_del_adapter(&ddc->adap);
0329 clk_disable_unprepare(ddc->clk);
0330
0331 return 0;
0332 }
0333
0334 static const struct of_device_id mtk_hdmi_ddc_match[] = {
0335 { .compatible = "mediatek,mt8173-hdmi-ddc", },
0336 {},
0337 };
0338 MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_match);
0339
0340 struct platform_driver mtk_hdmi_ddc_driver = {
0341 .probe = mtk_hdmi_ddc_probe,
0342 .remove = mtk_hdmi_ddc_remove,
0343 .driver = {
0344 .name = "mediatek-hdmi-ddc",
0345 .of_match_table = mtk_hdmi_ddc_match,
0346 },
0347 };
0348
0349 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
0350 MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");
0351 MODULE_LICENSE("GPL v2");
