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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Jie Qiu <jie.qiu@mediatek.com>
0005  */
0006 
0007 #include <linux/arm-smccc.h>
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/hdmi.h>
0011 #include <linux/i2c.h>
0012 #include <linux/io.h>
0013 #include <linux/kernel.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/module.h>
0016 #include <linux/mutex.h>
0017 #include <linux/of_platform.h>
0018 #include <linux/of.h>
0019 #include <linux/of_gpio.h>
0020 #include <linux/of_graph.h>
0021 #include <linux/phy/phy.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/regmap.h>
0024 
0025 #include <sound/hdmi-codec.h>
0026 
0027 #include <drm/drm_atomic_helper.h>
0028 #include <drm/drm_bridge.h>
0029 #include <drm/drm_crtc.h>
0030 #include <drm/drm_edid.h>
0031 #include <drm/drm_print.h>
0032 #include <drm/drm_probe_helper.h>
0033 
0034 #include "mtk_cec.h"
0035 #include "mtk_hdmi.h"
0036 #include "mtk_hdmi_regs.h"
0037 
0038 #define NCTS_BYTES  7
0039 
0040 enum mtk_hdmi_clk_id {
0041     MTK_HDMI_CLK_HDMI_PIXEL,
0042     MTK_HDMI_CLK_HDMI_PLL,
0043     MTK_HDMI_CLK_AUD_BCLK,
0044     MTK_HDMI_CLK_AUD_SPDIF,
0045     MTK_HDMI_CLK_COUNT
0046 };
0047 
0048 enum hdmi_aud_input_type {
0049     HDMI_AUD_INPUT_I2S = 0,
0050     HDMI_AUD_INPUT_SPDIF,
0051 };
0052 
0053 enum hdmi_aud_i2s_fmt {
0054     HDMI_I2S_MODE_RJT_24BIT = 0,
0055     HDMI_I2S_MODE_RJT_16BIT,
0056     HDMI_I2S_MODE_LJT_24BIT,
0057     HDMI_I2S_MODE_LJT_16BIT,
0058     HDMI_I2S_MODE_I2S_24BIT,
0059     HDMI_I2S_MODE_I2S_16BIT
0060 };
0061 
0062 enum hdmi_aud_mclk {
0063     HDMI_AUD_MCLK_128FS,
0064     HDMI_AUD_MCLK_192FS,
0065     HDMI_AUD_MCLK_256FS,
0066     HDMI_AUD_MCLK_384FS,
0067     HDMI_AUD_MCLK_512FS,
0068     HDMI_AUD_MCLK_768FS,
0069     HDMI_AUD_MCLK_1152FS,
0070 };
0071 
0072 enum hdmi_aud_channel_type {
0073     HDMI_AUD_CHAN_TYPE_1_0 = 0,
0074     HDMI_AUD_CHAN_TYPE_1_1,
0075     HDMI_AUD_CHAN_TYPE_2_0,
0076     HDMI_AUD_CHAN_TYPE_2_1,
0077     HDMI_AUD_CHAN_TYPE_3_0,
0078     HDMI_AUD_CHAN_TYPE_3_1,
0079     HDMI_AUD_CHAN_TYPE_4_0,
0080     HDMI_AUD_CHAN_TYPE_4_1,
0081     HDMI_AUD_CHAN_TYPE_5_0,
0082     HDMI_AUD_CHAN_TYPE_5_1,
0083     HDMI_AUD_CHAN_TYPE_6_0,
0084     HDMI_AUD_CHAN_TYPE_6_1,
0085     HDMI_AUD_CHAN_TYPE_7_0,
0086     HDMI_AUD_CHAN_TYPE_7_1,
0087     HDMI_AUD_CHAN_TYPE_3_0_LRS,
0088     HDMI_AUD_CHAN_TYPE_3_1_LRS,
0089     HDMI_AUD_CHAN_TYPE_4_0_CLRS,
0090     HDMI_AUD_CHAN_TYPE_4_1_CLRS,
0091     HDMI_AUD_CHAN_TYPE_6_1_CS,
0092     HDMI_AUD_CHAN_TYPE_6_1_CH,
0093     HDMI_AUD_CHAN_TYPE_6_1_OH,
0094     HDMI_AUD_CHAN_TYPE_6_1_CHR,
0095     HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
0096     HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
0097     HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
0098     HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
0099     HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
0100     HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
0101     HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
0102     HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
0103     HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
0104     HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
0105     HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
0106     HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
0107     HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
0108     HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
0109     HDMI_AUD_CHAN_TYPE_6_0_CS,
0110     HDMI_AUD_CHAN_TYPE_6_0_CH,
0111     HDMI_AUD_CHAN_TYPE_6_0_OH,
0112     HDMI_AUD_CHAN_TYPE_6_0_CHR,
0113     HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
0114     HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
0115     HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
0116     HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
0117     HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
0118     HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
0119     HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
0120     HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
0121     HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
0122     HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
0123     HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
0124     HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
0125     HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
0126     HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
0127     HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
0128     HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
0129 };
0130 
0131 enum hdmi_aud_channel_swap_type {
0132     HDMI_AUD_SWAP_LR,
0133     HDMI_AUD_SWAP_LFE_CC,
0134     HDMI_AUD_SWAP_LSRS,
0135     HDMI_AUD_SWAP_RLS_RRS,
0136     HDMI_AUD_SWAP_LR_STATUS,
0137 };
0138 
0139 struct hdmi_audio_param {
0140     enum hdmi_audio_coding_type aud_codec;
0141     enum hdmi_audio_sample_size aud_sampe_size;
0142     enum hdmi_aud_input_type aud_input_type;
0143     enum hdmi_aud_i2s_fmt aud_i2s_fmt;
0144     enum hdmi_aud_mclk aud_mclk;
0145     enum hdmi_aud_channel_type aud_input_chan_type;
0146     struct hdmi_codec_params codec_params;
0147 };
0148 
0149 struct mtk_hdmi_conf {
0150     bool tz_disabled;
0151     bool cea_modes_only;
0152     unsigned long max_mode_clock;
0153 };
0154 
0155 struct mtk_hdmi {
0156     struct drm_bridge bridge;
0157     struct drm_bridge *next_bridge;
0158     struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
0159     struct device *dev;
0160     const struct mtk_hdmi_conf *conf;
0161     struct phy *phy;
0162     struct device *cec_dev;
0163     struct i2c_adapter *ddc_adpt;
0164     struct clk *clk[MTK_HDMI_CLK_COUNT];
0165     struct drm_display_mode mode;
0166     bool dvi_mode;
0167     u32 min_clock;
0168     u32 max_clock;
0169     u32 max_hdisplay;
0170     u32 max_vdisplay;
0171     u32 ibias;
0172     u32 ibias_up;
0173     struct regmap *sys_regmap;
0174     unsigned int sys_offset;
0175     void __iomem *regs;
0176     enum hdmi_colorspace csp;
0177     struct hdmi_audio_param aud_param;
0178     bool audio_enable;
0179     bool powered;
0180     bool enabled;
0181     hdmi_codec_plugged_cb plugged_cb;
0182     struct device *codec_dev;
0183     struct mutex update_plugged_status_lock;
0184 };
0185 
0186 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
0187 {
0188     return container_of(b, struct mtk_hdmi, bridge);
0189 }
0190 
0191 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
0192 {
0193     return readl(hdmi->regs + offset);
0194 }
0195 
0196 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
0197 {
0198     writel(val, hdmi->regs + offset);
0199 }
0200 
0201 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
0202 {
0203     void __iomem *reg = hdmi->regs + offset;
0204     u32 tmp;
0205 
0206     tmp = readl(reg);
0207     tmp &= ~bits;
0208     writel(tmp, reg);
0209 }
0210 
0211 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
0212 {
0213     void __iomem *reg = hdmi->regs + offset;
0214     u32 tmp;
0215 
0216     tmp = readl(reg);
0217     tmp |= bits;
0218     writel(tmp, reg);
0219 }
0220 
0221 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
0222 {
0223     void __iomem *reg = hdmi->regs + offset;
0224     u32 tmp;
0225 
0226     tmp = readl(reg);
0227     tmp = (tmp & ~mask) | (val & mask);
0228     writel(tmp, reg);
0229 }
0230 
0231 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
0232 {
0233     mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
0234               VIDEO_SOURCE_SEL);
0235 }
0236 
0237 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
0238 {
0239     struct arm_smccc_res res;
0240 
0241     /*
0242      * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
0243      * output. This bit can only be controlled in ARM supervisor mode.
0244      * The ARM trusted firmware provides an API for the HDMI driver to set
0245      * this control bit to enable HDMI output in supervisor mode.
0246      */
0247     if (hdmi->conf && hdmi->conf->tz_disabled)
0248         regmap_update_bits(hdmi->sys_regmap,
0249                    hdmi->sys_offset + HDMI_SYS_CFG20,
0250                    0x80008005, enable ? 0x80000005 : 0x8000);
0251     else
0252         arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
0253                   0x80000000, 0, 0, 0, 0, 0, &res);
0254 
0255     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
0256                HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
0257     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
0258                HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
0259 }
0260 
0261 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
0262 {
0263     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
0264                HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
0265 }
0266 
0267 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
0268 {
0269     mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
0270 }
0271 
0272 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
0273 {
0274     mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
0275 }
0276 
0277 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
0278 {
0279     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
0280                HDMI_RST, HDMI_RST);
0281     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
0282                HDMI_RST, 0);
0283     mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
0284     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
0285                ANLG_ON, ANLG_ON);
0286 }
0287 
0288 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
0289 {
0290     mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
0291               CFG2_NOTICE_EN);
0292 }
0293 
0294 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
0295 {
0296     mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
0297 }
0298 
0299 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
0300 {
0301     mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
0302 }
0303 
0304 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
0305                     u8 len)
0306 {
0307     u32 ctrl_reg = GRL_CTRL;
0308     int i;
0309     u8 *frame_data;
0310     enum hdmi_infoframe_type frame_type;
0311     u8 frame_ver;
0312     u8 frame_len;
0313     u8 checksum;
0314     int ctrl_frame_en = 0;
0315 
0316     frame_type = *buffer++;
0317     frame_ver = *buffer++;
0318     frame_len = *buffer++;
0319     checksum = *buffer++;
0320     frame_data = buffer;
0321 
0322     dev_dbg(hdmi->dev,
0323         "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
0324         frame_type, frame_ver, frame_len, checksum);
0325 
0326     switch (frame_type) {
0327     case HDMI_INFOFRAME_TYPE_AVI:
0328         ctrl_frame_en = CTRL_AVI_EN;
0329         ctrl_reg = GRL_CTRL;
0330         break;
0331     case HDMI_INFOFRAME_TYPE_SPD:
0332         ctrl_frame_en = CTRL_SPD_EN;
0333         ctrl_reg = GRL_CTRL;
0334         break;
0335     case HDMI_INFOFRAME_TYPE_AUDIO:
0336         ctrl_frame_en = CTRL_AUDIO_EN;
0337         ctrl_reg = GRL_CTRL;
0338         break;
0339     case HDMI_INFOFRAME_TYPE_VENDOR:
0340         ctrl_frame_en = VS_EN;
0341         ctrl_reg = GRL_ACP_ISRC_CTRL;
0342         break;
0343     default:
0344         dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
0345         return;
0346     }
0347     mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
0348     mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
0349     mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
0350     mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
0351 
0352     mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
0353     for (i = 0; i < frame_len; i++)
0354         mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
0355 
0356     mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
0357 }
0358 
0359 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
0360 {
0361     mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
0362               AUDIO_PACKET_OFF);
0363 }
0364 
0365 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
0366 {
0367     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
0368                HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
0369     usleep_range(2000, 4000);
0370     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
0371                HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
0372 }
0373 
0374 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
0375 {
0376     regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
0377                DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
0378                COLOR_8BIT_MODE);
0379 }
0380 
0381 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
0382 {
0383     mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
0384     usleep_range(2000, 4000);
0385     mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
0386 }
0387 
0388 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
0389 {
0390     mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
0391               CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
0392     usleep_range(2000, 4000);
0393     mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
0394               CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
0395 }
0396 
0397 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
0398 {
0399     mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
0400               CTS_CTRL_SOFT);
0401 }
0402 
0403 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
0404                            bool enable)
0405 {
0406     mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
0407               NCTS_WRI_ANYTIME);
0408 }
0409 
0410 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
0411                      struct drm_display_mode *mode)
0412 {
0413     mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
0414 
0415     if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
0416         mode->clock == 74250 &&
0417         mode->vdisplay == 1080)
0418         mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
0419     else
0420         mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
0421 }
0422 
0423 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
0424                     enum hdmi_aud_channel_swap_type swap)
0425 {
0426     u8 swap_bit;
0427 
0428     switch (swap) {
0429     case HDMI_AUD_SWAP_LR:
0430         swap_bit = LR_SWAP;
0431         break;
0432     case HDMI_AUD_SWAP_LFE_CC:
0433         swap_bit = LFE_CC_SWAP;
0434         break;
0435     case HDMI_AUD_SWAP_LSRS:
0436         swap_bit = LSRS_SWAP;
0437         break;
0438     case HDMI_AUD_SWAP_RLS_RRS:
0439         swap_bit = RLS_RRS_SWAP;
0440         break;
0441     case HDMI_AUD_SWAP_LR_STATUS:
0442         swap_bit = LR_STATUS_SWAP;
0443         break;
0444     default:
0445         swap_bit = LFE_CC_SWAP;
0446         break;
0447     }
0448     mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
0449 }
0450 
0451 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
0452                     enum hdmi_audio_sample_size bit_num)
0453 {
0454     u32 val;
0455 
0456     switch (bit_num) {
0457     case HDMI_AUDIO_SAMPLE_SIZE_16:
0458         val = AOUT_16BIT;
0459         break;
0460     case HDMI_AUDIO_SAMPLE_SIZE_20:
0461         val = AOUT_20BIT;
0462         break;
0463     case HDMI_AUDIO_SAMPLE_SIZE_24:
0464     case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
0465         val = AOUT_24BIT;
0466         break;
0467     }
0468 
0469     mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
0470 }
0471 
0472 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
0473                     enum hdmi_aud_i2s_fmt i2s_fmt)
0474 {
0475     u32 val;
0476 
0477     val = mtk_hdmi_read(hdmi, GRL_CFG0);
0478     val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
0479 
0480     switch (i2s_fmt) {
0481     case HDMI_I2S_MODE_RJT_24BIT:
0482         val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
0483         break;
0484     case HDMI_I2S_MODE_RJT_16BIT:
0485         val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
0486         break;
0487     case HDMI_I2S_MODE_LJT_24BIT:
0488     default:
0489         val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
0490         break;
0491     case HDMI_I2S_MODE_LJT_16BIT:
0492         val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
0493         break;
0494     case HDMI_I2S_MODE_I2S_24BIT:
0495         val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
0496         break;
0497     case HDMI_I2S_MODE_I2S_16BIT:
0498         val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
0499         break;
0500     }
0501     mtk_hdmi_write(hdmi, GRL_CFG0, val);
0502 }
0503 
0504 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
0505 {
0506     const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
0507     u8 val;
0508 
0509     /* Disable high bitrate, set DST packet normal/double */
0510     mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
0511 
0512     if (dst)
0513         val = DST_NORMAL_DOUBLE | SACD_DST;
0514     else
0515         val = 0;
0516 
0517     mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
0518 }
0519 
0520 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
0521                     enum hdmi_aud_channel_type channel_type,
0522                     u8 channel_count)
0523 {
0524     unsigned int ch_switch;
0525     u8 i2s_uv;
0526 
0527     ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
0528             CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
0529             CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
0530             CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
0531 
0532     if (channel_count == 2) {
0533         i2s_uv = I2S_UV_CH_EN(0);
0534     } else if (channel_count == 3 || channel_count == 4) {
0535         if (channel_count == 4 &&
0536             (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
0537             channel_type == HDMI_AUD_CHAN_TYPE_4_0))
0538             i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
0539         else
0540             i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
0541     } else if (channel_count == 6 || channel_count == 5) {
0542         if (channel_count == 6 &&
0543             channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
0544             channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
0545             i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
0546                  I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
0547         } else {
0548             i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
0549                  I2S_UV_CH_EN(0);
0550         }
0551     } else if (channel_count == 8 || channel_count == 7) {
0552         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
0553              I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
0554     } else {
0555         i2s_uv = I2S_UV_CH_EN(0);
0556     }
0557 
0558     mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
0559     mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
0560     mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
0561     mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
0562 }
0563 
0564 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
0565                        enum hdmi_aud_input_type input_type)
0566 {
0567     u32 val;
0568 
0569     val = mtk_hdmi_read(hdmi, GRL_CFG1);
0570     if (input_type == HDMI_AUD_INPUT_I2S &&
0571         (val & CFG1_SPDIF) == CFG1_SPDIF) {
0572         val &= ~CFG1_SPDIF;
0573     } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
0574         (val & CFG1_SPDIF) == 0) {
0575         val |= CFG1_SPDIF;
0576     }
0577     mtk_hdmi_write(hdmi, GRL_CFG1, val);
0578 }
0579 
0580 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
0581                            u8 *channel_status)
0582 {
0583     int i;
0584 
0585     for (i = 0; i < 5; i++) {
0586         mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
0587         mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
0588         mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
0589     }
0590     for (; i < 24; i++) {
0591         mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
0592         mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
0593     }
0594 }
0595 
0596 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
0597 {
0598     u32 val;
0599 
0600     val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
0601     if (val & MIX_CTRL_SRC_EN) {
0602         val &= ~MIX_CTRL_SRC_EN;
0603         mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
0604         usleep_range(255, 512);
0605         val |= MIX_CTRL_SRC_EN;
0606         mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
0607     }
0608 }
0609 
0610 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
0611 {
0612     u32 val;
0613 
0614     val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
0615     val &= ~MIX_CTRL_SRC_EN;
0616     mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
0617     mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
0618 }
0619 
0620 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
0621                      enum hdmi_aud_mclk mclk)
0622 {
0623     u32 val;
0624 
0625     val = mtk_hdmi_read(hdmi, GRL_CFG5);
0626     val &= CFG5_CD_RATIO_MASK;
0627 
0628     switch (mclk) {
0629     case HDMI_AUD_MCLK_128FS:
0630         val |= CFG5_FS128;
0631         break;
0632     case HDMI_AUD_MCLK_256FS:
0633         val |= CFG5_FS256;
0634         break;
0635     case HDMI_AUD_MCLK_384FS:
0636         val |= CFG5_FS384;
0637         break;
0638     case HDMI_AUD_MCLK_512FS:
0639         val |= CFG5_FS512;
0640         break;
0641     case HDMI_AUD_MCLK_768FS:
0642         val |= CFG5_FS768;
0643         break;
0644     default:
0645         val |= CFG5_FS256;
0646         break;
0647     }
0648     mtk_hdmi_write(hdmi, GRL_CFG5, val);
0649 }
0650 
0651 struct hdmi_acr_n {
0652     unsigned int clock;
0653     unsigned int n[3];
0654 };
0655 
0656 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
0657 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
0658     /* Clock, N: 32kHz 44.1kHz 48kHz */
0659     {  25175, {  4576,  7007,  6864 } },
0660     {  74176, { 11648, 17836, 11648 } },
0661     { 148352, { 11648,  8918,  5824 } },
0662     { 296703, {  5824,  4459,  5824 } },
0663     { 297000, {  3072,  4704,  5120 } },
0664     {      0, {  4096,  6272,  6144 } }, /* all other TMDS clocks */
0665 };
0666 
0667 /**
0668  * hdmi_recommended_n() - Return N value recommended by HDMI specification
0669  * @freq: audio sample rate in Hz
0670  * @clock: rounded TMDS clock in kHz
0671  */
0672 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
0673 {
0674     const struct hdmi_acr_n *recommended;
0675     unsigned int i;
0676 
0677     for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
0678         if (clock == hdmi_rec_n_table[i].clock)
0679             break;
0680     }
0681     recommended = hdmi_rec_n_table + i;
0682 
0683     switch (freq) {
0684     case 32000:
0685         return recommended->n[0];
0686     case 44100:
0687         return recommended->n[1];
0688     case 48000:
0689         return recommended->n[2];
0690     case 88200:
0691         return recommended->n[1] * 2;
0692     case 96000:
0693         return recommended->n[2] * 2;
0694     case 176400:
0695         return recommended->n[1] * 4;
0696     case 192000:
0697         return recommended->n[2] * 4;
0698     default:
0699         return (128 * freq) / 1000;
0700     }
0701 }
0702 
0703 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
0704 {
0705     switch (clock) {
0706     case 25175:
0707         return 25174825;    /* 25.2/1.001 MHz */
0708     case 74176:
0709         return 74175824;    /* 74.25/1.001 MHz */
0710     case 148352:
0711         return 148351648;   /* 148.5/1.001 MHz */
0712     case 296703:
0713         return 296703297;   /* 297/1.001 MHz */
0714     default:
0715         return clock * 1000;
0716     }
0717 }
0718 
0719 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
0720                       unsigned int tmds_clock, unsigned int n)
0721 {
0722     return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
0723                      128 * audio_sample_rate);
0724 }
0725 
0726 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
0727                     unsigned int cts)
0728 {
0729     unsigned char val[NCTS_BYTES];
0730     int i;
0731 
0732     mtk_hdmi_write(hdmi, GRL_NCTS, 0);
0733     mtk_hdmi_write(hdmi, GRL_NCTS, 0);
0734     mtk_hdmi_write(hdmi, GRL_NCTS, 0);
0735     memset(val, 0, sizeof(val));
0736 
0737     val[0] = (cts >> 24) & 0xff;
0738     val[1] = (cts >> 16) & 0xff;
0739     val[2] = (cts >> 8) & 0xff;
0740     val[3] = cts & 0xff;
0741 
0742     val[4] = (n >> 16) & 0xff;
0743     val[5] = (n >> 8) & 0xff;
0744     val[6] = n & 0xff;
0745 
0746     for (i = 0; i < NCTS_BYTES; i++)
0747         mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
0748 }
0749 
0750 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
0751                      unsigned int sample_rate,
0752                      unsigned int clock)
0753 {
0754     unsigned int n, cts;
0755 
0756     n = hdmi_recommended_n(sample_rate, clock);
0757     cts = hdmi_expected_cts(sample_rate, clock, n);
0758 
0759     dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
0760         __func__, sample_rate, clock, n, cts);
0761 
0762     mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
0763               AUDIO_I2S_NCTS_SEL);
0764     do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
0765 }
0766 
0767 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
0768 {
0769     switch (channel_type) {
0770     case HDMI_AUD_CHAN_TYPE_1_0:
0771     case HDMI_AUD_CHAN_TYPE_1_1:
0772     case HDMI_AUD_CHAN_TYPE_2_0:
0773         return 2;
0774     case HDMI_AUD_CHAN_TYPE_2_1:
0775     case HDMI_AUD_CHAN_TYPE_3_0:
0776         return 3;
0777     case HDMI_AUD_CHAN_TYPE_3_1:
0778     case HDMI_AUD_CHAN_TYPE_4_0:
0779     case HDMI_AUD_CHAN_TYPE_3_0_LRS:
0780         return 4;
0781     case HDMI_AUD_CHAN_TYPE_4_1:
0782     case HDMI_AUD_CHAN_TYPE_5_0:
0783     case HDMI_AUD_CHAN_TYPE_3_1_LRS:
0784     case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
0785         return 5;
0786     case HDMI_AUD_CHAN_TYPE_5_1:
0787     case HDMI_AUD_CHAN_TYPE_6_0:
0788     case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
0789     case HDMI_AUD_CHAN_TYPE_6_0_CS:
0790     case HDMI_AUD_CHAN_TYPE_6_0_CH:
0791     case HDMI_AUD_CHAN_TYPE_6_0_OH:
0792     case HDMI_AUD_CHAN_TYPE_6_0_CHR:
0793         return 6;
0794     case HDMI_AUD_CHAN_TYPE_6_1:
0795     case HDMI_AUD_CHAN_TYPE_6_1_CS:
0796     case HDMI_AUD_CHAN_TYPE_6_1_CH:
0797     case HDMI_AUD_CHAN_TYPE_6_1_OH:
0798     case HDMI_AUD_CHAN_TYPE_6_1_CHR:
0799     case HDMI_AUD_CHAN_TYPE_7_0:
0800     case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
0801     case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
0802     case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
0803     case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
0804     case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
0805     case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
0806     case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
0807     case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
0808     case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
0809     case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
0810     case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
0811     case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
0812     case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
0813     case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
0814     case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
0815         return 7;
0816     case HDMI_AUD_CHAN_TYPE_7_1:
0817     case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
0818     case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
0819     case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
0820     case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
0821     case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
0822     case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
0823     case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
0824     case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
0825     case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
0826     case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
0827     case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
0828     case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
0829     case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
0830     case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
0831         return 8;
0832     default:
0833         return 2;
0834     }
0835 }
0836 
0837 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
0838 {
0839     unsigned long rate;
0840     int ret;
0841 
0842     /* The DPI driver already should have set TVDPLL to the correct rate */
0843     ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
0844     if (ret) {
0845         dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
0846             ret);
0847         return ret;
0848     }
0849 
0850     rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
0851 
0852     if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
0853         dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
0854              rate);
0855     else
0856         dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
0857 
0858     mtk_hdmi_hw_config_sys(hdmi);
0859     mtk_hdmi_hw_set_deep_color_mode(hdmi);
0860     return 0;
0861 }
0862 
0863 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
0864                         struct drm_display_mode *mode)
0865 {
0866     mtk_hdmi_hw_reset(hdmi);
0867     mtk_hdmi_hw_enable_notice(hdmi, true);
0868     mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
0869     mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
0870     mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
0871 
0872     mtk_hdmi_hw_msic_setting(hdmi, mode);
0873 }
0874 
0875 
0876 static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
0877 {
0878     enum hdmi_aud_channel_type chan_type;
0879     u8 chan_count;
0880     bool dst;
0881 
0882     mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
0883     mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
0884 
0885     if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
0886         hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
0887         mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
0888     } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
0889         hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
0890     }
0891 
0892     mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
0893     mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
0894 
0895     dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
0896            (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
0897     mtk_hdmi_hw_audio_config(hdmi, dst);
0898 
0899     if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
0900         chan_type = HDMI_AUD_CHAN_TYPE_2_0;
0901     else
0902         chan_type = hdmi->aud_param.aud_input_chan_type;
0903     chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
0904     mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
0905     mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
0906 }
0907 
0908 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
0909                 struct drm_display_mode *display_mode)
0910 {
0911     unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
0912 
0913     mtk_hdmi_hw_ncts_enable(hdmi, false);
0914     mtk_hdmi_hw_aud_src_disable(hdmi);
0915     mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
0916 
0917     if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
0918         switch (sample_rate) {
0919         case 32000:
0920         case 44100:
0921         case 48000:
0922         case 88200:
0923         case 96000:
0924             break;
0925         default:
0926             return -EINVAL;
0927         }
0928         mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
0929     } else {
0930         switch (sample_rate) {
0931         case 32000:
0932         case 44100:
0933         case 48000:
0934             break;
0935         default:
0936             return -EINVAL;
0937         }
0938         mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
0939     }
0940 
0941     mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
0942 
0943     mtk_hdmi_hw_aud_src_reenable(hdmi);
0944     return 0;
0945 }
0946 
0947 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
0948                       struct drm_display_mode *display_mode)
0949 {
0950     mtk_hdmi_hw_aud_mute(hdmi);
0951     mtk_hdmi_hw_send_aud_packet(hdmi, false);
0952 
0953     mtk_hdmi_aud_set_input(hdmi);
0954     mtk_hdmi_aud_set_src(hdmi, display_mode);
0955     mtk_hdmi_hw_aud_set_channel_status(hdmi,
0956             hdmi->aud_param.codec_params.iec.status);
0957 
0958     usleep_range(50, 100);
0959 
0960     mtk_hdmi_hw_ncts_enable(hdmi, true);
0961     mtk_hdmi_hw_send_aud_packet(hdmi, true);
0962     mtk_hdmi_hw_aud_unmute(hdmi);
0963     return 0;
0964 }
0965 
0966 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
0967                     struct drm_display_mode *mode)
0968 {
0969     struct hdmi_avi_infoframe frame;
0970     u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
0971     ssize_t err;
0972 
0973     err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
0974                                hdmi->curr_conn, mode);
0975     if (err < 0) {
0976         dev_err(hdmi->dev,
0977             "Failed to get AVI infoframe from mode: %zd\n", err);
0978         return err;
0979     }
0980 
0981     err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
0982     if (err < 0) {
0983         dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
0984         return err;
0985     }
0986 
0987     mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
0988     return 0;
0989 }
0990 
0991 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
0992                     const char *vendor,
0993                     const char *product)
0994 {
0995     struct hdmi_spd_infoframe frame;
0996     u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
0997     ssize_t err;
0998 
0999     err = hdmi_spd_infoframe_init(&frame, vendor, product);
1000     if (err < 0) {
1001         dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1002             err);
1003         return err;
1004     }
1005 
1006     err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1007     if (err < 0) {
1008         dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1009         return err;
1010     }
1011 
1012     mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1013     return 0;
1014 }
1015 
1016 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1017 {
1018     struct hdmi_audio_infoframe frame;
1019     u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
1020     ssize_t err;
1021 
1022     err = hdmi_audio_infoframe_init(&frame);
1023     if (err < 0) {
1024         dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1025             err);
1026         return err;
1027     }
1028 
1029     frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1030     frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1031     frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1032     frame.channels = mtk_hdmi_aud_get_chnl_count(
1033                     hdmi->aud_param.aud_input_chan_type);
1034 
1035     err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1036     if (err < 0) {
1037         dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1038             err);
1039         return err;
1040     }
1041 
1042     mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1043     return 0;
1044 }
1045 
1046 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1047                         struct drm_display_mode *mode)
1048 {
1049     struct hdmi_vendor_infoframe frame;
1050     u8 buffer[10];
1051     ssize_t err;
1052 
1053     err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1054                               hdmi->curr_conn, mode);
1055     if (err) {
1056         dev_err(hdmi->dev,
1057             "Failed to get vendor infoframe from mode: %zd\n", err);
1058         return err;
1059     }
1060 
1061     err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1062     if (err < 0) {
1063         dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1064             err);
1065         return err;
1066     }
1067 
1068     mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1069     return 0;
1070 }
1071 
1072 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1073 {
1074     struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1075 
1076     hdmi->csp = HDMI_COLORSPACE_RGB;
1077     aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1078     aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1079     aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1080     aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1081     aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1082     aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1083 
1084     return 0;
1085 }
1086 
1087 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1088 {
1089     mtk_hdmi_hw_send_aud_packet(hdmi, true);
1090     hdmi->audio_enable = true;
1091 }
1092 
1093 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1094 {
1095     mtk_hdmi_hw_send_aud_packet(hdmi, false);
1096     hdmi->audio_enable = false;
1097 }
1098 
1099 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1100                     struct hdmi_audio_param *param)
1101 {
1102     if (!hdmi->audio_enable) {
1103         dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1104         return -EINVAL;
1105     }
1106     dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1107         param->aud_codec, param->aud_input_type,
1108         param->aud_input_chan_type, param->codec_params.sample_rate);
1109     memcpy(&hdmi->aud_param, param, sizeof(*param));
1110     return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1111 }
1112 
1113 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1114                         struct drm_display_mode *mode)
1115 {
1116     int ret;
1117 
1118     mtk_hdmi_hw_vid_black(hdmi, true);
1119     mtk_hdmi_hw_aud_mute(hdmi);
1120     mtk_hdmi_hw_send_av_mute(hdmi);
1121     phy_power_off(hdmi->phy);
1122 
1123     ret = mtk_hdmi_video_change_vpll(hdmi,
1124                      mode->clock * 1000);
1125     if (ret) {
1126         dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1127         return ret;
1128     }
1129     mtk_hdmi_video_set_display_mode(hdmi, mode);
1130 
1131     phy_power_on(hdmi->phy);
1132     mtk_hdmi_aud_output_config(hdmi, mode);
1133 
1134     mtk_hdmi_hw_vid_black(hdmi, false);
1135     mtk_hdmi_hw_aud_unmute(hdmi);
1136     mtk_hdmi_hw_send_av_unmute(hdmi);
1137 
1138     return 0;
1139 }
1140 
1141 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1142     [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1143     [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1144     [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1145     [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1146 };
1147 
1148 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1149                 struct device_node *np)
1150 {
1151     int i;
1152 
1153     for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1154         hdmi->clk[i] = of_clk_get_by_name(np,
1155                           mtk_hdmi_clk_names[i]);
1156         if (IS_ERR(hdmi->clk[i]))
1157             return PTR_ERR(hdmi->clk[i]);
1158     }
1159     return 0;
1160 }
1161 
1162 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1163 {
1164     int ret;
1165 
1166     ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1167     if (ret)
1168         return ret;
1169 
1170     ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1171     if (ret)
1172         goto err;
1173 
1174     return 0;
1175 err:
1176     clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1177     return ret;
1178 }
1179 
1180 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1181 {
1182     clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1183     clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1184 }
1185 
1186 static enum drm_connector_status
1187 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
1188 {
1189     bool connected;
1190 
1191     mutex_lock(&hdmi->update_plugged_status_lock);
1192     connected = mtk_cec_hpd_high(hdmi->cec_dev);
1193     if (hdmi->plugged_cb && hdmi->codec_dev)
1194         hdmi->plugged_cb(hdmi->codec_dev, connected);
1195     mutex_unlock(&hdmi->update_plugged_status_lock);
1196 
1197     return connected ?
1198            connector_status_connected : connector_status_disconnected;
1199 }
1200 
1201 static enum drm_connector_status mtk_hdmi_detect(struct mtk_hdmi *hdmi)
1202 {
1203     return mtk_hdmi_update_plugged_status(hdmi);
1204 }
1205 
1206 static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1207                       const struct drm_display_info *info,
1208                       const struct drm_display_mode *mode)
1209 {
1210     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1211     struct drm_bridge *next_bridge;
1212 
1213     dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1214         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1215         !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1216 
1217     next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge);
1218     if (next_bridge) {
1219         struct drm_display_mode adjusted_mode;
1220 
1221         drm_mode_copy(&adjusted_mode, mode);
1222         if (!drm_bridge_chain_mode_fixup(next_bridge, mode,
1223                          &adjusted_mode))
1224             return MODE_BAD;
1225     }
1226 
1227     if (hdmi->conf) {
1228         if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
1229             return MODE_BAD;
1230 
1231         if (hdmi->conf->max_mode_clock &&
1232             mode->clock > hdmi->conf->max_mode_clock)
1233             return MODE_CLOCK_HIGH;
1234     }
1235 
1236     if (mode->clock < 27000)
1237         return MODE_CLOCK_LOW;
1238     if (mode->clock > 297000)
1239         return MODE_CLOCK_HIGH;
1240 
1241     return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1242 }
1243 
1244 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1245 {
1246     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1247 
1248     if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) {
1249         static enum drm_connector_status status;
1250 
1251         status = mtk_hdmi_detect(hdmi);
1252         drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1253         drm_bridge_hpd_notify(&hdmi->bridge, status);
1254     }
1255 }
1256 
1257 /*
1258  * Bridge callbacks
1259  */
1260 
1261 static enum drm_connector_status mtk_hdmi_bridge_detect(struct drm_bridge *bridge)
1262 {
1263     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1264 
1265     return mtk_hdmi_detect(hdmi);
1266 }
1267 
1268 static struct edid *mtk_hdmi_bridge_get_edid(struct drm_bridge *bridge,
1269                          struct drm_connector *connector)
1270 {
1271     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1272     struct edid *edid;
1273 
1274     if (!hdmi->ddc_adpt)
1275         return NULL;
1276     edid = drm_get_edid(connector, hdmi->ddc_adpt);
1277     if (!edid)
1278         return NULL;
1279     hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1280     return edid;
1281 }
1282 
1283 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
1284                   enum drm_bridge_attach_flags flags)
1285 {
1286     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1287     int ret;
1288 
1289     if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
1290         DRM_ERROR("%s: The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n",
1291               __func__);
1292         return -EINVAL;
1293     }
1294 
1295     if (hdmi->next_bridge) {
1296         ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1297                     bridge, flags);
1298         if (ret)
1299             return ret;
1300     }
1301 
1302     mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1303 
1304     return 0;
1305 }
1306 
1307 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1308                        const struct drm_display_mode *mode,
1309                        struct drm_display_mode *adjusted_mode)
1310 {
1311     return true;
1312 }
1313 
1314 static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
1315                        struct drm_bridge_state *old_bridge_state)
1316 {
1317     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1318 
1319     if (!hdmi->enabled)
1320         return;
1321 
1322     phy_power_off(hdmi->phy);
1323     clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1324     clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1325 
1326     hdmi->curr_conn = NULL;
1327 
1328     hdmi->enabled = false;
1329 }
1330 
1331 static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
1332                         struct drm_bridge_state *old_state)
1333 {
1334     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1335 
1336     if (!hdmi->powered)
1337         return;
1338 
1339     mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1340     mtk_hdmi_hw_make_reg_writable(hdmi, false);
1341 
1342     hdmi->powered = false;
1343 }
1344 
1345 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1346                 const struct drm_display_mode *mode,
1347                 const struct drm_display_mode *adjusted_mode)
1348 {
1349     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1350 
1351     dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1352         adjusted_mode->name, adjusted_mode->hdisplay);
1353     dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1354         adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1355         adjusted_mode->htotal);
1356     dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1357         adjusted_mode->hskew, adjusted_mode->vdisplay);
1358     dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1359         adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1360         adjusted_mode->vtotal);
1361     dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1362         adjusted_mode->vscan, adjusted_mode->flags);
1363 
1364     drm_mode_copy(&hdmi->mode, adjusted_mode);
1365 }
1366 
1367 static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1368                           struct drm_bridge_state *old_state)
1369 {
1370     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1371 
1372     mtk_hdmi_hw_make_reg_writable(hdmi, true);
1373     mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1374 
1375     hdmi->powered = true;
1376 }
1377 
1378 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1379                     struct drm_display_mode *mode)
1380 {
1381     mtk_hdmi_setup_audio_infoframe(hdmi);
1382     mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1383     mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1384     if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1385         mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1386 }
1387 
1388 static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
1389                       struct drm_bridge_state *old_state)
1390 {
1391     struct drm_atomic_state *state = old_state->base.state;
1392     struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1393 
1394     /* Retrieve the connector through the atomic state. */
1395     hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,
1396                                    bridge->encoder);
1397 
1398     mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1399     clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1400     clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1401     phy_power_on(hdmi->phy);
1402     mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1403 
1404     hdmi->enabled = true;
1405 }
1406 
1407 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1408     .mode_valid = mtk_hdmi_bridge_mode_valid,
1409     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1410     .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1411     .atomic_reset = drm_atomic_helper_bridge_reset,
1412     .attach = mtk_hdmi_bridge_attach,
1413     .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1414     .atomic_disable = mtk_hdmi_bridge_atomic_disable,
1415     .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable,
1416     .mode_set = mtk_hdmi_bridge_mode_set,
1417     .atomic_pre_enable = mtk_hdmi_bridge_atomic_pre_enable,
1418     .atomic_enable = mtk_hdmi_bridge_atomic_enable,
1419     .detect = mtk_hdmi_bridge_detect,
1420     .get_edid = mtk_hdmi_bridge_get_edid,
1421 };
1422 
1423 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1424                    struct platform_device *pdev)
1425 {
1426     struct device *dev = &pdev->dev;
1427     struct device_node *np = dev->of_node;
1428     struct device_node *cec_np, *remote, *i2c_np;
1429     struct platform_device *cec_pdev;
1430     struct regmap *regmap;
1431     struct resource *mem;
1432     int ret;
1433 
1434     ret = mtk_hdmi_get_all_clk(hdmi, np);
1435     if (ret) {
1436         if (ret != -EPROBE_DEFER)
1437             dev_err(dev, "Failed to get clocks: %d\n", ret);
1438 
1439         return ret;
1440     }
1441 
1442     /* The CEC module handles HDMI hotplug detection */
1443     cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1444     if (!cec_np) {
1445         dev_err(dev, "Failed to find CEC node\n");
1446         return -EINVAL;
1447     }
1448 
1449     cec_pdev = of_find_device_by_node(cec_np);
1450     if (!cec_pdev) {
1451         dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1452             cec_np);
1453         of_node_put(cec_np);
1454         return -EPROBE_DEFER;
1455     }
1456     of_node_put(cec_np);
1457     hdmi->cec_dev = &cec_pdev->dev;
1458 
1459     /*
1460      * The mediatek,syscon-hdmi property contains a phandle link to the
1461      * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1462      * registers it contains.
1463      */
1464     regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1465     ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1466                      &hdmi->sys_offset);
1467     if (IS_ERR(regmap))
1468         ret = PTR_ERR(regmap);
1469     if (ret) {
1470         dev_err(dev,
1471             "Failed to get system configuration registers: %d\n",
1472             ret);
1473         goto put_device;
1474     }
1475     hdmi->sys_regmap = regmap;
1476 
1477     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1478     hdmi->regs = devm_ioremap_resource(dev, mem);
1479     if (IS_ERR(hdmi->regs)) {
1480         ret = PTR_ERR(hdmi->regs);
1481         goto put_device;
1482     }
1483 
1484     remote = of_graph_get_remote_node(np, 1, 0);
1485     if (!remote) {
1486         ret = -EINVAL;
1487         goto put_device;
1488     }
1489 
1490     if (!of_device_is_compatible(remote, "hdmi-connector")) {
1491         hdmi->next_bridge = of_drm_find_bridge(remote);
1492         if (!hdmi->next_bridge) {
1493             dev_err(dev, "Waiting for external bridge\n");
1494             of_node_put(remote);
1495             ret = -EPROBE_DEFER;
1496             goto put_device;
1497         }
1498     }
1499 
1500     i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1501     if (!i2c_np) {
1502         dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1503             remote);
1504         of_node_put(remote);
1505         ret = -EINVAL;
1506         goto put_device;
1507     }
1508     of_node_put(remote);
1509 
1510     hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1511     of_node_put(i2c_np);
1512     if (!hdmi->ddc_adpt) {
1513         dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1514         ret = -EINVAL;
1515         goto put_device;
1516     }
1517 
1518     return 0;
1519 put_device:
1520     put_device(hdmi->cec_dev);
1521     return ret;
1522 }
1523 
1524 /*
1525  * HDMI audio codec callbacks
1526  */
1527 
1528 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1529                     struct hdmi_codec_daifmt *daifmt,
1530                     struct hdmi_codec_params *params)
1531 {
1532     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1533     struct hdmi_audio_param hdmi_params;
1534     unsigned int chan = params->cea.channels;
1535 
1536     dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1537         params->sample_rate, params->sample_width, chan);
1538 
1539     if (!hdmi->bridge.encoder)
1540         return -ENODEV;
1541 
1542     switch (chan) {
1543     case 2:
1544         hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1545         break;
1546     case 4:
1547         hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1548         break;
1549     case 6:
1550         hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1551         break;
1552     case 8:
1553         hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1554         break;
1555     default:
1556         dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1557         return -EINVAL;
1558     }
1559 
1560     switch (params->sample_rate) {
1561     case 32000:
1562     case 44100:
1563     case 48000:
1564     case 88200:
1565     case 96000:
1566     case 176400:
1567     case 192000:
1568         break;
1569     default:
1570         dev_err(hdmi->dev, "rate[%d] not supported!\n",
1571             params->sample_rate);
1572         return -EINVAL;
1573     }
1574 
1575     switch (daifmt->fmt) {
1576     case HDMI_I2S:
1577         hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1578         hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1579         hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1580         hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1581         hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1582         break;
1583     case HDMI_SPDIF:
1584         hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1585         hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1586         hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1587         break;
1588     default:
1589         dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1590             daifmt->fmt);
1591         return -EINVAL;
1592     }
1593 
1594     memcpy(&hdmi_params.codec_params, params,
1595            sizeof(hdmi_params.codec_params));
1596 
1597     mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1598 
1599     return 0;
1600 }
1601 
1602 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1603 {
1604     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1605 
1606     mtk_hdmi_audio_enable(hdmi);
1607 
1608     return 0;
1609 }
1610 
1611 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1612 {
1613     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1614 
1615     mtk_hdmi_audio_disable(hdmi);
1616 }
1617 
1618 static int
1619 mtk_hdmi_audio_mute(struct device *dev, void *data,
1620             bool enable, int direction)
1621 {
1622     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1623 
1624     if (enable)
1625         mtk_hdmi_hw_aud_mute(hdmi);
1626     else
1627         mtk_hdmi_hw_aud_unmute(hdmi);
1628 
1629     return 0;
1630 }
1631 
1632 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1633 {
1634     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1635 
1636     if (hdmi->enabled)
1637         memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
1638     else
1639         memset(buf, 0, len);
1640     return 0;
1641 }
1642 
1643 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
1644                       hdmi_codec_plugged_cb fn,
1645                       struct device *codec_dev)
1646 {
1647     struct mtk_hdmi *hdmi = data;
1648 
1649     mutex_lock(&hdmi->update_plugged_status_lock);
1650     hdmi->plugged_cb = fn;
1651     hdmi->codec_dev = codec_dev;
1652     mutex_unlock(&hdmi->update_plugged_status_lock);
1653 
1654     mtk_hdmi_update_plugged_status(hdmi);
1655 
1656     return 0;
1657 }
1658 
1659 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1660     .hw_params = mtk_hdmi_audio_hw_params,
1661     .audio_startup = mtk_hdmi_audio_startup,
1662     .audio_shutdown = mtk_hdmi_audio_shutdown,
1663     .mute_stream = mtk_hdmi_audio_mute,
1664     .get_eld = mtk_hdmi_audio_get_eld,
1665     .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
1666     .no_capture_mute = 1,
1667 };
1668 
1669 static int mtk_hdmi_register_audio_driver(struct device *dev)
1670 {
1671     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1672     struct hdmi_codec_pdata codec_data = {
1673         .ops = &mtk_hdmi_audio_codec_ops,
1674         .max_i2s_channels = 2,
1675         .i2s = 1,
1676         .data = hdmi,
1677     };
1678     struct platform_device *pdev;
1679 
1680     pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1681                          PLATFORM_DEVID_AUTO, &codec_data,
1682                          sizeof(codec_data));
1683     if (IS_ERR(pdev))
1684         return PTR_ERR(pdev);
1685 
1686     DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1687     return 0;
1688 }
1689 
1690 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1691 {
1692     struct mtk_hdmi *hdmi;
1693     struct device *dev = &pdev->dev;
1694     int ret;
1695 
1696     hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1697     if (!hdmi)
1698         return -ENOMEM;
1699 
1700     hdmi->dev = dev;
1701     hdmi->conf = of_device_get_match_data(dev);
1702 
1703     ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1704     if (ret)
1705         return ret;
1706 
1707     hdmi->phy = devm_phy_get(dev, "hdmi");
1708     if (IS_ERR(hdmi->phy)) {
1709         ret = PTR_ERR(hdmi->phy);
1710         dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1711         return ret;
1712     }
1713 
1714     mutex_init(&hdmi->update_plugged_status_lock);
1715     platform_set_drvdata(pdev, hdmi);
1716 
1717     ret = mtk_hdmi_output_init(hdmi);
1718     if (ret) {
1719         dev_err(dev, "Failed to initialize hdmi output\n");
1720         return ret;
1721     }
1722 
1723     ret = mtk_hdmi_register_audio_driver(dev);
1724     if (ret) {
1725         dev_err(dev, "Failed to register audio driver: %d\n", ret);
1726         return ret;
1727     }
1728 
1729     hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1730     hdmi->bridge.of_node = pdev->dev.of_node;
1731     hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
1732              | DRM_BRIDGE_OP_HPD;
1733     hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1734     drm_bridge_add(&hdmi->bridge);
1735 
1736     ret = mtk_hdmi_clk_enable_audio(hdmi);
1737     if (ret) {
1738         dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1739         goto err_bridge_remove;
1740     }
1741 
1742     return 0;
1743 
1744 err_bridge_remove:
1745     drm_bridge_remove(&hdmi->bridge);
1746     return ret;
1747 }
1748 
1749 static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1750 {
1751     struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1752 
1753     drm_bridge_remove(&hdmi->bridge);
1754     mtk_hdmi_clk_disable_audio(hdmi);
1755     return 0;
1756 }
1757 
1758 #ifdef CONFIG_PM_SLEEP
1759 static int mtk_hdmi_suspend(struct device *dev)
1760 {
1761     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1762 
1763     mtk_hdmi_clk_disable_audio(hdmi);
1764 
1765     return 0;
1766 }
1767 
1768 static int mtk_hdmi_resume(struct device *dev)
1769 {
1770     struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1771     int ret = 0;
1772 
1773     ret = mtk_hdmi_clk_enable_audio(hdmi);
1774     if (ret) {
1775         dev_err(dev, "hdmi resume failed!\n");
1776         return ret;
1777     }
1778 
1779     return 0;
1780 }
1781 #endif
1782 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1783              mtk_hdmi_suspend, mtk_hdmi_resume);
1784 
1785 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
1786     .tz_disabled = true,
1787 };
1788 
1789 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
1790     .max_mode_clock = 148500,
1791     .cea_modes_only = true,
1792 };
1793 
1794 static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1795     { .compatible = "mediatek,mt2701-hdmi",
1796       .data = &mtk_hdmi_conf_mt2701,
1797     },
1798     { .compatible = "mediatek,mt8167-hdmi",
1799       .data = &mtk_hdmi_conf_mt8167,
1800     },
1801     { .compatible = "mediatek,mt8173-hdmi",
1802     },
1803     {}
1804 };
1805 MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids);
1806 
1807 static struct platform_driver mtk_hdmi_driver = {
1808     .probe = mtk_drm_hdmi_probe,
1809     .remove = mtk_drm_hdmi_remove,
1810     .driver = {
1811         .name = "mediatek-drm-hdmi",
1812         .of_match_table = mtk_drm_hdmi_of_ids,
1813         .pm = &mtk_hdmi_pm_ops,
1814     },
1815 };
1816 
1817 static struct platform_driver * const mtk_hdmi_drivers[] = {
1818     &mtk_hdmi_ddc_driver,
1819     &mtk_cec_driver,
1820     &mtk_hdmi_driver,
1821 };
1822 
1823 static int __init mtk_hdmitx_init(void)
1824 {
1825     return platform_register_drivers(mtk_hdmi_drivers,
1826                      ARRAY_SIZE(mtk_hdmi_drivers));
1827 }
1828 
1829 static void __exit mtk_hdmitx_exit(void)
1830 {
1831     platform_unregister_drivers(mtk_hdmi_drivers,
1832                     ARRAY_SIZE(mtk_hdmi_drivers));
1833 }
1834 
1835 module_init(mtk_hdmitx_init);
1836 module_exit(mtk_hdmitx_exit);
1837 
1838 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1839 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1840 MODULE_LICENSE("GPL v2");
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