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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015 MediaTek Inc.
0004  * Author: YT SHEN <yt.shen@mediatek.com>
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/component.h>
0010 #include <linux/iommu.h>
0011 #include <linux/module.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/dma-mapping.h>
0016 
0017 #include <drm/drm_atomic.h>
0018 #include <drm/drm_atomic_helper.h>
0019 #include <drm/drm_drv.h>
0020 #include <drm/drm_fb_helper.h>
0021 #include <drm/drm_fourcc.h>
0022 #include <drm/drm_gem.h>
0023 #include <drm/drm_gem_cma_helper.h>
0024 #include <drm/drm_gem_framebuffer_helper.h>
0025 #include <drm/drm_of.h>
0026 #include <drm/drm_probe_helper.h>
0027 #include <drm/drm_vblank.h>
0028 
0029 #include "mtk_drm_crtc.h"
0030 #include "mtk_drm_ddp_comp.h"
0031 #include "mtk_drm_drv.h"
0032 #include "mtk_drm_gem.h"
0033 
0034 #define DRIVER_NAME "mediatek"
0035 #define DRIVER_DESC "Mediatek SoC DRM"
0036 #define DRIVER_DATE "20150513"
0037 #define DRIVER_MAJOR 1
0038 #define DRIVER_MINOR 0
0039 
0040 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
0041     .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
0042 };
0043 
0044 static struct drm_framebuffer *
0045 mtk_drm_mode_fb_create(struct drm_device *dev,
0046                struct drm_file *file,
0047                const struct drm_mode_fb_cmd2 *cmd)
0048 {
0049     const struct drm_format_info *info = drm_get_format_info(dev, cmd);
0050 
0051     if (info->num_planes != 1)
0052         return ERR_PTR(-EINVAL);
0053 
0054     return drm_gem_fb_create(dev, file, cmd);
0055 }
0056 
0057 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
0058     .fb_create = mtk_drm_mode_fb_create,
0059     .atomic_check = drm_atomic_helper_check,
0060     .atomic_commit = drm_atomic_helper_commit,
0061 };
0062 
0063 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
0064     DDP_COMPONENT_OVL0,
0065     DDP_COMPONENT_RDMA0,
0066     DDP_COMPONENT_COLOR0,
0067     DDP_COMPONENT_BLS,
0068     DDP_COMPONENT_DSI0,
0069 };
0070 
0071 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
0072     DDP_COMPONENT_RDMA1,
0073     DDP_COMPONENT_DPI0,
0074 };
0075 
0076 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
0077     DDP_COMPONENT_OVL0,
0078     DDP_COMPONENT_RDMA0,
0079     DDP_COMPONENT_COLOR0,
0080     DDP_COMPONENT_BLS,
0081     DDP_COMPONENT_DPI0,
0082 };
0083 
0084 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
0085     DDP_COMPONENT_RDMA1,
0086     DDP_COMPONENT_DSI0,
0087 };
0088 
0089 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
0090     DDP_COMPONENT_OVL0,
0091     DDP_COMPONENT_COLOR0,
0092     DDP_COMPONENT_AAL0,
0093     DDP_COMPONENT_OD0,
0094     DDP_COMPONENT_RDMA0,
0095     DDP_COMPONENT_DPI0,
0096     DDP_COMPONENT_PWM0,
0097 };
0098 
0099 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
0100     DDP_COMPONENT_OVL1,
0101     DDP_COMPONENT_COLOR1,
0102     DDP_COMPONENT_AAL1,
0103     DDP_COMPONENT_OD1,
0104     DDP_COMPONENT_RDMA1,
0105     DDP_COMPONENT_DPI1,
0106     DDP_COMPONENT_PWM1,
0107 };
0108 
0109 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
0110     DDP_COMPONENT_RDMA2,
0111     DDP_COMPONENT_DSI3,
0112     DDP_COMPONENT_PWM2,
0113 };
0114 
0115 static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
0116     DDP_COMPONENT_OVL0,
0117     DDP_COMPONENT_COLOR0,
0118     DDP_COMPONENT_CCORR,
0119     DDP_COMPONENT_AAL0,
0120     DDP_COMPONENT_GAMMA,
0121     DDP_COMPONENT_DITHER0,
0122     DDP_COMPONENT_RDMA0,
0123     DDP_COMPONENT_DSI0,
0124 };
0125 
0126 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
0127     DDP_COMPONENT_OVL0,
0128     DDP_COMPONENT_COLOR0,
0129     DDP_COMPONENT_AAL0,
0130     DDP_COMPONENT_OD0,
0131     DDP_COMPONENT_RDMA0,
0132     DDP_COMPONENT_UFOE,
0133     DDP_COMPONENT_DSI0,
0134     DDP_COMPONENT_PWM0,
0135 };
0136 
0137 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
0138     DDP_COMPONENT_OVL1,
0139     DDP_COMPONENT_COLOR1,
0140     DDP_COMPONENT_GAMMA,
0141     DDP_COMPONENT_RDMA1,
0142     DDP_COMPONENT_DPI0,
0143 };
0144 
0145 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
0146     DDP_COMPONENT_OVL0,
0147     DDP_COMPONENT_OVL_2L0,
0148     DDP_COMPONENT_RDMA0,
0149     DDP_COMPONENT_COLOR0,
0150     DDP_COMPONENT_CCORR,
0151     DDP_COMPONENT_AAL0,
0152     DDP_COMPONENT_GAMMA,
0153     DDP_COMPONENT_DITHER0,
0154     DDP_COMPONENT_DSI0,
0155 };
0156 
0157 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
0158     DDP_COMPONENT_OVL_2L1,
0159     DDP_COMPONENT_RDMA1,
0160     DDP_COMPONENT_DPI0,
0161 };
0162 
0163 static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = {
0164     DDP_COMPONENT_OVL0,
0165     DDP_COMPONENT_RDMA0,
0166     DDP_COMPONENT_COLOR0,
0167     DDP_COMPONENT_CCORR,
0168     DDP_COMPONENT_AAL0,
0169     DDP_COMPONENT_GAMMA,
0170     DDP_COMPONENT_POSTMASK0,
0171     DDP_COMPONENT_DITHER0,
0172     DDP_COMPONENT_DSI0,
0173 };
0174 
0175 static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = {
0176     DDP_COMPONENT_OVL_2L0,
0177     DDP_COMPONENT_RDMA1,
0178     DDP_COMPONENT_DPI0,
0179 };
0180 
0181 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
0182     DDP_COMPONENT_OVL0,
0183     DDP_COMPONENT_OVL_2L0,
0184     DDP_COMPONENT_RDMA0,
0185     DDP_COMPONENT_COLOR0,
0186     DDP_COMPONENT_CCORR,
0187     DDP_COMPONENT_AAL0,
0188     DDP_COMPONENT_GAMMA,
0189     DDP_COMPONENT_POSTMASK0,
0190     DDP_COMPONENT_DITHER0,
0191     DDP_COMPONENT_DSI0,
0192 };
0193 
0194 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
0195     DDP_COMPONENT_OVL_2L2,
0196     DDP_COMPONENT_RDMA4,
0197     DDP_COMPONENT_DPI0,
0198 };
0199 
0200 static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
0201     DDP_COMPONENT_OVL0,
0202     DDP_COMPONENT_RDMA0,
0203     DDP_COMPONENT_COLOR0,
0204     DDP_COMPONENT_CCORR,
0205     DDP_COMPONENT_AAL0,
0206     DDP_COMPONENT_GAMMA,
0207     DDP_COMPONENT_DITHER0,
0208     DDP_COMPONENT_DSC0,
0209     DDP_COMPONENT_MERGE0,
0210     DDP_COMPONENT_DP_INTF0,
0211 };
0212 
0213 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
0214     .main_path = mt2701_mtk_ddp_main,
0215     .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
0216     .ext_path = mt2701_mtk_ddp_ext,
0217     .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
0218     .shadow_register = true,
0219 };
0220 
0221 static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
0222     .num_drv_data = 1,
0223     .drv_data = {
0224         &mt2701_mmsys_driver_data,
0225     },
0226 };
0227 
0228 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
0229     .main_path = mt7623_mtk_ddp_main,
0230     .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
0231     .ext_path = mt7623_mtk_ddp_ext,
0232     .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
0233     .shadow_register = true,
0234 };
0235 
0236 static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
0237     .num_drv_data = 1,
0238     .drv_data = {
0239         &mt7623_mmsys_driver_data,
0240     },
0241 };
0242 
0243 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
0244     .main_path = mt2712_mtk_ddp_main,
0245     .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
0246     .ext_path = mt2712_mtk_ddp_ext,
0247     .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
0248     .third_path = mt2712_mtk_ddp_third,
0249     .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
0250 };
0251 
0252 static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
0253     .num_drv_data = 1,
0254     .drv_data = {
0255         &mt2712_mmsys_driver_data,
0256     },
0257 };
0258 
0259 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
0260     .main_path = mt8167_mtk_ddp_main,
0261     .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
0262 };
0263 
0264 static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
0265     .num_drv_data = 1,
0266     .drv_data = {
0267         &mt8167_mmsys_driver_data,
0268     },
0269 };
0270 
0271 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
0272     .main_path = mt8173_mtk_ddp_main,
0273     .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
0274     .ext_path = mt8173_mtk_ddp_ext,
0275     .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
0276 };
0277 
0278 static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
0279     .num_drv_data = 1,
0280     .drv_data = {
0281         &mt8173_mmsys_driver_data,
0282     },
0283 };
0284 
0285 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
0286     .main_path = mt8183_mtk_ddp_main,
0287     .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
0288     .ext_path = mt8183_mtk_ddp_ext,
0289     .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
0290 };
0291 
0292 static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
0293     .num_drv_data = 1,
0294     .drv_data = {
0295         &mt8183_mmsys_driver_data,
0296     },
0297 };
0298 
0299 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
0300     .main_path = mt8186_mtk_ddp_main,
0301     .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
0302     .ext_path = mt8186_mtk_ddp_ext,
0303     .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
0304 };
0305 
0306 static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
0307     .num_drv_data = 1,
0308     .drv_data = {
0309         &mt8186_mmsys_driver_data,
0310     },
0311 };
0312 
0313 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
0314     .main_path = mt8192_mtk_ddp_main,
0315     .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
0316     .ext_path = mt8192_mtk_ddp_ext,
0317     .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
0318 };
0319 
0320 static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
0321     .num_drv_data = 1,
0322     .drv_data = {
0323         &mt8192_mmsys_driver_data,
0324     },
0325 };
0326 
0327 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
0328     .io_start = 0x1c01a000,
0329     .main_path = mt8195_mtk_ddp_main,
0330     .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
0331 };
0332 
0333 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
0334     .io_start = 0x1c100000,
0335 };
0336 
0337 static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
0338     .num_drv_data = 1,
0339     .drv_data = {
0340         &mt8195_vdosys0_driver_data,
0341         &mt8195_vdosys1_driver_data,
0342     },
0343 };
0344 
0345 static int mtk_drm_kms_init(struct drm_device *drm)
0346 {
0347     struct mtk_drm_private *private = drm->dev_private;
0348     struct platform_device *pdev;
0349     struct device_node *np;
0350     struct device *dma_dev;
0351     int ret;
0352 
0353     if (drm_firmware_drivers_only())
0354         return -ENODEV;
0355 
0356     if (!iommu_present(&platform_bus_type))
0357         return -EPROBE_DEFER;
0358 
0359     pdev = of_find_device_by_node(private->mutex_node);
0360     if (!pdev) {
0361         dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
0362             private->mutex_node);
0363         of_node_put(private->mutex_node);
0364         return -EPROBE_DEFER;
0365     }
0366     private->mutex_dev = &pdev->dev;
0367 
0368     ret = drmm_mode_config_init(drm);
0369     if (ret)
0370         goto put_mutex_dev;
0371 
0372     drm->mode_config.min_width = 64;
0373     drm->mode_config.min_height = 64;
0374 
0375     /*
0376      * set max width and height as default value(4096x4096).
0377      * this value would be used to check framebuffer size limitation
0378      * at drm_mode_addfb().
0379      */
0380     drm->mode_config.max_width = 4096;
0381     drm->mode_config.max_height = 4096;
0382     drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
0383     drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
0384 
0385     ret = component_bind_all(drm->dev, drm);
0386     if (ret)
0387         goto put_mutex_dev;
0388 
0389     /*
0390      * We currently support two fixed data streams, each optional,
0391      * and each statically assigned to a crtc:
0392      * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
0393      */
0394     ret = mtk_drm_crtc_create(drm, private->data->main_path,
0395                   private->data->main_len);
0396     if (ret < 0)
0397         goto err_component_unbind;
0398     /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
0399     ret = mtk_drm_crtc_create(drm, private->data->ext_path,
0400                   private->data->ext_len);
0401     if (ret < 0)
0402         goto err_component_unbind;
0403 
0404     ret = mtk_drm_crtc_create(drm, private->data->third_path,
0405                   private->data->third_len);
0406     if (ret < 0)
0407         goto err_component_unbind;
0408 
0409     /* Use OVL device for all DMA memory allocations */
0410     np = private->comp_node[private->data->main_path[0]] ?:
0411          private->comp_node[private->data->ext_path[0]];
0412     pdev = of_find_device_by_node(np);
0413     if (!pdev) {
0414         ret = -ENODEV;
0415         dev_err(drm->dev, "Need at least one OVL device\n");
0416         goto err_component_unbind;
0417     }
0418 
0419     dma_dev = &pdev->dev;
0420     private->dma_dev = dma_dev;
0421 
0422     /*
0423      * Configure the DMA segment size to make sure we get contiguous IOVA
0424      * when importing PRIME buffers.
0425      */
0426     ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
0427     if (ret) {
0428         dev_err(dma_dev, "Failed to set DMA segment size\n");
0429         goto err_component_unbind;
0430     }
0431 
0432     ret = drm_vblank_init(drm, MAX_CRTC);
0433     if (ret < 0)
0434         goto err_component_unbind;
0435 
0436     drm_kms_helper_poll_init(drm);
0437     drm_mode_config_reset(drm);
0438 
0439     return 0;
0440 
0441 err_component_unbind:
0442     component_unbind_all(drm->dev, drm);
0443 put_mutex_dev:
0444     put_device(private->mutex_dev);
0445     return ret;
0446 }
0447 
0448 static void mtk_drm_kms_deinit(struct drm_device *drm)
0449 {
0450     drm_kms_helper_poll_fini(drm);
0451     drm_atomic_helper_shutdown(drm);
0452 
0453     component_unbind_all(drm->dev, drm);
0454 }
0455 
0456 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
0457 
0458 /*
0459  * We need to override this because the device used to import the memory is
0460  * not dev->dev, as drm_gem_prime_import() expects.
0461  */
0462 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev,
0463                                struct dma_buf *dma_buf)
0464 {
0465     struct mtk_drm_private *private = dev->dev_private;
0466 
0467     return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
0468 }
0469 
0470 static const struct drm_driver mtk_drm_driver = {
0471     .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
0472 
0473     .dumb_create = mtk_drm_gem_dumb_create,
0474 
0475     .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
0476     .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
0477     .gem_prime_import = mtk_drm_gem_prime_import,
0478     .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
0479     .gem_prime_mmap = drm_gem_prime_mmap,
0480     .fops = &mtk_drm_fops,
0481 
0482     .name = DRIVER_NAME,
0483     .desc = DRIVER_DESC,
0484     .date = DRIVER_DATE,
0485     .major = DRIVER_MAJOR,
0486     .minor = DRIVER_MINOR,
0487 };
0488 
0489 static int mtk_drm_bind(struct device *dev)
0490 {
0491     struct mtk_drm_private *private = dev_get_drvdata(dev);
0492     struct drm_device *drm;
0493     int ret;
0494 
0495     drm = drm_dev_alloc(&mtk_drm_driver, dev);
0496     if (IS_ERR(drm))
0497         return PTR_ERR(drm);
0498 
0499     drm->dev_private = private;
0500     private->drm = drm;
0501 
0502     ret = mtk_drm_kms_init(drm);
0503     if (ret < 0)
0504         goto err_free;
0505 
0506     ret = drm_dev_register(drm, 0);
0507     if (ret < 0)
0508         goto err_deinit;
0509 
0510     drm_fbdev_generic_setup(drm, 32);
0511 
0512     return 0;
0513 
0514 err_deinit:
0515     mtk_drm_kms_deinit(drm);
0516 err_free:
0517     drm_dev_put(drm);
0518     return ret;
0519 }
0520 
0521 static void mtk_drm_unbind(struct device *dev)
0522 {
0523     struct mtk_drm_private *private = dev_get_drvdata(dev);
0524 
0525     drm_dev_unregister(private->drm);
0526     mtk_drm_kms_deinit(private->drm);
0527     drm_dev_put(private->drm);
0528     private->num_pipes = 0;
0529     private->drm = NULL;
0530 }
0531 
0532 static const struct component_master_ops mtk_drm_ops = {
0533     .bind       = mtk_drm_bind,
0534     .unbind     = mtk_drm_unbind,
0535 };
0536 
0537 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
0538     { .compatible = "mediatek,mt8167-disp-aal",
0539       .data = (void *)MTK_DISP_AAL},
0540     { .compatible = "mediatek,mt8173-disp-aal",
0541       .data = (void *)MTK_DISP_AAL},
0542     { .compatible = "mediatek,mt8183-disp-aal",
0543       .data = (void *)MTK_DISP_AAL},
0544     { .compatible = "mediatek,mt8192-disp-aal",
0545       .data = (void *)MTK_DISP_AAL},
0546     { .compatible = "mediatek,mt8167-disp-ccorr",
0547       .data = (void *)MTK_DISP_CCORR },
0548     { .compatible = "mediatek,mt8183-disp-ccorr",
0549       .data = (void *)MTK_DISP_CCORR },
0550     { .compatible = "mediatek,mt8192-disp-ccorr",
0551       .data = (void *)MTK_DISP_CCORR },
0552     { .compatible = "mediatek,mt2701-disp-color",
0553       .data = (void *)MTK_DISP_COLOR },
0554     { .compatible = "mediatek,mt8167-disp-color",
0555       .data = (void *)MTK_DISP_COLOR },
0556     { .compatible = "mediatek,mt8173-disp-color",
0557       .data = (void *)MTK_DISP_COLOR },
0558     { .compatible = "mediatek,mt8167-disp-dither",
0559       .data = (void *)MTK_DISP_DITHER },
0560     { .compatible = "mediatek,mt8183-disp-dither",
0561       .data = (void *)MTK_DISP_DITHER },
0562     { .compatible = "mediatek,mt8195-disp-dsc",
0563       .data = (void *)MTK_DISP_DSC },
0564     { .compatible = "mediatek,mt8167-disp-gamma",
0565       .data = (void *)MTK_DISP_GAMMA, },
0566     { .compatible = "mediatek,mt8173-disp-gamma",
0567       .data = (void *)MTK_DISP_GAMMA, },
0568     { .compatible = "mediatek,mt8183-disp-gamma",
0569       .data = (void *)MTK_DISP_GAMMA, },
0570     { .compatible = "mediatek,mt8195-disp-merge",
0571       .data = (void *)MTK_DISP_MERGE },
0572     { .compatible = "mediatek,mt2701-disp-mutex",
0573       .data = (void *)MTK_DISP_MUTEX },
0574     { .compatible = "mediatek,mt2712-disp-mutex",
0575       .data = (void *)MTK_DISP_MUTEX },
0576     { .compatible = "mediatek,mt8167-disp-mutex",
0577       .data = (void *)MTK_DISP_MUTEX },
0578     { .compatible = "mediatek,mt8173-disp-mutex",
0579       .data = (void *)MTK_DISP_MUTEX },
0580     { .compatible = "mediatek,mt8183-disp-mutex",
0581       .data = (void *)MTK_DISP_MUTEX },
0582     { .compatible = "mediatek,mt8186-disp-mutex",
0583       .data = (void *)MTK_DISP_MUTEX },
0584     { .compatible = "mediatek,mt8192-disp-mutex",
0585       .data = (void *)MTK_DISP_MUTEX },
0586     { .compatible = "mediatek,mt8195-disp-mutex",
0587       .data = (void *)MTK_DISP_MUTEX },
0588     { .compatible = "mediatek,mt8173-disp-od",
0589       .data = (void *)MTK_DISP_OD },
0590     { .compatible = "mediatek,mt2701-disp-ovl",
0591       .data = (void *)MTK_DISP_OVL },
0592     { .compatible = "mediatek,mt8167-disp-ovl",
0593       .data = (void *)MTK_DISP_OVL },
0594     { .compatible = "mediatek,mt8173-disp-ovl",
0595       .data = (void *)MTK_DISP_OVL },
0596     { .compatible = "mediatek,mt8183-disp-ovl",
0597       .data = (void *)MTK_DISP_OVL },
0598     { .compatible = "mediatek,mt8192-disp-ovl",
0599       .data = (void *)MTK_DISP_OVL },
0600     { .compatible = "mediatek,mt8183-disp-ovl-2l",
0601       .data = (void *)MTK_DISP_OVL_2L },
0602     { .compatible = "mediatek,mt8192-disp-ovl-2l",
0603       .data = (void *)MTK_DISP_OVL_2L },
0604     { .compatible = "mediatek,mt8192-disp-postmask",
0605       .data = (void *)MTK_DISP_POSTMASK },
0606     { .compatible = "mediatek,mt2701-disp-pwm",
0607       .data = (void *)MTK_DISP_BLS },
0608     { .compatible = "mediatek,mt8167-disp-pwm",
0609       .data = (void *)MTK_DISP_PWM },
0610     { .compatible = "mediatek,mt8173-disp-pwm",
0611       .data = (void *)MTK_DISP_PWM },
0612     { .compatible = "mediatek,mt2701-disp-rdma",
0613       .data = (void *)MTK_DISP_RDMA },
0614     { .compatible = "mediatek,mt8167-disp-rdma",
0615       .data = (void *)MTK_DISP_RDMA },
0616     { .compatible = "mediatek,mt8173-disp-rdma",
0617       .data = (void *)MTK_DISP_RDMA },
0618     { .compatible = "mediatek,mt8183-disp-rdma",
0619       .data = (void *)MTK_DISP_RDMA },
0620     { .compatible = "mediatek,mt8195-disp-rdma",
0621       .data = (void *)MTK_DISP_RDMA },
0622     { .compatible = "mediatek,mt8173-disp-ufoe",
0623       .data = (void *)MTK_DISP_UFOE },
0624     { .compatible = "mediatek,mt8173-disp-wdma",
0625       .data = (void *)MTK_DISP_WDMA },
0626     { .compatible = "mediatek,mt2701-dpi",
0627       .data = (void *)MTK_DPI },
0628     { .compatible = "mediatek,mt8167-dsi",
0629       .data = (void *)MTK_DSI },
0630     { .compatible = "mediatek,mt8173-dpi",
0631       .data = (void *)MTK_DPI },
0632     { .compatible = "mediatek,mt8183-dpi",
0633       .data = (void *)MTK_DPI },
0634     { .compatible = "mediatek,mt8192-dpi",
0635       .data = (void *)MTK_DPI },
0636     { .compatible = "mediatek,mt8195-dp-intf",
0637       .data = (void *)MTK_DP_INTF },
0638     { .compatible = "mediatek,mt2701-dsi",
0639       .data = (void *)MTK_DSI },
0640     { .compatible = "mediatek,mt8173-dsi",
0641       .data = (void *)MTK_DSI },
0642     { .compatible = "mediatek,mt8183-dsi",
0643       .data = (void *)MTK_DSI },
0644     { .compatible = "mediatek,mt8186-dsi",
0645       .data = (void *)MTK_DSI },
0646     { }
0647 };
0648 
0649 static const struct of_device_id mtk_drm_of_ids[] = {
0650     { .compatible = "mediatek,mt2701-mmsys",
0651       .data = &mt2701_mmsys_match_data},
0652     { .compatible = "mediatek,mt7623-mmsys",
0653       .data = &mt7623_mmsys_match_data},
0654     { .compatible = "mediatek,mt2712-mmsys",
0655       .data = &mt2712_mmsys_match_data},
0656     { .compatible = "mediatek,mt8167-mmsys",
0657       .data = &mt8167_mmsys_match_data},
0658     { .compatible = "mediatek,mt8173-mmsys",
0659       .data = &mt8173_mmsys_match_data},
0660     { .compatible = "mediatek,mt8183-mmsys",
0661       .data = &mt8183_mmsys_match_data},
0662     { .compatible = "mediatek,mt8186-mmsys",
0663       .data = &mt8186_mmsys_match_data},
0664     { .compatible = "mediatek,mt8192-mmsys",
0665       .data = &mt8192_mmsys_match_data},
0666     { .compatible = "mediatek,mt8195-mmsys",
0667       .data = &mt8195_mmsys_match_data},
0668     { }
0669 };
0670 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
0671 
0672 static int mtk_drm_find_match_data(struct device *dev,
0673                    const struct mtk_mmsys_match_data *match_data)
0674 {
0675     int i;
0676     struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
0677     struct resource *res;
0678 
0679     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0680     if (!res) {
0681         dev_err(dev, "failed to get parent resource\n");
0682         return -EINVAL;
0683     }
0684 
0685     for (i = 0; i < match_data->num_drv_data; i++)
0686         if (match_data->drv_data[i]->io_start == res->start)
0687             return i;
0688 
0689     return -EINVAL;
0690 }
0691 
0692 static int mtk_drm_probe(struct platform_device *pdev)
0693 {
0694     struct device *dev = &pdev->dev;
0695     struct device_node *phandle = dev->parent->of_node;
0696     const struct of_device_id *of_id;
0697     const struct mtk_mmsys_match_data *match_data;
0698     struct mtk_drm_private *private;
0699     struct device_node *node;
0700     struct component_match *match = NULL;
0701     int ret;
0702     int i;
0703 
0704     private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
0705     if (!private)
0706         return -ENOMEM;
0707 
0708     private->mmsys_dev = dev->parent;
0709     if (!private->mmsys_dev) {
0710         dev_err(dev, "Failed to get MMSYS device\n");
0711         return -ENODEV;
0712     }
0713 
0714     of_id = of_match_node(mtk_drm_of_ids, phandle);
0715     if (!of_id)
0716         return -ENODEV;
0717 
0718     match_data = of_id->data;
0719     if (match_data->num_drv_data > 1) {
0720         /* This SoC has multiple mmsys channels */
0721         ret = mtk_drm_find_match_data(dev, match_data);
0722         if (ret < 0) {
0723             dev_err(dev, "Couldn't get match driver data\n");
0724             return ret;
0725         }
0726         private->data = match_data->drv_data[ret];
0727     } else {
0728         dev_dbg(dev, "Using single mmsys channel\n");
0729         private->data = match_data->drv_data[0];
0730     }
0731 
0732     /* Iterate over sibling DISP function blocks */
0733     for_each_child_of_node(phandle->parent, node) {
0734         const struct of_device_id *of_id;
0735         enum mtk_ddp_comp_type comp_type;
0736         int comp_id;
0737 
0738         of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
0739         if (!of_id)
0740             continue;
0741 
0742         if (!of_device_is_available(node)) {
0743             dev_dbg(dev, "Skipping disabled component %pOF\n",
0744                 node);
0745             continue;
0746         }
0747 
0748         comp_type = (enum mtk_ddp_comp_type)of_id->data;
0749 
0750         if (comp_type == MTK_DISP_MUTEX) {
0751             private->mutex_node = of_node_get(node);
0752             continue;
0753         }
0754 
0755         comp_id = mtk_ddp_comp_get_id(node, comp_type);
0756         if (comp_id < 0) {
0757             dev_warn(dev, "Skipping unknown component %pOF\n",
0758                  node);
0759             continue;
0760         }
0761 
0762         private->comp_node[comp_id] = of_node_get(node);
0763 
0764         /*
0765          * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
0766          * blocks have separate component platform drivers and initialize their own
0767          * DDP component structure. The others are initialized here.
0768          */
0769         if (comp_type == MTK_DISP_AAL ||
0770             comp_type == MTK_DISP_CCORR ||
0771             comp_type == MTK_DISP_COLOR ||
0772             comp_type == MTK_DISP_GAMMA ||
0773             comp_type == MTK_DISP_MERGE ||
0774             comp_type == MTK_DISP_OVL ||
0775             comp_type == MTK_DISP_OVL_2L ||
0776             comp_type == MTK_DISP_RDMA ||
0777             comp_type == MTK_DP_INTF ||
0778             comp_type == MTK_DPI ||
0779             comp_type == MTK_DSI) {
0780             dev_info(dev, "Adding component match for %pOF\n",
0781                  node);
0782             drm_of_component_match_add(dev, &match, component_compare_of,
0783                            node);
0784         }
0785 
0786         ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
0787         if (ret) {
0788             of_node_put(node);
0789             goto err_node;
0790         }
0791     }
0792 
0793     if (!private->mutex_node) {
0794         dev_err(dev, "Failed to find disp-mutex node\n");
0795         ret = -ENODEV;
0796         goto err_node;
0797     }
0798 
0799     pm_runtime_enable(dev);
0800 
0801     platform_set_drvdata(pdev, private);
0802 
0803     ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
0804     if (ret)
0805         goto err_pm;
0806 
0807     return 0;
0808 
0809 err_pm:
0810     pm_runtime_disable(dev);
0811 err_node:
0812     of_node_put(private->mutex_node);
0813     for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
0814         of_node_put(private->comp_node[i]);
0815     return ret;
0816 }
0817 
0818 static int mtk_drm_remove(struct platform_device *pdev)
0819 {
0820     struct mtk_drm_private *private = platform_get_drvdata(pdev);
0821     int i;
0822 
0823     component_master_del(&pdev->dev, &mtk_drm_ops);
0824     pm_runtime_disable(&pdev->dev);
0825     of_node_put(private->mutex_node);
0826     for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
0827         of_node_put(private->comp_node[i]);
0828 
0829     return 0;
0830 }
0831 
0832 static int mtk_drm_sys_prepare(struct device *dev)
0833 {
0834     struct mtk_drm_private *private = dev_get_drvdata(dev);
0835     struct drm_device *drm = private->drm;
0836     int ret;
0837 
0838     ret = drm_mode_config_helper_suspend(drm);
0839 
0840     return ret;
0841 }
0842 
0843 static void mtk_drm_sys_complete(struct device *dev)
0844 {
0845     struct mtk_drm_private *private = dev_get_drvdata(dev);
0846     struct drm_device *drm = private->drm;
0847     int ret;
0848 
0849     ret = drm_mode_config_helper_resume(drm);
0850     if (ret)
0851         dev_err(dev, "Failed to resume\n");
0852 }
0853 
0854 static const struct dev_pm_ops mtk_drm_pm_ops = {
0855     .prepare = mtk_drm_sys_prepare,
0856     .complete = mtk_drm_sys_complete,
0857 };
0858 
0859 static struct platform_driver mtk_drm_platform_driver = {
0860     .probe  = mtk_drm_probe,
0861     .remove = mtk_drm_remove,
0862     .driver = {
0863         .name   = "mediatek-drm",
0864         .pm     = &mtk_drm_pm_ops,
0865     },
0866 };
0867 
0868 static struct platform_driver * const mtk_drm_drivers[] = {
0869     &mtk_disp_aal_driver,
0870     &mtk_disp_ccorr_driver,
0871     &mtk_disp_color_driver,
0872     &mtk_disp_gamma_driver,
0873     &mtk_disp_merge_driver,
0874     &mtk_disp_ovl_driver,
0875     &mtk_disp_rdma_driver,
0876     &mtk_dpi_driver,
0877     &mtk_drm_platform_driver,
0878     &mtk_dsi_driver,
0879     &mtk_mdp_rdma_driver,
0880 };
0881 
0882 static int __init mtk_drm_init(void)
0883 {
0884     return platform_register_drivers(mtk_drm_drivers,
0885                      ARRAY_SIZE(mtk_drm_drivers));
0886 }
0887 
0888 static void __exit mtk_drm_exit(void)
0889 {
0890     platform_unregister_drivers(mtk_drm_drivers,
0891                     ARRAY_SIZE(mtk_drm_drivers));
0892 }
0893 
0894 module_init(mtk_drm_init);
0895 module_exit(mtk_drm_exit);
0896 
0897 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
0898 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
0899 MODULE_LICENSE("GPL v2");
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