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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015 MediaTek Inc.
0004  * Authors:
0005  *  YT Shen <yt.shen@mediatek.com>
0006  *  CK Hu <ck.hu@mediatek.com>
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_platform.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/soc/mediatek/mtk-cmdq.h>
0015 #include <drm/drm_print.h>
0016 
0017 #include "mtk_disp_drv.h"
0018 #include "mtk_drm_drv.h"
0019 #include "mtk_drm_plane.h"
0020 #include "mtk_drm_ddp_comp.h"
0021 #include "mtk_drm_crtc.h"
0022 
0023 
0024 #define DISP_REG_DITHER_EN          0x0000
0025 #define DITHER_EN               BIT(0)
0026 #define DISP_REG_DITHER_CFG         0x0020
0027 #define DITHER_RELAY_MODE           BIT(0)
0028 #define DITHER_ENGINE_EN            BIT(1)
0029 #define DISP_DITHERING              BIT(2)
0030 #define DISP_REG_DITHER_SIZE            0x0030
0031 #define DISP_REG_DITHER_5           0x0114
0032 #define DISP_REG_DITHER_7           0x011c
0033 #define DISP_REG_DITHER_15          0x013c
0034 #define DITHER_LSB_ERR_SHIFT_R(x)       (((x) & 0x7) << 28)
0035 #define DITHER_ADD_LSHIFT_R(x)          (((x) & 0x7) << 20)
0036 #define DITHER_NEW_BIT_MODE         BIT(0)
0037 #define DISP_REG_DITHER_16          0x0140
0038 #define DITHER_LSB_ERR_SHIFT_B(x)       (((x) & 0x7) << 28)
0039 #define DITHER_ADD_LSHIFT_B(x)          (((x) & 0x7) << 20)
0040 #define DITHER_LSB_ERR_SHIFT_G(x)       (((x) & 0x7) << 12)
0041 #define DITHER_ADD_LSHIFT_G(x)          (((x) & 0x7) << 4)
0042 
0043 #define DISP_REG_DSC_CON            0x0000
0044 #define DSC_EN                  BIT(0)
0045 #define DSC_DUAL_INOUT              BIT(2)
0046 #define DSC_BYPASS              BIT(4)
0047 #define DSC_UFOE_SEL                BIT(16)
0048 
0049 #define DISP_REG_OD_EN              0x0000
0050 #define DISP_REG_OD_CFG             0x0020
0051 #define OD_RELAYMODE                BIT(0)
0052 #define DISP_REG_OD_SIZE            0x0030
0053 
0054 #define DISP_REG_POSTMASK_EN            0x0000
0055 #define POSTMASK_EN                 BIT(0)
0056 #define DISP_REG_POSTMASK_CFG           0x0020
0057 #define POSTMASK_RELAY_MODE             BIT(0)
0058 #define DISP_REG_POSTMASK_SIZE          0x0030
0059 
0060 #define DISP_REG_UFO_START          0x0000
0061 #define UFO_BYPASS              BIT(2)
0062 
0063 struct mtk_ddp_comp_dev {
0064     struct clk *clk;
0065     void __iomem *regs;
0066     struct cmdq_client_reg cmdq_reg;
0067 };
0068 
0069 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
0070            struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
0071            unsigned int offset)
0072 {
0073 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0074     if (cmdq_pkt)
0075         cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
0076                    cmdq_reg->offset + offset, value);
0077     else
0078 #endif
0079         writel(value, regs + offset);
0080 }
0081 
0082 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
0083                struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
0084                unsigned int offset)
0085 {
0086 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0087     if (cmdq_pkt)
0088         cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
0089                    cmdq_reg->offset + offset, value);
0090     else
0091 #endif
0092         writel_relaxed(value, regs + offset);
0093 }
0094 
0095 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
0096             struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
0097             unsigned int offset, unsigned int mask)
0098 {
0099 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0100     if (cmdq_pkt) {
0101         cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
0102                     cmdq_reg->offset + offset, value, mask);
0103     } else {
0104 #endif
0105         u32 tmp = readl(regs + offset);
0106 
0107         tmp = (tmp & ~mask) | (value & mask);
0108         writel(tmp, regs + offset);
0109 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0110     }
0111 #endif
0112 }
0113 
0114 static int mtk_ddp_clk_enable(struct device *dev)
0115 {
0116     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0117 
0118     return clk_prepare_enable(priv->clk);
0119 }
0120 
0121 static void mtk_ddp_clk_disable(struct device *dev)
0122 {
0123     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0124 
0125     clk_disable_unprepare(priv->clk);
0126 }
0127 
0128 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
0129                unsigned int bpc, unsigned int cfg,
0130                unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
0131 {
0132     /* If bpc equal to 0, the dithering function didn't be enabled */
0133     if (bpc == 0)
0134         return;
0135 
0136     if (bpc >= MTK_MIN_BPC) {
0137         mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
0138         mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
0139         mtk_ddp_write(cmdq_pkt,
0140                   DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
0141                   DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
0142                   DITHER_NEW_BIT_MODE,
0143                   cmdq_reg, regs, DISP_REG_DITHER_15);
0144         mtk_ddp_write(cmdq_pkt,
0145                   DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
0146                   DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
0147                   DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
0148                   DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
0149                   cmdq_reg, regs, DISP_REG_DITHER_16);
0150         mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
0151     }
0152 }
0153 
0154 static void mtk_dither_config(struct device *dev, unsigned int w,
0155                   unsigned int h, unsigned int vrefresh,
0156                   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
0157 {
0158     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0159 
0160     mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
0161     mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
0162               DISP_REG_DITHER_CFG);
0163     mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
0164                   DITHER_ENGINE_EN, cmdq_pkt);
0165 }
0166 
0167 static void mtk_dither_start(struct device *dev)
0168 {
0169     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0170 
0171     writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
0172 }
0173 
0174 static void mtk_dither_stop(struct device *dev)
0175 {
0176     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0177 
0178     writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
0179 }
0180 
0181 static void mtk_dither_set(struct device *dev, unsigned int bpc,
0182                unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
0183 {
0184     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0185 
0186     mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
0187                   DISP_DITHERING, cmdq_pkt);
0188 }
0189 
0190 static void mtk_dsc_config(struct device *dev, unsigned int w,
0191                unsigned int h, unsigned int vrefresh,
0192                unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
0193 {
0194     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0195 
0196     /* dsc bypass mode */
0197     mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
0198                DISP_REG_DSC_CON, DSC_BYPASS);
0199     mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
0200                DISP_REG_DSC_CON, DSC_UFOE_SEL);
0201     mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
0202                DISP_REG_DSC_CON, DSC_DUAL_INOUT);
0203 }
0204 
0205 static void mtk_dsc_start(struct device *dev)
0206 {
0207     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0208 
0209     /* write with mask to reserve the value set in mtk_dsc_config */
0210     mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
0211 }
0212 
0213 static void mtk_dsc_stop(struct device *dev)
0214 {
0215     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0216 
0217     writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
0218 }
0219 
0220 static void mtk_od_config(struct device *dev, unsigned int w,
0221               unsigned int h, unsigned int vrefresh,
0222               unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
0223 {
0224     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0225 
0226     mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
0227     mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
0228     mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
0229 }
0230 
0231 static void mtk_od_start(struct device *dev)
0232 {
0233     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0234 
0235     writel(1, priv->regs + DISP_REG_OD_EN);
0236 }
0237 
0238 static void mtk_postmask_config(struct device *dev, unsigned int w,
0239                 unsigned int h, unsigned int vrefresh,
0240                 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
0241 {
0242     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0243 
0244     mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
0245               DISP_REG_POSTMASK_SIZE);
0246     mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
0247               priv->regs, DISP_REG_POSTMASK_CFG);
0248 }
0249 
0250 static void mtk_postmask_start(struct device *dev)
0251 {
0252     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0253 
0254     writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
0255 }
0256 
0257 static void mtk_postmask_stop(struct device *dev)
0258 {
0259     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0260 
0261     writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
0262 }
0263 
0264 static void mtk_ufoe_start(struct device *dev)
0265 {
0266     struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
0267 
0268     writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
0269 }
0270 
0271 static const struct mtk_ddp_comp_funcs ddp_aal = {
0272     .clk_enable = mtk_aal_clk_enable,
0273     .clk_disable = mtk_aal_clk_disable,
0274     .gamma_set = mtk_aal_gamma_set,
0275     .config = mtk_aal_config,
0276     .start = mtk_aal_start,
0277     .stop = mtk_aal_stop,
0278 };
0279 
0280 static const struct mtk_ddp_comp_funcs ddp_ccorr = {
0281     .clk_enable = mtk_ccorr_clk_enable,
0282     .clk_disable = mtk_ccorr_clk_disable,
0283     .config = mtk_ccorr_config,
0284     .start = mtk_ccorr_start,
0285     .stop = mtk_ccorr_stop,
0286     .ctm_set = mtk_ccorr_ctm_set,
0287 };
0288 
0289 static const struct mtk_ddp_comp_funcs ddp_color = {
0290     .clk_enable = mtk_color_clk_enable,
0291     .clk_disable = mtk_color_clk_disable,
0292     .config = mtk_color_config,
0293     .start = mtk_color_start,
0294 };
0295 
0296 static const struct mtk_ddp_comp_funcs ddp_dither = {
0297     .clk_enable = mtk_ddp_clk_enable,
0298     .clk_disable = mtk_ddp_clk_disable,
0299     .config = mtk_dither_config,
0300     .start = mtk_dither_start,
0301     .stop = mtk_dither_stop,
0302 };
0303 
0304 static const struct mtk_ddp_comp_funcs ddp_dpi = {
0305     .start = mtk_dpi_start,
0306     .stop = mtk_dpi_stop,
0307 };
0308 
0309 static const struct mtk_ddp_comp_funcs ddp_dsc = {
0310     .clk_enable = mtk_ddp_clk_enable,
0311     .clk_disable = mtk_ddp_clk_disable,
0312     .config = mtk_dsc_config,
0313     .start = mtk_dsc_start,
0314     .stop = mtk_dsc_stop,
0315 };
0316 
0317 static const struct mtk_ddp_comp_funcs ddp_dsi = {
0318     .start = mtk_dsi_ddp_start,
0319     .stop = mtk_dsi_ddp_stop,
0320 };
0321 
0322 static const struct mtk_ddp_comp_funcs ddp_gamma = {
0323     .clk_enable = mtk_gamma_clk_enable,
0324     .clk_disable = mtk_gamma_clk_disable,
0325     .gamma_set = mtk_gamma_set,
0326     .config = mtk_gamma_config,
0327     .start = mtk_gamma_start,
0328     .stop = mtk_gamma_stop,
0329 };
0330 
0331 static const struct mtk_ddp_comp_funcs ddp_merge = {
0332     .clk_enable = mtk_merge_clk_enable,
0333     .clk_disable = mtk_merge_clk_disable,
0334     .start = mtk_merge_start,
0335     .stop = mtk_merge_stop,
0336     .config = mtk_merge_config,
0337 };
0338 
0339 static const struct mtk_ddp_comp_funcs ddp_od = {
0340     .clk_enable = mtk_ddp_clk_enable,
0341     .clk_disable = mtk_ddp_clk_disable,
0342     .config = mtk_od_config,
0343     .start = mtk_od_start,
0344 };
0345 
0346 static const struct mtk_ddp_comp_funcs ddp_ovl = {
0347     .clk_enable = mtk_ovl_clk_enable,
0348     .clk_disable = mtk_ovl_clk_disable,
0349     .config = mtk_ovl_config,
0350     .start = mtk_ovl_start,
0351     .stop = mtk_ovl_stop,
0352     .register_vblank_cb = mtk_ovl_register_vblank_cb,
0353     .unregister_vblank_cb = mtk_ovl_unregister_vblank_cb,
0354     .enable_vblank = mtk_ovl_enable_vblank,
0355     .disable_vblank = mtk_ovl_disable_vblank,
0356     .supported_rotations = mtk_ovl_supported_rotations,
0357     .layer_nr = mtk_ovl_layer_nr,
0358     .layer_check = mtk_ovl_layer_check,
0359     .layer_config = mtk_ovl_layer_config,
0360     .bgclr_in_on = mtk_ovl_bgclr_in_on,
0361     .bgclr_in_off = mtk_ovl_bgclr_in_off,
0362 };
0363 
0364 static const struct mtk_ddp_comp_funcs ddp_postmask = {
0365     .clk_enable = mtk_ddp_clk_enable,
0366     .clk_disable = mtk_ddp_clk_disable,
0367     .config = mtk_postmask_config,
0368     .start = mtk_postmask_start,
0369     .stop = mtk_postmask_stop,
0370 };
0371 
0372 static const struct mtk_ddp_comp_funcs ddp_rdma = {
0373     .clk_enable = mtk_rdma_clk_enable,
0374     .clk_disable = mtk_rdma_clk_disable,
0375     .config = mtk_rdma_config,
0376     .start = mtk_rdma_start,
0377     .stop = mtk_rdma_stop,
0378     .register_vblank_cb = mtk_rdma_register_vblank_cb,
0379     .unregister_vblank_cb = mtk_rdma_unregister_vblank_cb,
0380     .enable_vblank = mtk_rdma_enable_vblank,
0381     .disable_vblank = mtk_rdma_disable_vblank,
0382     .layer_nr = mtk_rdma_layer_nr,
0383     .layer_config = mtk_rdma_layer_config,
0384 };
0385 
0386 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
0387     .clk_enable = mtk_ddp_clk_enable,
0388     .clk_disable = mtk_ddp_clk_disable,
0389     .start = mtk_ufoe_start,
0390 };
0391 
0392 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
0393     [MTK_DISP_AAL] = "aal",
0394     [MTK_DISP_BLS] = "bls",
0395     [MTK_DISP_CCORR] = "ccorr",
0396     [MTK_DISP_COLOR] = "color",
0397     [MTK_DISP_DITHER] = "dither",
0398     [MTK_DISP_DSC] = "dsc",
0399     [MTK_DISP_GAMMA] = "gamma",
0400     [MTK_DISP_MERGE] = "merge",
0401     [MTK_DISP_MUTEX] = "mutex",
0402     [MTK_DISP_OD] = "od",
0403     [MTK_DISP_OVL] = "ovl",
0404     [MTK_DISP_OVL_2L] = "ovl-2l",
0405     [MTK_DISP_POSTMASK] = "postmask",
0406     [MTK_DISP_PWM] = "pwm",
0407     [MTK_DISP_RDMA] = "rdma",
0408     [MTK_DISP_UFOE] = "ufoe",
0409     [MTK_DISP_WDMA] = "wdma",
0410     [MTK_DP_INTF] = "dp-intf",
0411     [MTK_DPI] = "dpi",
0412     [MTK_DSI] = "dsi",
0413 };
0414 
0415 struct mtk_ddp_comp_match {
0416     enum mtk_ddp_comp_type type;
0417     int alias_id;
0418     const struct mtk_ddp_comp_funcs *funcs;
0419 };
0420 
0421 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
0422     [DDP_COMPONENT_AAL0]        = { MTK_DISP_AAL,   0, &ddp_aal },
0423     [DDP_COMPONENT_AAL1]        = { MTK_DISP_AAL,   1, &ddp_aal },
0424     [DDP_COMPONENT_BLS]     = { MTK_DISP_BLS,   0, NULL },
0425     [DDP_COMPONENT_CCORR]       = { MTK_DISP_CCORR, 0, &ddp_ccorr },
0426     [DDP_COMPONENT_COLOR0]      = { MTK_DISP_COLOR, 0, &ddp_color },
0427     [DDP_COMPONENT_COLOR1]      = { MTK_DISP_COLOR, 1, &ddp_color },
0428     [DDP_COMPONENT_DITHER0]     = { MTK_DISP_DITHER,    0, &ddp_dither },
0429     [DDP_COMPONENT_DP_INTF0]    = { MTK_DP_INTF,    0, &ddp_dpi },
0430     [DDP_COMPONENT_DP_INTF1]    = { MTK_DP_INTF,    1, &ddp_dpi },
0431     [DDP_COMPONENT_DPI0]        = { MTK_DPI,        0, &ddp_dpi },
0432     [DDP_COMPONENT_DPI1]        = { MTK_DPI,        1, &ddp_dpi },
0433     [DDP_COMPONENT_DSC0]        = { MTK_DISP_DSC,   0, &ddp_dsc },
0434     [DDP_COMPONENT_DSC1]        = { MTK_DISP_DSC,   1, &ddp_dsc },
0435     [DDP_COMPONENT_DSI0]        = { MTK_DSI,        0, &ddp_dsi },
0436     [DDP_COMPONENT_DSI1]        = { MTK_DSI,        1, &ddp_dsi },
0437     [DDP_COMPONENT_DSI2]        = { MTK_DSI,        2, &ddp_dsi },
0438     [DDP_COMPONENT_DSI3]        = { MTK_DSI,        3, &ddp_dsi },
0439     [DDP_COMPONENT_GAMMA]       = { MTK_DISP_GAMMA, 0, &ddp_gamma },
0440     [DDP_COMPONENT_MERGE0]      = { MTK_DISP_MERGE, 0, &ddp_merge },
0441     [DDP_COMPONENT_MERGE1]      = { MTK_DISP_MERGE, 1, &ddp_merge },
0442     [DDP_COMPONENT_MERGE2]      = { MTK_DISP_MERGE, 2, &ddp_merge },
0443     [DDP_COMPONENT_MERGE3]      = { MTK_DISP_MERGE, 3, &ddp_merge },
0444     [DDP_COMPONENT_MERGE4]      = { MTK_DISP_MERGE, 4, &ddp_merge },
0445     [DDP_COMPONENT_MERGE5]      = { MTK_DISP_MERGE, 5, &ddp_merge },
0446     [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,    0, &ddp_od },
0447     [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,    1, &ddp_od },
0448     [DDP_COMPONENT_OVL0]        = { MTK_DISP_OVL,   0, &ddp_ovl },
0449     [DDP_COMPONENT_OVL1]        = { MTK_DISP_OVL,   1, &ddp_ovl },
0450     [DDP_COMPONENT_OVL_2L0]     = { MTK_DISP_OVL_2L,    0, &ddp_ovl },
0451     [DDP_COMPONENT_OVL_2L1]     = { MTK_DISP_OVL_2L,    1, &ddp_ovl },
0452     [DDP_COMPONENT_OVL_2L2]     = { MTK_DISP_OVL_2L,    2, &ddp_ovl },
0453     [DDP_COMPONENT_POSTMASK0]   = { MTK_DISP_POSTMASK,  0, &ddp_postmask },
0454     [DDP_COMPONENT_PWM0]        = { MTK_DISP_PWM,   0, NULL },
0455     [DDP_COMPONENT_PWM1]        = { MTK_DISP_PWM,   1, NULL },
0456     [DDP_COMPONENT_PWM2]        = { MTK_DISP_PWM,   2, NULL },
0457     [DDP_COMPONENT_RDMA0]       = { MTK_DISP_RDMA,  0, &ddp_rdma },
0458     [DDP_COMPONENT_RDMA1]       = { MTK_DISP_RDMA,  1, &ddp_rdma },
0459     [DDP_COMPONENT_RDMA2]       = { MTK_DISP_RDMA,  2, &ddp_rdma },
0460     [DDP_COMPONENT_RDMA4]       = { MTK_DISP_RDMA,      4, &ddp_rdma },
0461     [DDP_COMPONENT_UFOE]        = { MTK_DISP_UFOE,  0, &ddp_ufoe },
0462     [DDP_COMPONENT_WDMA0]       = { MTK_DISP_WDMA,  0, NULL },
0463     [DDP_COMPONENT_WDMA1]       = { MTK_DISP_WDMA,  1, NULL },
0464 };
0465 
0466 static bool mtk_drm_find_comp_in_ddp(struct device *dev,
0467                      const enum mtk_ddp_comp_id *path,
0468                      unsigned int path_len,
0469                      struct mtk_ddp_comp *ddp_comp)
0470 {
0471     unsigned int i;
0472 
0473     if (path == NULL)
0474         return false;
0475 
0476     for (i = 0U; i < path_len; i++)
0477         if (dev == ddp_comp[path[i]].dev)
0478             return true;
0479 
0480     return false;
0481 }
0482 
0483 int mtk_ddp_comp_get_id(struct device_node *node,
0484             enum mtk_ddp_comp_type comp_type)
0485 {
0486     int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
0487     int i;
0488 
0489     for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
0490         if (comp_type == mtk_ddp_matches[i].type &&
0491             (id < 0 || id == mtk_ddp_matches[i].alias_id))
0492             return i;
0493     }
0494 
0495     return -EINVAL;
0496 }
0497 
0498 unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
0499                         struct device *dev)
0500 {
0501     struct mtk_drm_private *private = drm->dev_private;
0502     unsigned int ret = 0;
0503 
0504     if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len,
0505                      private->ddp_comp))
0506         ret = BIT(0);
0507     else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
0508                       private->data->ext_len, private->ddp_comp))
0509         ret = BIT(1);
0510     else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
0511                       private->data->third_len, private->ddp_comp))
0512         ret = BIT(2);
0513     else
0514         DRM_INFO("Failed to find comp in ddp table\n");
0515 
0516     return ret;
0517 }
0518 
0519 int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
0520               enum mtk_ddp_comp_id comp_id)
0521 {
0522     struct platform_device *comp_pdev;
0523     enum mtk_ddp_comp_type type;
0524     struct mtk_ddp_comp_dev *priv;
0525 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0526     int ret;
0527 #endif
0528 
0529     if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
0530         return -EINVAL;
0531 
0532     type = mtk_ddp_matches[comp_id].type;
0533 
0534     comp->id = comp_id;
0535     comp->funcs = mtk_ddp_matches[comp_id].funcs;
0536     comp_pdev = of_find_device_by_node(node);
0537     if (!comp_pdev) {
0538         DRM_INFO("Waiting for device %s\n", node->full_name);
0539         return -EPROBE_DEFER;
0540     }
0541     comp->dev = &comp_pdev->dev;
0542 
0543     if (type == MTK_DISP_AAL ||
0544         type == MTK_DISP_BLS ||
0545         type == MTK_DISP_CCORR ||
0546         type == MTK_DISP_COLOR ||
0547         type == MTK_DISP_GAMMA ||
0548         type == MTK_DISP_MERGE ||
0549         type == MTK_DISP_OVL ||
0550         type == MTK_DISP_OVL_2L ||
0551         type == MTK_DISP_PWM ||
0552         type == MTK_DISP_RDMA ||
0553         type == MTK_DPI ||
0554         type == MTK_DP_INTF ||
0555         type == MTK_DSI)
0556         return 0;
0557 
0558     priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
0559     if (!priv)
0560         return -ENOMEM;
0561 
0562     priv->regs = of_iomap(node, 0);
0563     priv->clk = of_clk_get(node, 0);
0564     if (IS_ERR(priv->clk))
0565         return PTR_ERR(priv->clk);
0566 
0567 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0568     ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
0569     if (ret)
0570         dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
0571 #endif
0572 
0573     platform_set_drvdata(comp_pdev, priv);
0574 
0575     return 0;
0576 }
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